| 1 | /* |
| 2 | * ADM5120 interrupt controller definitions |
| 3 | * |
| 4 | * This header file defines the hardware registers of the ADM5120 SoC |
| 5 | * built-in interrupt controller. |
| 6 | * |
| 7 | * Copyright (C) 2007-2008 Gabor Juhos <juhosg@openwrt.org> |
| 8 | * |
| 9 | * This program is free software; you can redistribute it and/or modify it |
| 10 | * under the terms of the GNU General Public License version 2 as published |
| 11 | * by the Free Software Foundation. |
| 12 | * |
| 13 | */ |
| 14 | |
| 15 | #ifndef _MACH_ADM5120_INTC_H |
| 16 | #define _MACH_ADM5120_INTC_H |
| 17 | |
| 18 | /* |
| 19 | * INTC register offsets |
| 20 | */ |
| 21 | #define INTC_REG_IRQ_STATUS 0x00 /* Interrupt status after masking */ |
| 22 | #define INTC_REG_IRQ_RAW_STATUS 0x04 /* Interrupt status before masking */ |
| 23 | #define INTC_REG_IRQ_ENABLE 0x08 /* Used to enable the interrupt sources */ |
| 24 | #define INTC_REG_IRQ_ENABLE_CLEAR 0x0C /* Used to disable the interrupt sources */ |
| 25 | #define INTC_REG_IRQ_DISABLE INTC_REG_IRQ_ENABLE_CLEAR |
| 26 | #define INTC_REG_INT_MODE 0x14 /* The interrupt mode of the sources */ |
| 27 | #define INTC_REG_FIQ_STATUS 0x18 /* FIQ status */ |
| 28 | #define INTC_REG_IRQ_TEST_SOURCE 0x1C |
| 29 | #define INTC_REG_IRQ_SOURCE_SELECT 0x20 |
| 30 | #define INTC_REG_INT_LEVEL 0x24 |
| 31 | |
| 32 | /* |
| 33 | * INTC IRQ numbers |
| 34 | */ |
| 35 | #define INTC_IRQ_TIMER 0 /* built in timer */ |
| 36 | #define INTC_IRQ_UART0 1 /* built-in UART0 */ |
| 37 | #define INTC_IRQ_UART1 2 /* built-in UART1 */ |
| 38 | #define INTC_IRQ_USBC 3 /* USB Host Controller */ |
| 39 | #define INTC_IRQ_GPIO2 4 /* GPIO line 2 */ |
| 40 | #define INTC_IRQ_GPIO4 5 /* GPIO line 4 */ |
| 41 | #define INTC_IRQ_PCI0 6 /* PCI slot 2 */ |
| 42 | #define INTC_IRQ_PCI1 7 /* PCI slot 3 */ |
| 43 | #define INTC_IRQ_PCI2 8 /* PCI slot 4 */ |
| 44 | #define INTC_IRQ_SWITCH 9 /* built-in ethernet switch */ |
| 45 | #define INTC_IRQ_LAST INTC_IRQ_SWITCH |
| 46 | #define INTC_IRQ_COUNT 10 |
| 47 | |
| 48 | /* |
| 49 | * INTC register bits |
| 50 | */ |
| 51 | #define INTC_INT_TIMER (1 << INTC_IRQ_TIMER) |
| 52 | #define INTC_INT_UART0 (1 << INTC_IRQ_UART0) |
| 53 | #define INTC_INT_UART1 (1 << INTC_IRQ_UART1) |
| 54 | #define INTC_INT_USBC (1 << INTC_IRQ_USBC) |
| 55 | #define INTC_INT_INTX0 (1 << INTC_IRQ_INTX0) |
| 56 | #define INTC_INT_INTX1 (1 << INTC_IRQ_INTX1) |
| 57 | #define INTC_INT_PCI0 (1 << INTC_IRQ_PCI0) |
| 58 | #define INTC_INT_PCI1 (1 << INTC_IRQ_PCI1) |
| 59 | #define INTC_INT_PCI2 (1 << INTC_IRQ_PCI2) |
| 60 | #define INTC_INT_SWITCH (1 << INTC_IRQ_SWITCH) |
| 61 | #define INTC_INT_ALL ((1 << INTC_IRQ_COUNT) - 1) |
| 62 | |
| 63 | #endif /* _MACH_ADM5120_INTC_H */ |
| 64 | |
