| 1 | /* |
| 2 | * ADM8668 minimal clock support |
| 3 | * |
| 4 | * Copyright (C) 2012, Florian Fainelli <florian@openwrt.org> |
| 5 | * |
| 6 | * Licensed under the terms of the GPLv2 |
| 7 | */ |
| 8 | |
| 9 | #include <linux/kernel.h> |
| 10 | #include <linux/module.h> |
| 11 | #include <linux/device.h> |
| 12 | #include <linux/err.h> |
| 13 | #include <linux/clk.h> |
| 14 | |
| 15 | #include <adm8668.h> |
| 16 | |
| 17 | struct clk { |
| 18 | unsigned long rate; |
| 19 | }; |
| 20 | |
| 21 | static struct clk uart_clk = { |
| 22 | .rate = 62500000, |
| 23 | }; |
| 24 | |
| 25 | static struct clk sys_clk; |
| 26 | |
| 27 | struct clk *clk_get(struct device *dev, const char *id) |
| 28 | { |
| 29 | const char *lookup = id; |
| 30 | |
| 31 | if (dev) |
| 32 | lookup = dev_name(dev); |
| 33 | |
| 34 | if (!strcmp(lookup, "apb:uart0")) |
| 35 | return &uart_clk; |
| 36 | if (!strcmp(lookup, "sys")) |
| 37 | return &sys_clk; |
| 38 | |
| 39 | return ERR_PTR(-ENOENT); |
| 40 | } |
| 41 | EXPORT_SYMBOL(clk_get); |
| 42 | |
| 43 | int clk_enable(struct clk *clk) |
| 44 | { |
| 45 | return 0; |
| 46 | } |
| 47 | EXPORT_SYMBOL(clk_enable); |
| 48 | |
| 49 | void clk_disable(struct clk *clk) |
| 50 | { |
| 51 | } |
| 52 | EXPORT_SYMBOL(clk_disable); |
| 53 | |
| 54 | unsigned long clk_get_rate(struct clk *clk) |
| 55 | { |
| 56 | return clk->rate; |
| 57 | } |
| 58 | EXPORT_SYMBOL(clk_get_rate); |
| 59 | |
| 60 | void clk_put(struct clk *clk) |
| 61 | { |
| 62 | } |
| 63 | EXPORT_SYMBOL(clk_put); |
| 64 | |
| 65 | void __init adm8668_init_clocks(void) |
| 66 | { |
| 67 | u32 adj; |
| 68 | |
| 69 | /* adjustable clock selection |
| 70 | * CR3 bit 14~11, 0000 -> 175MHz, 0001 -> 180MHz, etc... |
| 71 | */ |
| 72 | adj = (ADM8668_CONFIG_REG(ADM8668_CR3) >> 11) & 0xf; |
| 73 | sys_clk.rate = 175000000 + (adj * 5000000); |
| 74 | |
| 75 | pr_info("ADM8668 CPU clock: %lu MHz\n", sys_clk.rate / 1000000); |
| 76 | } |
| 77 | |
