| 1 | #ifndef AMAZON_H |
| 2 | #define AMAZON_H |
| 3 | /****************************************************************************** |
| 4 | Copyright (c) 2002, Infineon Technologies. All rights reserved. |
| 5 | |
| 6 | No Warranty |
| 7 | Because the program is licensed free of charge, there is no warranty for |
| 8 | the program, to the extent permitted by applicable law. Except when |
| 9 | otherwise stated in writing the copyright holders and/or other parties |
| 10 | provide the program "as is" without warranty of any kind, either |
| 11 | expressed or implied, including, but not limited to, the implied |
| 12 | warranties of merchantability and fitness for a particular purpose. The |
| 13 | entire risk as to the quality and performance of the program is with |
| 14 | you. should the program prove defective, you assume the cost of all |
| 15 | necessary servicing, repair or correction. |
| 16 | |
| 17 | In no event unless required by applicable law or agreed to in writing |
| 18 | will any copyright holder, or any other party who may modify and/or |
| 19 | redistribute the program as permitted above, be liable to you for |
| 20 | damages, including any general, special, incidental or consequential |
| 21 | damages arising out of the use or inability to use the program |
| 22 | (including but not limited to loss of data or data being rendered |
| 23 | inaccurate or losses sustained by you or third parties or a failure of |
| 24 | the program to operate with any other programs), even if such holder or |
| 25 | other party has been advised of the possibility of such damages. |
| 26 | ******************************************************************************/ |
| 27 | |
| 28 | #define amazon_readl(a) __raw_readl(((u32*)(a))) |
| 29 | #define amazon_writel(a,b) __raw_writel(a, ((u32*)(b))) |
| 30 | #define amazon_writel_masked(a,b,c) __raw_writel((__raw_readl(((u32*)(a))) & ~b) | (c & b), ((u32*)(a))) |
| 31 | |
| 32 | unsigned int amazon_get_fpi_hz(void); |
| 33 | |
| 34 | #define IOPORT_RESOURCE_START 0x10000000 |
| 35 | #define IOPORT_RESOURCE_END 0xffffffff |
| 36 | #define IOMEM_RESOURCE_START 0x10000000 |
| 37 | #define IOMEM_RESOURCE_END 0xffffffff |
| 38 | |
| 39 | /* check ADSL link status */ |
| 40 | #define AMAZON_CHECK_LINK |
| 41 | |
| 42 | /***********************************************************************/ |
| 43 | /* Module : WDT register address and bits */ |
| 44 | /***********************************************************************/ |
| 45 | |
| 46 | #define AMAZON_WDT (KSEG1+0x10100900) |
| 47 | /***********************************************************************/ |
| 48 | |
| 49 | /***Reset Request Register***/ |
| 50 | #define AMAZON_RST_REQ ((volatile u32*)(AMAZON_WDT+ 0x0010)) |
| 51 | #define AMAZON_RST_REQ_PLL (1 << 31) |
| 52 | #define AMAZON_RST_REQ_PCI_CORE (1 << 13) |
| 53 | #define AMAZON_RST_REQ_TPE (1 << 12) |
| 54 | #define AMAZON_RST_REQ_AFE (1 << 11) |
| 55 | #define AMAZON_RST_REQ_DMA (1 << 9) |
| 56 | #define AMAZON_RST_REQ_SWITCH (1 << 8) |
| 57 | #define AMAZON_RST_REQ_DFE (1 << 7) |
| 58 | #define AMAZON_RST_REQ_PHY (1 << 5) |
| 59 | #define AMAZON_RST_REQ_PCI (1 << 4) |
| 60 | #define AMAZON_RST_REQ_FPI (1 << 2) |
| 61 | #define AMAZON_RST_REQ_CPU (1 << 1) |
| 62 | #define AMAZON_RST_REQ_HRST (1 << 0) |
| 63 | #define AMAZON_RST_ALL (AMAZON_RST_REQ_PLL \ |
| 64 | |AMAZON_RST_REQ_PCI_CORE \ |
| 65 | |AMAZON_RST_REQ_TPE \ |
| 66 | |AMAZON_RST_REQ_AFE \ |
| 67 | |AMAZON_RST_REQ_DMA \ |
| 68 | |AMAZON_RST_REQ_SWITCH \ |
| 69 | |AMAZON_RST_REQ_DFE \ |
| 70 | |AMAZON_RST_REQ_PHY \ |
| 71 | |AMAZON_RST_REQ_PCI \ |
| 72 | |AMAZON_RST_REQ_FPI \ |
| 73 | |AMAZON_RST_REQ_CPU \ |
| 74 | |AMAZON_RST_REQ_HRST) |
| 75 | |
| 76 | /***Reset Status Register Power On***/ |
| 77 | #define AMAZON_RST_SR ((volatile u32*)(AMAZON_WDT+ 0x0014)) |
| 78 | |
| 79 | /***Watchdog Timer Control Register 0***/ |
| 80 | #define AMAZON_WDT_CON0 ((volatile u32*)(AMAZON_WDT+ 0x0020)) |
| 81 | |
| 82 | /***Watchdog Timer Control Register 1***/ |
| 83 | #define AMAZON_WDT_CON1 ((volatile u32*)(AMAZON_WDT+ 0x0024)) |
| 84 | #define AMAZON_WDT_CON1_WDTDR (1 << 3) |
| 85 | #define AMAZON_WDT_CON1_WDTIR (1 << 2) |
| 86 | |
| 87 | /***Watchdog Timer Status Register***/ |
| 88 | #define AMAZON_WDT_SR ((volatile u32*)(AMAZON_WDT+ 0x0028)) |
| 89 | #define AMAZON_WDT_SR_WDTTIM(value) (((( 1 << 16) - 1) & (value)) << 16) |
| 90 | #define AMAZON_WDT_SR_WDTPR (1 << 5) |
| 91 | #define AMAZON_WDT_SR_WDTTO (1 << 4) |
| 92 | #define AMAZON_WDT_SR_WDTDS (1 << 3) |
| 93 | #define AMAZON_WDT_SR_WDTIS (1 << 2) |
| 94 | #define AMAZON_WDT_SR_WDTOE (1 << 1) |
| 95 | #define AMAZON_WDT_SR_WDTAE (1 << 0) |
| 96 | |
| 97 | /***NMI Status Register***/ |
| 98 | #define AMAZON_WDT_NMISR ((volatile u32*)(AMAZON_WDT+ 0x002C)) |
| 99 | #define AMAZON_WDT_NMISR_NMIWDT (1 << 2) |
| 100 | #define AMAZON_WDT_NMISR_NMIPLL (1 << 1) |
| 101 | #define AMAZON_WDT_NMISR_NMIEXT (1 << 0) |
| 102 | |
| 103 | #define AMAZON_WDT_RST_MON ((volatile u32*)(AMAZON_WDT+ 0x0030)) |
| 104 | |
| 105 | /***********************************************************************/ |
| 106 | /* Module : MCD register address and bits */ |
| 107 | /***********************************************************************/ |
| 108 | #define AMAZON_MCD (KSEG1+0x1F106000) |
| 109 | |
| 110 | /***Manufacturer Identification Register***/ |
| 111 | #define AMAZON_MCD_MANID ((volatile u32*)(AMAZON_MCD+ 0x0024)) |
| 112 | #define AMAZON_MCD_MANID_MANUF(value) (((( 1 << 11) - 1) & (value)) << 5) |
| 113 | |
| 114 | /***Chip Identification Register***/ |
| 115 | #define AMAZON_MCD_CHIPID ((volatile u32*)(AMAZON_MCD+ 0x0028)) |
| 116 | #define AMAZON_MCD_CHIPID_VERSION_GET(value) (((value) >> 28) & ((1 << 4) - 1)) |
| 117 | #define AMAZON_MCD_CHIPID_VERSION_SET(value) (((( 1 << 4) - 1) & (value)) << 28) |
| 118 | #define AMAZON_MCD_CHIPID_PART_NUMBER_GET(value) (((value) >> 12) & ((1 << 16) - 1)) |
| 119 | #define AMAZON_MCD_CHIPID_PART_NUMBER_SET(value) (((( 1 << 16) - 1) & (value)) << 12) |
| 120 | #define AMAZON_MCD_CHIPID_MANID_GET(value) (((value) >> 1) & ((1 << 11) - 1)) |
| 121 | #define AMAZON_MCD_CHIPID_MANID_SET(value) (((( 1 << 11) - 1) & (value)) << 1) |
| 122 | |
| 123 | #define AMAZON_CHIPID_STANDARD 0x00EB |
| 124 | #define AMAZON_CHIPID_YANGTSE 0x00ED |
| 125 | |
| 126 | /***Redesign Tracing Identification Register***/ |
| 127 | #define AMAZON_MCD_RTID ((volatile u32*)(AMAZON_MCD+ 0x002C)) |
| 128 | #define AMAZON_MCD_RTID_LC (1 << 15) |
| 129 | #define AMAZON_MCD_RTID_RIX(value) (((( 1 << 3) - 1) & (value)) << 0) |
| 130 | |
| 131 | |
| 132 | /***********************************************************************/ |
| 133 | /* Module : CGU register address and bits */ |
| 134 | /***********************************************************************/ |
| 135 | |
| 136 | #define AMAZON_CGU (KSEG1+0x1F103000) |
| 137 | /***********************************************************************/ |
| 138 | |
| 139 | /***CGU Clock Divider Select Register***/ |
| 140 | #define AMAZON_CGU_DIV (AMAZON_CGU + 0x0000) |
| 141 | /***CGU PLL0 Status Register***/ |
| 142 | #define AMAZON_CGU_PLL0SR (AMAZON_CGU + 0x0004) |
| 143 | /***CGU PLL1 Status Register***/ |
| 144 | #define AMAZON_CGU_PLL1SR (AMAZON_CGU + 0x0008) |
| 145 | /***CGU Interface Clock Control Register***/ |
| 146 | #define AMAZON_CGU_IFCCR (AMAZON_CGU + 0x000c) |
| 147 | /***CGU Oscillator Control Register***/ |
| 148 | #define AMAZON_CGU_OSCCR (AMAZON_CGU + 0x0010) |
| 149 | /***CGU Memory Clock Delay Register***/ |
| 150 | #define AMAZON_CGU_MCDEL (AMAZON_CGU + 0x0014) |
| 151 | /***CGU CPU Clock Reduction Register***/ |
| 152 | #define AMAZON_CGU_CPUCRD (AMAZON_CGU + 0x0018) |
| 153 | /***CGU Test Register**/ |
| 154 | #define AMAZON_CGU_TST (AMAZON_CGU + 0x003c) |
| 155 | |
| 156 | /***********************************************************************/ |
| 157 | /* Module : PMU register address and bits */ |
| 158 | /***********************************************************************/ |
| 159 | |
| 160 | #define AMAZON_PMU AMAZON_CGU |
| 161 | /***********************************************************************/ |
| 162 | |
| 163 | |
| 164 | /***PMU Power Down Control Register***/ |
| 165 | #define AMAZON_PMU_PWDCR ((volatile u32*)(AMAZON_PMU+ 0x001c)) |
| 166 | #define AMAZON_PMU_PWDCR_TPE (1 << 13) |
| 167 | #define AMAZON_PMU_PWDCR_PLL (1 << 12) |
| 168 | #define AMAZON_PMU_PWDCR_XTAL (1 << 11) |
| 169 | #define AMAZON_PMU_PWDCR_EBU (1 << 10) |
| 170 | #define AMAZON_PMU_PWDCR_DFE (1 << 9) |
| 171 | #define AMAZON_PMU_PWDCR_SPI (1 << 8) |
| 172 | #define AMAZON_PMU_PWDCR_UART (1 << 7) |
| 173 | #define AMAZON_PMU_PWDCR_GPT (1 << 6) |
| 174 | #define AMAZON_PMU_PWDCR_DMA (1 << 5) |
| 175 | #define AMAZON_PMU_PWDCR_PCI (1 << 4) |
| 176 | #define AMAZON_PMU_PWDCR_SW (1 << 3) |
| 177 | #define AMAZON_PMU_PWDCR_IOR (1 << 2) |
| 178 | #define AMAZON_PMU_PWDCR_FPI (1 << 1) |
| 179 | #define AMAZON_PMU_PWDCR_EPHY (1 << 0) |
| 180 | |
| 181 | /***PMU Status Register***/ |
| 182 | #define AMAZON_PMU_SR ((volatile u32*)(AMAZON_PMU+ 0x0020)) |
| 183 | #define AMAZON_PMU_SR_TPE (1 << 13) |
| 184 | #define AMAZON_PMU_SR_PLL (1 << 12) |
| 185 | #define AMAZON_PMU_SR_XTAL (1 << 11) |
| 186 | #define AMAZON_PMU_SR_EBU (1 << 10) |
| 187 | #define AMAZON_PMU_SR_DFE (1 << 9) |
| 188 | #define AMAZON_PMU_SR_SPI (1 << 8) |
| 189 | #define AMAZON_PMU_SR_UART (1 << 7) |
| 190 | #define AMAZON_PMU_SR_GPT (1 << 6) |
| 191 | #define AMAZON_PMU_SR_DMA (1 << 5) |
| 192 | #define AMAZON_PMU_SR_PCI (1 << 4) |
| 193 | #define AMAZON_PMU_SR_SW (1 << 3) |
| 194 | #define AMAZON_PMU_SR_IOR (1 << 2) |
| 195 | #define AMAZON_PMU_SR_FPI (1 << 1) |
| 196 | #define AMAZON_PMU_SR_EPHY (1 << 0) |
| 197 | |
| 198 | /***********************************************************************/ |
| 199 | /* Module : BCU register address and bits */ |
| 200 | /***********************************************************************/ |
| 201 | |
| 202 | #define AMAZON_BCU (KSEG1+0x10100000) |
| 203 | /***********************************************************************/ |
| 204 | |
| 205 | |
| 206 | /***BCU Control Register (0010H)***/ |
| 207 | #define AMAZON_BCU_CON ((volatile u32*)(AMAZON_BCU+ 0x0010)) |
| 208 | #define AMAZON_BCU_CON_SPC(value) (((( 1 << 8) - 1) & (value)) << 24) |
| 209 | #define AMAZON_BCU_CON_SPE (1 << 19) |
| 210 | #define AMAZON_BCU_CON_PSE (1 << 18) |
| 211 | #define AMAZON_BCU_CON_DBG (1 << 16) |
| 212 | #define AMAZON_BCU_CON_TOUT(value) (((( 1 << 16) - 1) & (value)) << 0) |
| 213 | |
| 214 | /***BCU Error Control Capture Register (0020H)***/ |
| 215 | #define AMAZON_BCU_ECON ((volatile u32*)(AMAZON_BCU+ 0x0020)) |
| 216 | #define AMAZON_BCU_ECON_TAG(value) (((( 1 << 4) - 1) & (value)) << 24) |
| 217 | #define AMAZON_BCU_ECON_RDN (1 << 23) |
| 218 | #define AMAZON_BCU_ECON_WRN (1 << 22) |
| 219 | #define AMAZON_BCU_ECON_SVM (1 << 21) |
| 220 | #define AMAZON_BCU_ECON_ACK(value) (((( 1 << 2) - 1) & (value)) << 19) |
| 221 | #define AMAZON_BCU_ECON_ABT (1 << 18) |
| 222 | #define AMAZON_BCU_ECON_RDY (1 << 17) |
| 223 | #define AMAZON_BCU_ECON_TOUT (1 << 16) |
| 224 | #define AMAZON_BCU_ECON_ERRCNT(value) (((( 1 << 16) - 1) & (value)) << 0) |
| 225 | #define AMAZON_BCU_ECON_OPC(value) (((( 1 << 4) - 1) & (value)) << 28) |
| 226 | |
| 227 | /***BCU Error Address Capture Register (0024 H)***/ |
| 228 | #define AMAZON_BCU_EADD ((volatile u32*)(AMAZON_BCU+ 0x0024)) |
| 229 | #define AMAZON_BCU_EADD_FPIADR |
| 230 | |
| 231 | /***BCU Error Data Capture Register (0028H)***/ |
| 232 | #define AMAZON_BCU_EDAT ((volatile u32*)(AMAZON_BCU+ 0x0028)) |
| 233 | #define AMAZON_BCU_EDAT_FPIDAT |
| 234 | |
| 235 | /***********************************************************************/ |
| 236 | /* Module : Switch register address and bits */ |
| 237 | /***********************************************************************/ |
| 238 | |
| 239 | #define AMAZON_SWITCH (KSEG1+0x10106000) |
| 240 | /***********************************************************************/ |
| 241 | #define AMAZON_SW_UN_DEST AMAZON_SWITCH+0x00 /*Unknown destination register*/ |
| 242 | #define AMAZON_SW_VLAN_CTRL AMAZON_SWITCH+0x04 /*VLAN control register*/ |
| 243 | #define AMAZON_SW_PS_CTL AMAZON_SWITCH+0x08 /*port status control register*/ |
| 244 | #define AMAZON_SW_COS_CTL AMAZON_SWITCH+0x0c /*Cos control register*/ |
| 245 | #define AMAZON_SW_VLAN_COS AMAZON_SWITCH+0x10 /*VLAN priority cos mapping register*/ |
| 246 | #define AMAZON_SW_DSCP_COS3 AMAZON_SWITCH+0x14 /*DSCP cos mapping register3*/ |
| 247 | #define AMAZON_SW_DSCP_COS2 AMAZON_SWITCH+0x18 /*DSCP cos mapping register2*/ |
| 248 | #define AMAZON_SW_DSCP_COS1 AMAZON_SWITCH+0x1c /*DSCP cos mapping register1*/ |
| 249 | #define AMAZON_SW_DSCP_COS0 AMAZON_SWITCH+0x20 /*DSCP cos mapping register*/ |
| 250 | #define AMAZON_SW_ARL_CTL AMAZON_SWITCH+0x24 /*ARL control register*/ |
| 251 | #define AMAZON_SW_PKT_LEN AMAZON_SWITCH+0x28 /*packet length register*/ |
| 252 | #define AMAZON_SW_CPU_ACTL AMAZON_SWITCH+0x2c /*CPU control register1*/ |
| 253 | #define AMAZON_SW_DATA1 AMAZON_SWITCH+0x30 /*CPU access control register1*/ |
| 254 | #define AMAZON_SW_DATA2 AMAZON_SWITCH+0x34 /*CPU access control register2*/ |
| 255 | #define AMAZON_SW_P2_PCTL AMAZON_SWITCH+0x38 /*Port2 control register*/ |
| 256 | #define AMAZON_SW_P0_TX_CTL AMAZON_SWITCH+0x3c /*port0 TX control register*/ |
| 257 | #define AMAZON_SW_P1_TX_CTL AMAZON_SWITCH+0x40 /*port 1 TX control register*/ |
| 258 | #define AMAZON_SW_P0_WM AMAZON_SWITCH+0x44 /*port 0 watermark control register*/ |
| 259 | #define AMAZON_SW_P1_WM AMAZON_SWITCH+0x48 /*port 1 watermark control register*/ |
| 260 | #define AMAZON_SW_P2_WM AMAZON_SWITCH+0x4c /*port 2 watermark control register*/ |
| 261 | #define AMAZON_SW_GBL_WM AMAZON_SWITCH+0x50 /*Global watermark register*/ |
| 262 | #define AMAZON_SW_PM_CTL AMAZON_SWITCH+0x54 /*PM control register*/ |
| 263 | #define AMAZON_SW_P2_CTL AMAZON_SWITCH+0x58 /*PMAC control register*/ |
| 264 | #define AMAZON_SW_P2_TX_IPG AMAZON_SWITCH+0x5c /*port2 TX IPG control register*/ |
| 265 | #define AMAZON_SW_P2_RX_IPG AMAZON_SWITCH+0x60 /*prot2 RX IPG control register*/ |
| 266 | #define AMAZON_SW_MDIO_ACC AMAZON_SWITCH+0x64 /*MDIO access register*/ |
| 267 | #define AMAZON_SW_EPHY AMAZON_SWITCH+0x68 /*Ethernet PHY register*/ |
| 268 | #define AMAZON_SW_MDIO_CFG AMAZON_SWITCH+0x6c /*MDIO configuration register*/ |
| 269 | #define AMAZON_SW_P0_RCV_DROP_CNT AMAZON_SWITCH+0x70 /*port0 receive drop counter */ |
| 270 | #define AMAZON_SW_P0_RCV_FRAME_ERR_CNT AMAZON_SWITCH+0x74 /*port0 receive frame error conter*/ |
| 271 | #define AMAZON_SW_P0_TX_COLL_CNT AMAZON_SWITCH+0x78 /*port0 transmit collision counter*/ |
| 272 | #define AMAZON_SW_P0_TX_DROP_CNT AMAZON_SWITCH+0x7c /*port1 transmit drop counter*/ |
| 273 | #define AMAZON_SW_P1_RCV_DROP_CNT AMAZON_SWITCH+0x80 /*port1 receive drop counter*/ |
| 274 | #define AMAZON_SW_P1_RCV_FRAME_ERR_CNT AMAZON_SWITCH+0x84 /*port1 receive error counter*/ |
| 275 | #define AMAZON_SW_P1_TX_COLL_CNT AMAZON_SWITCH+0x88 /*port1 transmit collision counter*/ |
| 276 | #define AMAZON_SW_P1_TX_DROP_CNT AMAZON_SWITCH+0x8c /*port1 transmit drop counter*/ |
| 277 | |
| 278 | |
| 279 | |
| 280 | /***********************************************************************/ |
| 281 | /* Module : SSC register address and bits */ |
| 282 | /***********************************************************************/ |
| 283 | #define AMAZON_SSC_BASE_ADD_0 (KSEG1+0x10100800) |
| 284 | |
| 285 | /*165001:henryhsu:20050603:Source add by Bing Tao*/ |
| 286 | |
| 287 | /*configuration/Status Registers in Bus Clock Domain*/ |
| 288 | #define AMAZON_SSC_CLC ((volatile u32*)(AMAZON_SSC_BASE_ADD_0+0x0000)) |
| 289 | #define AMAZON_SSC_ID ((volatile u32*)(AMAZON_SSC_BASE_ADD_0+0x0008)) |
| 290 | #define AMAZON_SSC_CON ((volatile u32*)(AMAZON_SSC_BASE_ADD_0+0x0010)) |
| 291 | #define AMAZON_SSC_STATE ((volatile u32*)(AMAZON_SSC_BASE_ADD_0+0x0014)) |
| 292 | #define AMAZON_SSC_WHBSTATE ((volatile u32*)(AMAZON_SSC_BASE_ADD_0+0x0018)) |
| 293 | #define AMAZON_SSC_TB ((volatile u32*)(AMAZON_SSC_BASE_ADD_0+0x0020)) |
| 294 | #define AMAZON_SSC_RB ((volatile u32*)(AMAZON_SSC_BASE_ADD_0+0x0024)) |
| 295 | #define AMAZON_SSC_FSTAT ((volatile u32*)(AMAZON_SSC_BASE_ADD_0+0x0038)) |
| 296 | |
| 297 | /*Configuration/Status Registers in Kernel Clock Domain*/ |
| 298 | #define AMAZON_SSC_PISEL ((volatile u32*)(AMAZON_SSC_BASE_ADD_0+0x0004)) |
| 299 | #define AMAZON_SSC_RXFCON ((volatile u32*)(AMAZON_SSC_BASE_ADD_0+0x0030)) |
| 300 | #define AMAZON_SSC_TXFCON ((volatile u32*)(AMAZON_SSC_BASE_ADD_0+0x0034)) |
| 301 | #define AMAZON_SSC_BR ((volatile u32*)(AMAZON_SSC_BASE_ADD_0+0x0040)) |
| 302 | #define AMAZON_SSC_BRSTAT ((volatile u32*)(AMAZON_SSC_BASE_ADD_0+0x0044)) |
| 303 | #define AMAZON_SSC_SFCON ((volatile u32*)(AMAZON_SSC_BASE_ADD_0+0x0060)) |
| 304 | #define AMAZON_SSC_SFSTAT ((volatile u32*)(AMAZON_SSC_BASE_ADD_0+0x0064)) |
| 305 | #define AMAZON_SSC_GPOCON ((volatile u32*)(AMAZON_SSC_BASE_ADD_0+0x0070)) |
| 306 | #define AMAZON_SSC_GPOSTAT ((volatile u32*)(AMAZON_SSC_BASE_ADD_0+0x0074)) |
| 307 | #define AMAZON_SSC_WHBGPOSTAT ((volatile u32*)(AMAZON_SSC_BASE_ADD_0+0x0078)) |
| 308 | #define AMAZON_SSC_RXREQ ((volatile u32*)(AMAZON_SSC_BASE_ADD_0+0x0080)) |
| 309 | #define AMAZON_SSC_RXCNT ((volatile u32*)(AMAZON_SSC_BASE_ADD_0+0x0084)) |
| 310 | |
| 311 | /*DMA Registers in Bus Clock Domain*/ |
| 312 | #define AMAZON_SSC_DMA_CON ((volatile u32*)(AMAZON_SSC_BASE_ADD_0+0x00ec)) |
| 313 | |
| 314 | /*interrupt Node Registers in Bus Clock Domain*/ |
| 315 | #define AMAZON_SSC_IRNEN ((volatile u32*)(AMAZON_SSC_BASE_ADD_0+0x00F4)) |
| 316 | #define AMAZON_SSC_IRNICR ((volatile u32*)(AMAZON_SSC_BASE_ADD_0+0x00FC)) |
| 317 | #define AMAZON_SSC_IRNCR ((volatile u32*)(AMAZON_SSC_BASE_ADD_0+0x00F8)) |
| 318 | |
| 319 | /*165001*/ |
| 320 | |
| 321 | /***********************************************************************/ |
| 322 | |
| 323 | |
| 324 | |
| 325 | /***********************************************************************/ |
| 326 | /* Module : EBU register address and bits */ |
| 327 | /***********************************************************************/ |
| 328 | |
| 329 | #define AMAZON_EBU (KSEG1+0x10105300) |
| 330 | /***********************************************************************/ |
| 331 | |
| 332 | |
| 333 | /***EBU Clock Control Register***/ |
| 334 | #define AMAZON_EBU_CLC ((volatile u32*)(AMAZON_EBU+ 0x0000)) |
| 335 | #define AMAZON_EBU_CLC_DISS (1 << 1) |
| 336 | #define AMAZON_EBU_CLC_DISR (1 << 0) |
| 337 | |
| 338 | /***EBU Global Control Register***/ |
| 339 | #define AMAZON_EBU_CON ((volatile u32*)(AMAZON_EBU+ 0x0010)) |
| 340 | #define AMAZON_EBU_CON_DTACS(value) (((( 1 << 3) - 1) & (value)) << 20) |
| 341 | #define AMAZON_EBU_CON_DTARW(value) (((( 1 << 3) - 1) & (value)) << 16) |
| 342 | #define AMAZON_EBU_CON_TOUTC(value) (((( 1 << 8) - 1) & (value)) << 8) |
| 343 | #define AMAZON_EBU_CON_ARBMODE(value) (((( 1 << 2) - 1) & (value)) << 6) |
| 344 | #define AMAZON_EBU_CON_ARBSYNC (1 << 5) |
| 345 | #define AMAZON_EBU_CON_1 (1 << 3) |
| 346 | |
| 347 | /***EBU Address Select Register 0***/ |
| 348 | #define AMAZON_EBU_ADDSEL0 ((volatile u32*)(AMAZON_EBU+ 0x0020)) |
| 349 | #define AMAZON_EBU_ADDSEL0_BASE(value) (((( 1 << 20) - 1) & (value)) << 12) |
| 350 | #define AMAZON_EBU_ADDSEL0_MASK(value) (((( 1 << 4) - 1) & (value)) << 4) |
| 351 | #define AMAZON_EBU_ADDSEL0_MIRRORE (1 << 1) |
| 352 | #define AMAZON_EBU_ADDSEL0_REGEN (1 << 0) |
| 353 | |
| 354 | /***EBU Address Select Register 1***/ |
| 355 | #define AMAZON_EBU_ADDSEL1 ((volatile u32*)(AMAZON_EBU+ 0x0024)) |
| 356 | #define AMAZON_EBU_ADDSEL1_BASE(value) (((( 1 << 20) - 1) & (value)) << 12) |
| 357 | #define AMAZON_EBU_ADDSEL1_MASK(value) (((( 1 << 4) - 1) & (value)) << 4) |
| 358 | #define AMAZON_EBU_ADDSEL1_MIRRORE (1 << 1) |
| 359 | #define AMAZON_EBU_ADDSEL1_REGEN (1 << 0) |
| 360 | |
| 361 | /***EBU Address Select Register 2***/ |
| 362 | #define AMAZON_EBU_ADDSEL2 ((volatile u32*)(AMAZON_EBU+ 0x0028)) |
| 363 | #define AMAZON_EBU_ADDSEL2_BASE(value) (((( 1 << 20) - 1) & (value)) << 12) |
| 364 | #define AMAZON_EBU_ADDSEL2_MASK(value) (((( 1 << 4) - 1) & (value)) << 4) |
| 365 | #define AMAZON_EBU_ADDSEL2_MIRRORE (1 << 1) |
| 366 | #define AMAZON_EBU_ADDSEL2_REGEN (1 << 0) |
| 367 | |
| 368 | /***EBU Bus Configuration Register 0***/ |
| 369 | #define AMAZON_EBU_BUSCON0 ((volatile u32*)(AMAZON_EBU+ 0x0060)) |
| 370 | #define AMAZON_EBU_BUSCON0_WRDIS (1 << 31) |
| 371 | #define AMAZON_EBU_BUSCON0_ALEC(value) (((( 1 << 2) - 1) & (value)) << 29) |
| 372 | #define AMAZON_EBU_BUSCON0_BCGEN(value) (((( 1 << 2) - 1) & (value)) << 27) |
| 373 | #define AMAZON_EBU_BUSCON0_AGEN(value) (((( 1 << 2) - 1) & (value)) << 24) |
| 374 | #define AMAZON_EBU_BUSCON0_CMULTR(value) (((( 1 << 2) - 1) & (value)) << 22) |
| 375 | #define AMAZON_EBU_BUSCON0_WAIT(value) (((( 1 << 2) - 1) & (value)) << 20) |
| 376 | #define AMAZON_EBU_BUSCON0_WAITINV (1 << 19) |
| 377 | #define AMAZON_EBU_BUSCON0_SETUP (1 << 18) |
| 378 | #define AMAZON_EBU_BUSCON0_PORTW(value) (((( 1 << 2) - 1) & (value)) << 16) |
| 379 | #define AMAZON_EBU_BUSCON0_WAITRDC(value) (((( 1 << 7) - 1) & (value)) << 9) |
| 380 | #define AMAZON_EBU_BUSCON0_WAITWRC(value) (((( 1 << 3) - 1) & (value)) << 6) |
| 381 | #define AMAZON_EBU_BUSCON0_HOLDC(value) (((( 1 << 2) - 1) & (value)) << 4) |
| 382 | #define AMAZON_EBU_BUSCON0_RECOVC(value) (((( 1 << 2) - 1) & (value)) << 2) |
| 383 | #define AMAZON_EBU_BUSCON0_CMULT(value) (((( 1 << 2) - 1) & (value)) << 0) |
| 384 | |
| 385 | /***EBU Bus Configuration Register 1***/ |
| 386 | #define AMAZON_EBU_BUSCON1 ((volatile u32*)(AMAZON_EBU+ 0x0064)) |
| 387 | #define AMAZON_EBU_BUSCON1_WRDIS (1 << 31) |
| 388 | #define AMAZON_EBU_BUSCON1_ALEC(value) (((( 1 << 2) - 1) & (value)) << 29) |
| 389 | #define AMAZON_EBU_BUSCON1_BCGEN(value) (((( 1 << 2) - 1) & (value)) << 27) |
| 390 | #define AMAZON_EBU_BUSCON1_AGEN(value) (((( 1 << 2) - 1) & (value)) << 24) |
| 391 | #define AMAZON_EBU_BUSCON1_CMULTR(value) (((( 1 << 2) - 1) & (value)) << 22) |
| 392 | #define AMAZON_EBU_BUSCON1_WAIT(value) (((( 1 << 2) - 1) & (value)) << 20) |
| 393 | #define AMAZON_EBU_BUSCON1_WAITINV (1 << 19) |
| 394 | #define AMAZON_EBU_BUSCON1_SETUP (1 << 18) |
| 395 | #define AMAZON_EBU_BUSCON1_PORTW(value) (((( 1 << 2) - 1) & (value)) << 16) |
| 396 | #define AMAZON_EBU_BUSCON1_WAITRDC(value) (((( 1 << 7) - 1) & (value)) << 9) |
| 397 | #define AMAZON_EBU_BUSCON1_WAITWRC(value) (((( 1 << 3) - 1) & (value)) << 6) |
| 398 | #define AMAZON_EBU_BUSCON1_HOLDC(value) (((( 1 << 2) - 1) & (value)) << 4) |
| 399 | #define AMAZON_EBU_BUSCON1_RECOVC(value) (((( 1 << 2) - 1) & (value)) << 2) |
| 400 | #define AMAZON_EBU_BUSCON1_CMULT(value) (((( 1 << 2) - 1) & (value)) << 0) |
| 401 | |
| 402 | /***EBU Bus Configuration Register 2***/ |
| 403 | #define AMAZON_EBU_BUSCON2 ((volatile u32*)(AMAZON_EBU+ 0x0068)) |
| 404 | #define AMAZON_EBU_BUSCON2_WRDIS (1 << 31) |
| 405 | #define AMAZON_EBU_BUSCON2_ALEC(value) (((( 1 << 2) - 1) & (value)) << 29) |
| 406 | #define AMAZON_EBU_BUSCON2_BCGEN(value) (((( 1 << 2) - 1) & (value)) << 27) |
| 407 | #define AMAZON_EBU_BUSCON2_AGEN(value) (((( 1 << 2) - 1) & (value)) << 24) |
| 408 | #define AMAZON_EBU_BUSCON2_CMULTR(value) (((( 1 << 2) - 1) & (value)) << 22) |
| 409 | #define AMAZON_EBU_BUSCON2_WAIT(value) (((( 1 << 2) - 1) & (value)) << 20) |
| 410 | #define AMAZON_EBU_BUSCON2_WAITINV (1 << 19) |
| 411 | #define AMAZON_EBU_BUSCON2_SETUP (1 << 18) |
| 412 | #define AMAZON_EBU_BUSCON2_PORTW(value) (((( 1 << 2) - 1) & (value)) << 16) |
| 413 | #define AMAZON_EBU_BUSCON2_WAITRDC(value) (((( 1 << 7) - 1) & (value)) << 9) |
| 414 | #define AMAZON_EBU_BUSCON2_WAITWRC(value) (((( 1 << 3) - 1) & (value)) << 6) |
| 415 | #define AMAZON_EBU_BUSCON2_HOLDC(value) (((( 1 << 2) - 1) & (value)) << 4) |
| 416 | #define AMAZON_EBU_BUSCON2_RECOVC(value) (((( 1 << 2) - 1) & (value)) << 2) |
| 417 | #define AMAZON_EBU_BUSCON2_CMULT(value) (((( 1 << 2) - 1) & (value)) << 0) |
| 418 | |
| 419 | /***********************************************************************/ |
| 420 | /* Module : SDRAM register address and bits */ |
| 421 | /***********************************************************************/ |
| 422 | |
| 423 | #define AMAZON_SDRAM (KSEG1+0x1F800000) |
| 424 | /***********************************************************************/ |
| 425 | |
| 426 | |
| 427 | /***MC Access Error Cause Register***/ |
| 428 | #define AMAZON_SDRAM_MC_ERRCAUSE ((volatile u32*)(AMAZON_SDRAM+ 0x0010)) |
| 429 | #define AMAZON_SDRAM_MC_ERRCAUSE_ERR (1 << 31) |
| 430 | #define AMAZON_SDRAM_MC_ERRCAUSE_PORT(value) (((( 1 << 4) - 1) & (value)) << 16) |
| 431 | #define AMAZON_SDRAM_MC_ERRCAUSE_CAUSE(value) (((( 1 << 2) - 1) & (value)) << 0) |
| 432 | #define AMAZON_SDRAM_MC_ERRCAUSE_Res(value) (((( 1 << NaN) - 1) & (value)) << NaN) |
| 433 | |
| 434 | /***MC Access Error Address Register***/ |
| 435 | #define AMAZON_SDRAM_MC_ERRADDR ((volatile u32*)(AMAZON_SDRAM+ 0x0020)) |
| 436 | #define AMAZON_SDRAM_MC_ERRADDR_ADDR |
| 437 | |
| 438 | /***MC I/O General Purpose Register***/ |
| 439 | #define AMAZON_SDRAM_MC_IOGP ((volatile u32*)(AMAZON_SDRAM+ 0x0100)) |
| 440 | #define AMAZON_SDRAM_MC_IOGP_GPR6(value) (((( 1 << 4) - 1) & (value)) << 28) |
| 441 | #define AMAZON_SDRAM_MC_IOGP_GPR5(value) (((( 1 << 4) - 1) & (value)) << 24) |
| 442 | #define AMAZON_SDRAM_MC_IOGP_GPR4(value) (((( 1 << 4) - 1) & (value)) << 20) |
| 443 | #define AMAZON_SDRAM_MC_IOGP_GPR3(value) (((( 1 << 4) - 1) & (value)) << 16) |
| 444 | #define AMAZON_SDRAM_MC_IOGP_GPR2(value) (((( 1 << 4) - 1) & (value)) << 12) |
| 445 | #define AMAZON_SDRAM_MC_IOGP_CPS (1 << 11) |
| 446 | #define AMAZON_SDRAM_MC_IOGP_CLKDELAY(value) (((( 1 << 3) - 1) & (value)) << 8) |
| 447 | #define AMAZON_SDRAM_MC_IOGP_CLKRAT(value) (((( 1 << 4) - 1) & (value)) << 4) |
| 448 | #define AMAZON_SDRAM_MC_IOGP_RDDEL(value) (((( 1 << 4) - 1) & (value)) << 0) |
| 449 | |
| 450 | /***MC Self Refresh Register***/ |
| 451 | #define AMAZON_SDRAM_MC_SELFRFSH ((volatile u32*)(AMAZON_SDRAM+ 0x01A0)) |
| 452 | #define AMAZON_SDRAM_MC_SELFRFSH_PWDS (1 << 1) |
| 453 | #define AMAZON_SDRAM_MC_SELFRFSH_PWD (1 << 0) |
| 454 | #define AMAZON_SDRAM_MC_SELFRFSH_Res(value) (((( 1 << 30) - 1) & (value)) << 2) |
| 455 | |
| 456 | /***MC Enable Register***/ |
| 457 | #define AMAZON_SDRAM_MC_CTRLENA ((volatile u32*)(AMAZON_SDRAM+ 0x0110)) |
| 458 | #define AMAZON_SDRAM_MC_CTRLENA_ENA (1 << 0) |
| 459 | #define AMAZON_SDRAM_MC_CTRLENA_Res(value) (((( 1 << 31) - 1) & (value)) << 1) |
| 460 | |
| 461 | /***MC Mode Register Setup Code***/ |
| 462 | #define AMAZON_SDRAM_MC_MRSCODE ((volatile u32*)(AMAZON_SDRAM+ 0x0120)) |
| 463 | #define AMAZON_SDRAM_MC_MRSCODE_UMC(value) (((( 1 << 5) - 1) & (value)) << 7) |
| 464 | #define AMAZON_SDRAM_MC_MRSCODE_CL(value) (((( 1 << 3) - 1) & (value)) << 4) |
| 465 | #define AMAZON_SDRAM_MC_MRSCODE_WT (1 << 3) |
| 466 | #define AMAZON_SDRAM_MC_MRSCODE_BL(value) (((( 1 << 3) - 1) & (value)) << 0) |
| 467 | |
| 468 | /***MC Configuration Data-word Width Register***/ |
| 469 | #define AMAZON_SDRAM_MC_CFGDW ((volatile u32*)(AMAZON_SDRAM+ 0x0130)) |
| 470 | #define AMAZON_SDRAM_MC_CFGDW_DW(value) (((( 1 << 4) - 1) & (value)) << 0) |
| 471 | #define AMAZON_SDRAM_MC_CFGDW_Res(value) (((( 1 << 28) - 1) & (value)) << 4) |
| 472 | |
| 473 | /***MC Configuration Physical Bank 0 Register***/ |
| 474 | #define AMAZON_SDRAM_MC_CFGPB0 ((volatile u32*)(AMAZON_SDRAM+ 0x140)) |
| 475 | #define AMAZON_SDRAM_MC_CFGPB0_MCSEN0(value) (((( 1 << 4) - 1) & (value)) << 12) |
| 476 | #define AMAZON_SDRAM_MC_CFGPB0_BANKN0(value) (((( 1 << 4) - 1) & (value)) << 8) |
| 477 | #define AMAZON_SDRAM_MC_CFGPB0_ROWW0(value) (((( 1 << 4) - 1) & (value)) << 4) |
| 478 | #define AMAZON_SDRAM_MC_CFGPB0_COLW0(value) (((( 1 << 4) - 1) & (value)) << 0) |
| 479 | #define AMAZON_SDRAM_MC_CFGPB0_Res(value) (((( 1 << 16) - 1) & (value)) << 16) |
| 480 | |
| 481 | /***MC Latency Register***/ |
| 482 | #define AMAZON_SDRAM_MC_LATENCY ((volatile u32*)(AMAZON_SDRAM+ 0x0180)) |
| 483 | #define AMAZON_SDRAM_MC_LATENCY_TRP(value) (((( 1 << 4) - 1) & (value)) << 16) |
| 484 | #define AMAZON_SDRAM_MC_LATENCY_TRAS(value) (((( 1 << 4) - 1) & (value)) << 12) |
| 485 | #define AMAZON_SDRAM_MC_LATENCY_TRCD(value) (((( 1 << 4) - 1) & (value)) << 8) |
| 486 | #define AMAZON_SDRAM_MC_LATENCY_TDPL(value) (((( 1 << 4) - 1) & (value)) << 4) |
| 487 | #define AMAZON_SDRAM_MC_LATENCY_TDAL(value) (((( 1 << 4) - 1) & (value)) << 0) |
| 488 | #define AMAZON_SDRAM_MC_LATENCY_Res(value) (((( 1 << 12) - 1) & (value)) << 20) |
| 489 | |
| 490 | /***MC Refresh Cycle Time Register***/ |
| 491 | #define AMAZON_SDRAM_MC_TREFRESH ((volatile u32*)(AMAZON_SDRAM+ 0x0190)) |
| 492 | #define AMAZON_SDRAM_MC_TREFRESH_TREF(value) (((( 1 << 13) - 1) & (value)) << 0) |
| 493 | #define AMAZON_SDRAM_MC_TREFRESH_Res(value) (((( 1 << 19) - 1) & (value)) << 13) |
| 494 | |
| 495 | /***********************************************************************/ |
| 496 | /* Module : GPTU register address and bits */ |
| 497 | /***********************************************************************/ |
| 498 | |
| 499 | #define AMAZON_GPTU (KSEG1+0x10100A00) |
| 500 | /***********************************************************************/ |
| 501 | |
| 502 | |
| 503 | /***GPT Clock Control Register***/ |
| 504 | #define AMAZON_GPTU_CLC ((volatile u32*)(AMAZON_GPTU+ 0x0000)) |
| 505 | #define AMAZON_GPTU_CLC_RMC(value) (((( 1 << 8) - 1) & (value)) << 8) |
| 506 | #define AMAZON_GPTU_CLC_DISS (1 << 1) |
| 507 | #define AMAZON_GPTU_CLC_DISR (1 << 0) |
| 508 | |
| 509 | /***GPT Timer 3 Control Register***/ |
| 510 | #define AMAZON_GPTU_T3CON ((volatile u32*)(AMAZON_GPTU+ 0x0014)) |
| 511 | #define AMAZON_GPTU_T3CON_T3RDIR (1 << 15) |
| 512 | #define AMAZON_GPTU_T3CON_T3CHDIR (1 << 14) |
| 513 | #define AMAZON_GPTU_T3CON_T3EDGE (1 << 13) |
| 514 | #define AMAZON_GPTU_T3CON_BPS1(value) (((( 1 << 2) - 1) & (value)) << 11) |
| 515 | #define AMAZON_GPTU_T3CON_T3OTL (1 << 10) |
| 516 | #define AMAZON_GPTU_T3CON_T3UD (1 << 7) |
| 517 | #define AMAZON_GPTU_T3CON_T3R (1 << 6) |
| 518 | #define AMAZON_GPTU_T3CON_T3M(value) (((( 1 << 3) - 1) & (value)) << 3) |
| 519 | #define AMAZON_GPTU_T3CON_T3I(value) (((( 1 << 3) - 1) & (value)) << 0) |
| 520 | |
| 521 | /***GPT Write Hardware Modified Timer 3 Control Register |
| 522 | If set and clear bit are written concurrently with 1, the associated bit is not changed.***/ |
| 523 | #define AMAZON_GPTU_WHBT3CON ((volatile u32*)(AMAZON_GPTU+ 0x004C)) |
| 524 | #define AMAZON_GPTU_WHBT3CON_SETT3CHDIR (1 << 15) |
| 525 | #define AMAZON_GPTU_WHBT3CON_CLRT3CHDIR (1 << 14) |
| 526 | #define AMAZON_GPTU_WHBT3CON_SETT3EDGE (1 << 13) |
| 527 | #define AMAZON_GPTU_WHBT3CON_CLRT3EDGE (1 << 12) |
| 528 | #define AMAZON_GPTU_WHBT3CON_SETT3OTL (1 << 11) |
| 529 | #define AMAZON_GPTU_WHBT3CON_CLRT3OTL (1 << 10) |
| 530 | |
| 531 | /***GPT Timer 2 Control Register***/ |
| 532 | #define AMAZON_GPTU_T2CON ((volatile u32*)(AMAZON_GPTU+ 0x0010)) |
| 533 | #define AMAZON_GPTU_T2CON_TxRDIR (1 << 15) |
| 534 | #define AMAZON_GPTU_T2CON_TxCHDIR (1 << 14) |
| 535 | #define AMAZON_GPTU_T2CON_TxEDGE (1 << 13) |
| 536 | #define AMAZON_GPTU_T2CON_TxIRDIS (1 << 12) |
| 537 | #define AMAZON_GPTU_T2CON_TxRC (1 << 9) |
| 538 | #define AMAZON_GPTU_T2CON_TxUD (1 << 7) |
| 539 | #define AMAZON_GPTU_T2CON_TxR (1 << 6) |
| 540 | #define AMAZON_GPTU_T2CON_TxM(value) (((( 1 << 3) - 1) & (value)) << 3) |
| 541 | #define AMAZON_GPTU_T2CON_TxI(value) (((( 1 << 3) - 1) & (value)) << 0) |
| 542 | |
| 543 | /***GPT Timer 4 Control Register***/ |
| 544 | #define AMAZON_GPTU_T4CON ((volatile u32*)(AMAZON_GPTU+ 0x0018)) |
| 545 | #define AMAZON_GPTU_T4CON_TxRDIR (1 << 15) |
| 546 | #define AMAZON_GPTU_T4CON_TxCHDIR (1 << 14) |
| 547 | #define AMAZON_GPTU_T4CON_TxEDGE (1 << 13) |
| 548 | #define AMAZON_GPTU_T4CON_TxIRDIS (1 << 12) |
| 549 | #define AMAZON_GPTU_T4CON_TxRC (1 << 9) |
| 550 | #define AMAZON_GPTU_T4CON_TxUD (1 << 7) |
| 551 | #define AMAZON_GPTU_T4CON_TxR (1 << 6) |
| 552 | #define AMAZON_GPTU_T4CON_TxM(value) (((( 1 << 3) - 1) & (value)) << 3) |
| 553 | #define AMAZON_GPTU_T4CON_TxI(value) (((( 1 << 3) - 1) & (value)) << 0) |
| 554 | |
| 555 | /***GPT Write HW Modified Timer 2 Control Register If set |
| 556 | and clear bit are written concurrently with 1, the associated bit is not changed.***/ |
| 557 | #define AMAZON_GPTU_WHBT2CON ((volatile u32*)(AMAZON_GPTU+ 0x0048)) |
| 558 | #define AMAZON_GPTU_WHBT2CON_SETTxCHDIR (1 << 15) |
| 559 | #define AMAZON_GPTU_WHBT2CON_CLRTxCHDIR (1 << 14) |
| 560 | #define AMAZON_GPTU_WHBT2CON_SETTxEDGE (1 << 13) |
| 561 | #define AMAZON_GPTU_WHBT2CON_CLRTxEDGE (1 << 12) |
| 562 | |
| 563 | /***GPT Write HW Modified Timer 4 Control Register If set |
| 564 | and clear bit are written concurrently with 1, the associated bit is not changed.***/ |
| 565 | #define AMAZON_GPTU_WHBT4CON ((volatile u32*)(AMAZON_GPTU+ 0x0050)) |
| 566 | #define AMAZON_GPTU_WHBT4CON_SETTxCHDIR (1 << 15) |
| 567 | #define AMAZON_GPTU_WHBT4CON_CLRTxCHDIR (1 << 14) |
| 568 | #define AMAZON_GPTU_WHBT4CON_SETTxEDGE (1 << 13) |
| 569 | #define AMAZON_GPTU_WHBT4CON_CLRTxEDGE (1 << 12) |
| 570 | |
| 571 | /***GPT Capture Reload Register***/ |
| 572 | #define AMAZON_GPTU_CAPREL ((volatile u32*)(AMAZON_GPTU+ 0x0030)) |
| 573 | #define AMAZON_GPTU_CAPREL_CAPREL(value) (((( 1 << 16) - 1) & (value)) << 0) |
| 574 | |
| 575 | /***GPT Timer 2 Register***/ |
| 576 | #define AMAZON_GPTU_T2 ((volatile u32*)(AMAZON_GPTU+ 0x0034)) |
| 577 | #define AMAZON_GPTU_T2_TVAL(value) (((( 1 << 16) - 1) & (value)) << 0) |
| 578 | |
| 579 | /***GPT Timer 3 Register***/ |
| 580 | #define AMAZON_GPTU_T3 ((volatile u32*)(AMAZON_GPTU+ 0x0038)) |
| 581 | #define AMAZON_GPTU_T3_TVAL(value) (((( 1 << 16) - 1) & (value)) << 0) |
| 582 | |
| 583 | /***GPT Timer 4 Register***/ |
| 584 | #define AMAZON_GPTU_T4 ((volatile u32*)(AMAZON_GPTU+ 0x003C)) |
| 585 | #define AMAZON_GPTU_T4_TVAL(value) (((( 1 << 16) - 1) & (value)) << 0) |
| 586 | |
| 587 | /***GPT Timer 5 Register***/ |
| 588 | #define AMAZON_GPTU_T5 ((volatile u32*)(AMAZON_GPTU+ 0x0040)) |
| 589 | #define AMAZON_GPTU_T5_TVAL(value) (((( 1 << 16) - 1) & (value)) << 0) |
| 590 | |
| 591 | /***GPT Timer 6 Register***/ |
| 592 | #define AMAZON_GPTU_T6 ((volatile u32*)(AMAZON_GPTU+ 0x0044)) |
| 593 | #define AMAZON_GPTU_T6_TVAL(value) (((( 1 << 16) - 1) & (value)) << 0) |
| 594 | |
| 595 | /***GPT Timer 6 Control Register***/ |
| 596 | #define AMAZON_GPTU_T6CON ((volatile u32*)(AMAZON_GPTU+ 0x0020)) |
| 597 | #define AMAZON_GPTU_T6CON_T6SR (1 << 15) |
| 598 | #define AMAZON_GPTU_T6CON_T6CLR (1 << 14) |
| 599 | #define AMAZON_GPTU_T6CON_BPS2(value) (((( 1 << 2) - 1) & (value)) << 11) |
| 600 | #define AMAZON_GPTU_T6CON_T6OTL (1 << 10) |
| 601 | #define AMAZON_GPTU_T6CON_T6UD (1 << 7) |
| 602 | #define AMAZON_GPTU_T6CON_T6R (1 << 6) |
| 603 | #define AMAZON_GPTU_T6CON_T6M(value) (((( 1 << 3) - 1) & (value)) << 3) |
| 604 | #define AMAZON_GPTU_T6CON_T6I(value) (((( 1 << 3) - 1) & (value)) << 0) |
| 605 | |
| 606 | /***GPT Write HW Modified Timer 6 Control Register If set |
| 607 | and clear bit are written concurrently with 1, the associated bit is not changed.***/ |
| 608 | #define AMAZON_GPTU_WHBT6CON ((volatile u32*)(AMAZON_GPTU+ 0x0054)) |
| 609 | #define AMAZON_GPTU_WHBT6CON_SETT6OTL (1 << 11) |
| 610 | #define AMAZON_GPTU_WHBT6CON_CLRT6OTL (1 << 10) |
| 611 | |
| 612 | /***GPT Timer 5 Control Register***/ |
| 613 | #define AMAZON_GPTU_T5CON ((volatile u32*)(AMAZON_GPTU+ 0x001C)) |
| 614 | #define AMAZON_GPTU_T5CON_T5SC (1 << 15) |
| 615 | #define AMAZON_GPTU_T5CON_T5CLR (1 << 14) |
| 616 | #define AMAZON_GPTU_T5CON_CI(value) (((( 1 << 2) - 1) & (value)) << 12) |
| 617 | #define AMAZON_GPTU_T5CON_T5CC (1 << 11) |
| 618 | #define AMAZON_GPTU_T5CON_CT3 (1 << 10) |
| 619 | #define AMAZON_GPTU_T5CON_T5RC (1 << 9) |
| 620 | #define AMAZON_GPTU_T5CON_T5UDE (1 << 8) |
| 621 | #define AMAZON_GPTU_T5CON_T5UD (1 << 7) |
| 622 | #define AMAZON_GPTU_T5CON_T5R (1 << 6) |
| 623 | #define AMAZON_GPTU_T5CON_T5M(value) (((( 1 << 3) - 1) & (value)) << 3) |
| 624 | #define AMAZON_GPTU_T5CON_T5I(value) (((( 1 << 3) - 1) & (value)) << 0) |
| 625 | |
| 626 | |
| 627 | /***********************************************************************/ |
| 628 | /* Module : ASC register address and bits */ |
| 629 | /***********************************************************************/ |
| 630 | |
| 631 | #define AMAZON_ASC (KSEG1+0x10100400) |
| 632 | /***********************************************************************/ |
| 633 | |
| 634 | |
| 635 | /***ASC Port Input Select Register***/ |
| 636 | #define AMAZON_ASC_PISEL (AMAZON_ASC+ 0x0004) |
| 637 | #define AMAZON_ASC_PISEL_RIS (1 << 0) |
| 638 | |
| 639 | /***ASC Control Register***/ |
| 640 | #define AMAZON_ASC_CON (AMAZON_ASC+ 0x0010) |
| 641 | #define AMAZON_ASC_CON_R (1 << 15) |
| 642 | #define AMAZON_ASC_CON_LB (1 << 14) |
| 643 | #define AMAZON_ASC_CON_BRS (1 << 13) |
| 644 | #define AMAZON_ASC_CON_ODD (1 << 12) |
| 645 | #define AMAZON_ASC_CON_FDE (1 << 11) |
| 646 | #define AMAZON_ASC_CON_OE (1 << 10) |
| 647 | #define AMAZON_ASC_CON_FE (1 << 9) |
| 648 | #define AMAZON_ASC_CON_PE (1 << 8) |
| 649 | #define AMAZON_ASC_CON_OEN (1 << 7) |
| 650 | #define AMAZON_ASC_CON_FEN (1 << 6) |
| 651 | #define AMAZON_ASC_CON_PENRXDI (1 << 5) |
| 652 | #define AMAZON_ASC_CON_REN (1 << 4) |
| 653 | #define AMAZON_ASC_CON_STP (1 << 3) |
| 654 | #define AMAZON_ASC_CON_M(value) (((( 1 << 3) - 1) & (value)) << 0) |
| 655 | |
| 656 | /***ASC Write Hardware Modified Control Register***/ |
| 657 | #define AMAZON_ASC_WHBCON (AMAZON_ASC+ 0x0050) |
| 658 | #define AMAZON_ASC_WHBCON_SETOE (1 << 13) |
| 659 | #define AMAZON_ASC_WHBCON_SETFE (1 << 12) |
| 660 | #define AMAZON_ASC_WHBCON_SETPE (1 << 11) |
| 661 | #define AMAZON_ASC_WHBCON_CLROE (1 << 10) |
| 662 | #define AMAZON_ASC_WHBCON_CLRFE (1 << 9) |
| 663 | #define AMAZON_ASC_WHBCON_CLRPE (1 << 8) |
| 664 | #define AMAZON_ASC_WHBCON_SETREN (1 << 5) |
| 665 | #define AMAZON_ASC_WHBCON_CLRREN (1 << 4) |
| 666 | |
| 667 | /***ASC Baudrate Timer/Reload Register***/ |
| 668 | #define AMAZON_ASC_BTR (AMAZON_ASC+ 0x0014) |
| 669 | #define AMAZON_ASC_BTR_BR_VALUE(value) (((( 1 << 13) - 1) & (value)) << 0) |
| 670 | |
| 671 | /***ASC Fractional Divider Register***/ |
| 672 | #define AMAZON_ASC_FDV (AMAZON_ASC+ 0x0018) |
| 673 | #define AMAZON_ASC_FDV_FD_VALUE(value) (((( 1 << 9) - 1) & (value)) << 0) |
| 674 | |
| 675 | /***ASC IrDA Pulse Mode/Width Register***/ |
| 676 | #define AMAZON_ASC_PMW (AMAZON_ASC+ 0x001C) |
| 677 | #define AMAZON_ASC_PMW_IRPW (1 << 8) |
| 678 | #define AMAZON_ASC_PMW_PW_VALUE(value) (((( 1 << 8) - 1) & (value)) << 0) |
| 679 | |
| 680 | /***ASC Transmit Buffer Register***/ |
| 681 | #define AMAZON_ASC_TBUF (AMAZON_ASC+ 0x0020) |
| 682 | #define AMAZON_ASC_TBUF_TD_VALUE(value) (((( 1 << 9) - 1) & (value)) << 0) |
| 683 | |
| 684 | /***ASC Receive Buffer Register***/ |
| 685 | #define AMAZON_ASC_RBUF (AMAZON_ASC+ 0x0024) |
| 686 | #define AMAZON_ASC_RBUF_RD_VALUE(value) (((( 1 << 9) - 1) & (value)) << 0) |
| 687 | |
| 688 | /***ASC Autobaud Control Register***/ |
| 689 | #define AMAZON_ASC_ABCON (AMAZON_ASC+ 0x0030) |
| 690 | #define AMAZON_ASC_ABCON_RXINV (1 << 11) |
| 691 | #define AMAZON_ASC_ABCON_TXINV (1 << 10) |
| 692 | #define AMAZON_ASC_ABCON_ABEM(value) (((( 1 << 2) - 1) & (value)) << 8) |
| 693 | #define AMAZON_ASC_ABCON_FCDETEN (1 << 4) |
| 694 | #define AMAZON_ASC_ABCON_ABDETEN (1 << 3) |
| 695 | #define AMAZON_ASC_ABCON_ABSTEN (1 << 2) |
| 696 | #define AMAZON_ASC_ABCON_AUREN (1 << 1) |
| 697 | #define AMAZON_ASC_ABCON_ABEN (1 << 0) |
| 698 | |
| 699 | /***Receive FIFO Control Register***/ |
| 700 | #define AMAZON_ASC_RXFCON (AMAZON_ASC+ 0x0040) |
| 701 | #define AMAZON_ASC_RXFCON_RXFITL(value) (((( 1 << 6) - 1) & (value)) << 8) |
| 702 | #define AMAZON_ASC_RXFCON_RXTMEN (1 << 2) |
| 703 | #define AMAZON_ASC_RXFCON_RXFFLU (1 << 1) |
| 704 | #define AMAZON_ASC_RXFCON_RXFEN (1 << 0) |
| 705 | |
| 706 | /***Transmit FIFO Control Register***/ |
| 707 | #define AMAZON_ASC_TXFCON (AMAZON_ASC+ 0x0044) |
| 708 | #define AMAZON_ASC_TXFCON_TXFITL(value) (((( 1 << 6) - 1) & (value)) << 8) |
| 709 | #define AMAZON_ASC_TXFCON_TXTMEN (1 << 2) |
| 710 | #define AMAZON_ASC_TXFCON_TXFFLU (1 << 1) |
| 711 | #define AMAZON_ASC_TXFCON_TXFEN (1 << 0) |
| 712 | |
| 713 | /***FIFO Status Register***/ |
| 714 | #define AMAZON_ASC_FSTAT (AMAZON_ASC+ 0x0048) |
| 715 | #define AMAZON_ASC_FSTAT_TXFFL(value) (((( 1 << 6) - 1) & (value)) << 8) |
| 716 | #define AMAZON_ASC_FSTAT_RXFFL(value) (((( 1 << 6) - 1) & (value)) << 0) |
| 717 | |
| 718 | /***ASC Write HW Modified Autobaud Control Register***/ |
| 719 | #define AMAZON_ASC_WHBABCON (AMAZON_ASC+ 0x0054) |
| 720 | #define AMAZON_ASC_WHBABCON_SETABEN (1 << 1) |
| 721 | #define AMAZON_ASC_WHBABCON_CLRABEN (1 << 0) |
| 722 | |
| 723 | /***ASC Autobaud Status Register***/ |
| 724 | #define AMAZON_ASC_ABSTAT (AMAZON_ASC+ 0x0034) |
| 725 | #define AMAZON_ASC_ABSTAT_DETWAIT (1 << 4) |
| 726 | #define AMAZON_ASC_ABSTAT_SCCDET (1 << 3) |
| 727 | #define AMAZON_ASC_ABSTAT_SCSDET (1 << 2) |
| 728 | #define AMAZON_ASC_ABSTAT_FCCDET (1 << 1) |
| 729 | #define AMAZON_ASC_ABSTAT_FCSDET (1 << 0) |
| 730 | |
| 731 | /***ASC Write HW Modified Autobaud Status Register***/ |
| 732 | #define AMAZON_ASC_WHBABSTAT (AMAZON_ASC+ 0x0058) |
| 733 | #define AMAZON_ASC_WHBABSTAT_SETDETWAIT (1 << 9) |
| 734 | #define AMAZON_ASC_WHBABSTAT_CLRDETWAIT (1 << 8) |
| 735 | #define AMAZON_ASC_WHBABSTAT_SETSCCDET (1 << 7) |
| 736 | #define AMAZON_ASC_WHBABSTAT_CLRSCCDET (1 << 6) |
| 737 | #define AMAZON_ASC_WHBABSTAT_SETSCSDET (1 << 5) |
| 738 | #define AMAZON_ASC_WHBABSTAT_CLRSCSDET (1 << 4) |
| 739 | #define AMAZON_ASC_WHBABSTAT_SETFCCDET (1 << 3) |
| 740 | #define AMAZON_ASC_WHBABSTAT_CLRFCCDET (1 << 2) |
| 741 | #define AMAZON_ASC_WHBABSTAT_SETFCSDET (1 << 1) |
| 742 | #define AMAZON_ASC_WHBABSTAT_CLRFCSDET (1 << 0) |
| 743 | |
| 744 | /***ASC Clock Control Register***/ |
| 745 | #define AMAZON_ASC_CLC (AMAZON_ASC+ 0x0000) |
| 746 | #define AMAZON_ASC_CLC_RMC(value) (((( 1 << 8) - 1) & (value)) << 8) |
| 747 | #define AMAZON_ASC_CLC_DISS (1 << 1) |
| 748 | #define AMAZON_ASC_CLC_DISR (1 << 0) |
| 749 | |
| 750 | /***ASC IRNCR0 **/ |
| 751 | #define AMAZON_ASC_IRNCR0 (AMAZON_ASC+ 0x00FC) |
| 752 | /***ASC IRNCR1 **/ |
| 753 | #define AMAZON_ASC_IRNCR1 (AMAZON_ASC+ 0x00F8) |
| 754 | #define ASC_IRNCR_TIR 0x1 |
| 755 | #define ASC_IRNCR_RIR 0x2 |
| 756 | #define ASC_IRNCR_EIR 0x4 |
| 757 | /***********************************************************************/ |
| 758 | /* Module : DMA register address and bits */ |
| 759 | /***********************************************************************/ |
| 760 | |
| 761 | #define AMAZON_DMA (KSEG1+0x10103000) |
| 762 | /***********************************************************************/ |
| 763 | #define AMAZON_DMA_CH_ON AMAZON_DMA+0x28 |
| 764 | #define AMAZON_DMA_CH_RST AMAZON_DMA+0x2c |
| 765 | #define AMAZON_DMA_CH0_ISR AMAZON_DMA+0x30 |
| 766 | #define AMAZON_DMA_CH1_ISR AMAZON_DMA+0x34 |
| 767 | #define AMAZON_DMA_CH2_ISR AMAZON_DMA+0x38 |
| 768 | #define AMAZON_DMA_CH3_ISR AMAZON_DMA+0x3c |
| 769 | #define AMAZON_DMA_CH4_ISR AMAZON_DMA+0x40 |
| 770 | #define AMAZON_DMA_CH5_ISR AMAZON_DMA+0x44 |
| 771 | #define AMAZON_DMA_CH6_ISR AMAZON_DMA+0x48 |
| 772 | #define AMAZON_DMA_CH7_ISR AMAZON_DMA+0x4c |
| 773 | #define AMAZON_DMA_CH8_ISR AMAZON_DMA+0x50 |
| 774 | #define AMAZON_DMA_CH9_ISR AMAZON_DMA+0x54 |
| 775 | #define AMAZON_DMA_CH10_ISR AMAZON_DMA+0x58 |
| 776 | #define AMAZON_DMA_CH11_ISR AMAZON_DMA+0x5c |
| 777 | #define AMAZON_DMA_CH0_MSK AMAZON_DMA+0x60 |
| 778 | #define AMAZON_DMA_CH1_MSK AMAZON_DMA+0x64 |
| 779 | #define AMAZON_DMA_CH2_MSK AMAZON_DMA+0x68 |
| 780 | #define AMAZON_DMA_CH3_MSK AMAZON_DMA+0x6c |
| 781 | #define AMAZON_DMA_CH4_MSK AMAZON_DMA+0x70 |
| 782 | #define AMAZON_DMA_CH5_MSK AMAZON_DMA+0x74 |
| 783 | #define AMAZON_DMA_CH6_MSK AMAZON_DMA+0x78 |
| 784 | #define AMAZON_DMA_CH7_MSK AMAZON_DMA+0x7c |
| 785 | #define AMAZON_DMA_CH8_MSK AMAZON_DMA+0x80 |
| 786 | #define AMAZON_DMA_CH9_MSK AMAZON_DMA+0x84 |
| 787 | #define AMAZON_DMA_CH10_MSK AMAZON_DMA+0x88 |
| 788 | #define AMAZON_DMA_CH11_MSK AMAZON_DMA+0x8c |
| 789 | #define AMAZON_DMA_Desc_BA AMAZON_DMA+0x90 |
| 790 | #define AMAZON_DMA_CH0_DES_LEN AMAZON_DMA+0x94 |
| 791 | #define AMAZON_DMA_CH1_DES_LEN AMAZON_DMA+0x98 |
| 792 | #define AMAZON_DMA_CH2_DES_LEN AMAZON_DMA+0x9c |
| 793 | #define AMAZON_DMA_CH3_DES_LEN AMAZON_DMA+0xa0 |
| 794 | #define AMAZON_DMA_CH4_DES_LEN AMAZON_DMA+0xa4 |
| 795 | #define AMAZON_DMA_CH5_DES_LEN AMAZON_DMA+0xa8 |
| 796 | #define AMAZON_DMA_CH6_DES_LEN AMAZON_DMA+0xac |
| 797 | #define AMAZON_DMA_CH7_DES_LEN AMAZON_DMA+0xb0 |
| 798 | #define AMAZON_DMA_CH8_DES_LEN AMAZON_DMA+0xb4 |
| 799 | #define AMAZON_DMA_CH9_DES_LEN AMAZON_DMA+0xb8 |
| 800 | #define AMAZON_DMA_CH10_DES_LEN AMAZON_DMA+0xbc |
| 801 | #define AMAZON_DMA_CH11_DES_LEN AMAZON_DMA+0xc0 |
| 802 | #define AMAZON_DMA_CH1_DES_OFST AMAZON_DMA+0xc4 |
| 803 | #define AMAZON_DMA_CH2_DES_OFST AMAZON_DMA+0xc8 |
| 804 | #define AMAZON_DMA_CH3_DES_OFST AMAZON_DMA+0xcc |
| 805 | #define AMAZON_DMA_CH4_DES_OFST AMAZON_DMA+0xd0 |
| 806 | #define AMAZON_DMA_CH5_DES_OFST AMAZON_DMA+0xd4 |
| 807 | #define AMAZON_DMA_CH6_DES_OFST AMAZON_DMA+0xd8 |
| 808 | #define AMAZON_DMA_CH7_DES_OFST AMAZON_DMA+0xdc |
| 809 | #define AMAZON_DMA_CH8_DES_OFST AMAZON_DMA+0xe0 |
| 810 | #define AMAZON_DMA_CH9_DES_OFST AMAZON_DMA+0xe4 |
| 811 | #define AMAZON_DMA_CH10_DES_OFST AMAZON_DMA+0xe8 |
| 812 | #define AMAZON_DMA_CH11_DES_OFST AMAZON_DMA+0xec |
| 813 | #define AMAZON_DMA_SW_BL AMAZON_DMA+0xf0 |
| 814 | #define AMAZON_DMA_TPE_BL AMAZON_DMA+0xf4 |
| 815 | #define AMAZON_DMA_DPlus2FPI_BL AMAZON_DMA+0xf8 |
| 816 | #define AMAZON_DMA_GRX_BUF_LEN AMAZON_DMA+0xfc |
| 817 | #define AMAZON_DMA_DMA_ECON_REG AMAZON_DMA+0x100 |
| 818 | #define AMAZON_DMA_POLLING_REG AMAZON_DMA+0x104 |
| 819 | #define AMAZON_DMA_CH_WGT AMAZON_DMA+0x108 |
| 820 | #define AMAZON_DMA_TX_WGT AMAZON_DMA+0x10c |
| 821 | #define AMAZON_DMA_DPLus2FPI_CLASS AMAZON_DMA+0x110 |
| 822 | #define AMAZON_DMA_COMB_ISR AMAZON_DMA+0x114 |
| 823 | |
| 824 | //channel reset |
| 825 | #define SWITCH1_RST_MASK 0x83 /* Switch1 channel mask */ |
| 826 | #define SWITCH2_RST_MASK 0x10C /* Switch1 channel mask */ |
| 827 | #define TPE_RST_MASK 0x630 /* TPE channel mask */ |
| 828 | #define DPlus2FPI_RST_MASK 0x840 /* DPlusFPI channel mask */ |
| 829 | |
| 830 | //ISR |
| 831 | #define DMA_ISR_RDERR 0x20 |
| 832 | #define DMA_ISR_CMDCPT 0x10 |
| 833 | #define DMA_ISR_CPT 0x8 |
| 834 | #define DMA_ISR_DURR 0x4 |
| 835 | #define DMA_ISR_EOP 0x2 |
| 836 | #define DMA_DESC_BYTEOFF_SHIFT 23 |
| 837 | |
| 838 | #define DMA_POLLING_ENABLE 0x80000000 |
| 839 | #define DMA_POLLING_CNT 0x50 /*minimum 0x10, max 0xfff0*/ |
| 840 | |
| 841 | /***********************************************************************/ |
| 842 | /* Module : Debug register address and bits */ |
| 843 | /***********************************************************************/ |
| 844 | |
| 845 | #define AMAZON_DEBUG (KSEG1+0x1F106000) |
| 846 | /***********************************************************************/ |
| 847 | |
| 848 | |
| 849 | /***MCD Break System Control Register***/ |
| 850 | #define AMAZON_DEBUG_MCD_BSCR ((volatile u32*)(AMAZON_DEBUG+ 0x0000)) |
| 851 | |
| 852 | /***PMC Performance Counter Control Register0***/ |
| 853 | #define AMAZON_DEBUG_PMC_PCCR0 ((volatile u32*)(AMAZON_DEBUG+ 0x0010)) |
| 854 | |
| 855 | /***PMC Performance Counter Control Register1***/ |
| 856 | #define AMAZON_DEBUG_PMC_PCCR1 ((volatile u32*)(AMAZON_DEBUG+ 0x0014)) |
| 857 | |
| 858 | /***PMC Performance Counter Register0***/ |
| 859 | #define AMAZON_DEBUG_PMC_PCR0 ((volatile u32*)(AMAZON_DEBUG+ 0x0018)) |
| 860 | |
| 861 | /*165001:henryhsu:20050603:Source modified by Bing Tao*/ |
| 862 | |
| 863 | /***PMC Performance Counter Register1***/ |
| 864 | //#define AMAZON_DEBUG_PMC_PCR1 ((volatile u32*)(AMAZON_DEBUG+ 0x0020)) |
| 865 | #define AMAZON_DEBUG_PMC_PCR1 ((volatile u32*)(AMAZON_DEBUG+ 0x001c)) |
| 866 | |
| 867 | /*165001*/ |
| 868 | |
| 869 | |
| 870 | |
| 871 | /***MCD Suspend Mode Control Register***/ |
| 872 | #define AMAZON_DEBUG_MCD_SMCR ((volatile u32*)(AMAZON_DEBUG+ 0x0024)) |
| 873 | |
| 874 | /***********************************************************************/ |
| 875 | /* Module : GPIO register address and bits */ |
| 876 | /***********************************************************************/ |
| 877 | |
| 878 | #define AMAZON_GPIO (KSEG1+0x10100B00) |
| 879 | /***********************************************************************/ |
| 880 | |
| 881 | |
| 882 | /***Port 0 Data Output Register (0010H)***/ |
| 883 | #define AMAZON_GPIO_P0_OUT ((volatile u32*)(AMAZON_GPIO+ 0x0010)) |
| 884 | |
| 885 | /***Port 1 Data Output Register (0040H)***/ |
| 886 | #define AMAZON_GPIO_P1_OUT ((volatile u32*)(AMAZON_GPIO+ 0x0040)) |
| 887 | |
| 888 | /***Port 0 Data Input Register (0014H)***/ |
| 889 | #define AMAZON_GPIO_P0_IN ((volatile u32*)(AMAZON_GPIO+ 0x0014)) |
| 890 | |
| 891 | /***Port 1 Data Input Register (0044H)***/ |
| 892 | #define AMAZON_GPIO_P1_IN ((volatile u32*)(AMAZON_GPIO+ 0x0044)) |
| 893 | |
| 894 | /***Port 0 Direction Register (0018H)***/ |
| 895 | #define AMAZON_GPIO_P0_DIR ((volatile u32*)(AMAZON_GPIO+ 0x0018)) |
| 896 | |
| 897 | /***Port 1 Direction Register (0048H)***/ |
| 898 | #define AMAZON_GPIO_P1_DIR ((volatile u32*)(AMAZON_GPIO+ 0x0048)) |
| 899 | |
| 900 | /***Port 0 Alternate Function Select Register 0 (001C H) ***/ |
| 901 | #define AMAZON_GPIO_P0_ALTSEL0 ((volatile u32*)(AMAZON_GPIO+ 0x001C)) |
| 902 | |
| 903 | /***Port 1 Alternate Function Select Register 0 (004C H) ***/ |
| 904 | #define AMAZON_GPIO_P1_ALTSEL0 ((volatile u32*)(AMAZON_GPIO+ 0x004C)) |
| 905 | |
| 906 | /***Port 0 Alternate Function Select Register 1 (0020 H) ***/ |
| 907 | #define AMAZON_GPIO_P0_ALTSEL1 ((volatile u32*)(AMAZON_GPIO+ 0x0020)) |
| 908 | |
| 909 | /***Port 1 Alternate Function Select Register 0 (0050 H) ***/ |
| 910 | #define AMAZON_GPIO_P1_ALTSEL1 ((volatile u32*)(AMAZON_GPIO+ 0x0050)) |
| 911 | |
| 912 | /***Port 0 Open Drain Control Register (0024H)***/ |
| 913 | #define AMAZON_GPIO_P0_OD ((volatile u32*)(AMAZON_GPIO+ 0x0024)) |
| 914 | |
| 915 | /***Port 1 Open Drain Control Register (0054H)***/ |
| 916 | #define AMAZON_GPIO_P1_OD ((volatile u32*)(AMAZON_GPIO+ 0x0054)) |
| 917 | |
| 918 | /***Port 0 Input Schmitt-Trigger Off Register (0028 H) ***/ |
| 919 | #define AMAZON_GPIO_P0_STOFF ((volatile u32*)(AMAZON_GPIO+ 0x0028)) |
| 920 | |
| 921 | /***Port 1 Input Schmitt-Trigger Off Register (0058 H) ***/ |
| 922 | #define AMAZON_GPIO_P1_STOFF ((volatile u32*)(AMAZON_GPIO+ 0x0058)) |
| 923 | |
| 924 | /***Port 0 Pull Up/Pull Down Select Register (002C H)***/ |
| 925 | #define AMAZON_GPIO_P0_PUDSEL ((volatile u32*)(AMAZON_GPIO+ 0x002C)) |
| 926 | |
| 927 | /***Port 1 Pull Up/Pull Down Select Register (005C H)***/ |
| 928 | #define AMAZON_GPIO_P1_PUDSEL ((volatile u32*)(AMAZON_GPIO+ 0x005C)) |
| 929 | |
| 930 | /***Port 0 Pull Up Device Enable Register (0030 H)***/ |
| 931 | #define AMAZON_GPIO_P0_PUDEN ((volatile u32*)(AMAZON_GPIO+ 0x0030)) |
| 932 | |
| 933 | /***Port 1 Pull Up Device Enable Register (0060 H)***/ |
| 934 | #define AMAZON_GPIO_P1_PUDEN ((volatile u32*)(AMAZON_GPIO+ 0x0060)) |
| 935 | |
| 936 | /***********************************************************************/ |
| 937 | /* Module : BIU register address and bits */ |
| 938 | /***********************************************************************/ |
| 939 | |
| 940 | #define AMAZON_BIU (KSEG1+0x1FA80000) |
| 941 | /***********************************************************************/ |
| 942 | |
| 943 | |
| 944 | /***BIU Identification Register***/ |
| 945 | #define AMAZON_BIU_ID ((volatile u32*)(AMAZON_BIU+ 0x0000)) |
| 946 | #define AMAZON_BIU_ID_ARCH (1 << 16) |
| 947 | #define AMAZON_BIU_ID_ID(value) (((( 1 << 8) - 1) & (value)) << 8) |
| 948 | #define AMAZON_BIU_ID_REV(value) (((( 1 << 8) - 1) & (value)) << 0) |
| 949 | |
| 950 | /***BIU Access Error Cause Register***/ |
| 951 | #define AMAZON_BIU_ERRCAUSE ((volatile u32*)(AMAZON_BIU+ 0x0100)) |
| 952 | #define AMAZON_BIU_ERRCAUSE_ERR (1 << 31) |
| 953 | #define AMAZON_BIU_ERRCAUSE_PORT(value) (((( 1 << 4) - 1) & (value)) << 16) |
| 954 | #define AMAZON_BIU_ERRCAUSE_CAUSE(value) (((( 1 << 2) - 1) & (value)) << 0) |
| 955 | |
| 956 | /***BIU Access Error Address Register***/ |
| 957 | #define AMAZON_BIU_ERRADDR ((volatile u32*)(AMAZON_BIU+ 0x0108)) |
| 958 | #define AMAZON_BIU_ERRADDR_ADDR |
| 959 | |
| 960 | /***********************************************************************/ |
| 961 | /* Module : ICU register address and bits */ |
| 962 | /***********************************************************************/ |
| 963 | |
| 964 | #define AMAZON_ICU (KSEG1+0x1F101000) |
| 965 | /***********************************************************************/ |
| 966 | |
| 967 | /***IM0 Interrupt Status Register***/ |
| 968 | #define AMAZON_ICU_IM0_ISR (AMAZON_ICU + 0x0010) |
| 969 | #define AMAZON_ICU_IM1_ISR (AMAZON_ICU + 0x0020) |
| 970 | #define AMAZON_ICU_IM2_ISR (AMAZON_ICU + 0x0030) |
| 971 | #define AMAZON_ICU_IM3_ISR (AMAZON_ICU + 0x0040) |
| 972 | #define AMAZON_ICU_IM4_ISR (AMAZON_ICU + 0x0050) |
| 973 | |
| 974 | /***IM0 Interrupt Enable Register***/ |
| 975 | #define AMAZON_ICU_IM0_IER (AMAZON_ICU + 0x0014) |
| 976 | #define AMAZON_ICU_IM1_IER (AMAZON_ICU + 0x0024) |
| 977 | #define AMAZON_ICU_IM2_IER (AMAZON_ICU + 0x0034) |
| 978 | #define AMAZON_ICU_IM3_IER (AMAZON_ICU + 0x0044) |
| 979 | #define AMAZON_ICU_IM4_IER (AMAZON_ICU + 0x0054) |
| 980 | |
| 981 | /***IM0 Interrupt Output Status Register***/ |
| 982 | #define AMAZON_ICU_IM0_IOSR (AMAZON_ICU + 0x0018) |
| 983 | #define AMAZON_ICU_IM1_IOSR (AMAZON_ICU + 0x0028) |
| 984 | #define AMAZON_ICU_IM2_IOSR (AMAZON_ICU + 0x0038) |
| 985 | #define AMAZON_ICU_IM3_IOSR (AMAZON_ICU + 0x0048) |
| 986 | #define AMAZON_ICU_IM4_IOSR (AMAZON_ICU + 0x0058) |
| 987 | |
| 988 | /***IM0 Interrupt Request Set Register***/ |
| 989 | #define AMAZON_ICU_IM0_IRSR (AMAZON_ICU + 0x001c) |
| 990 | #define AMAZON_ICU_IM1_IRSR (AMAZON_ICU + 0x002c) |
| 991 | #define AMAZON_ICU_IM2_IRSR (AMAZON_ICU + 0x003c) |
| 992 | #define AMAZON_ICU_IM3_IRSR (AMAZON_ICU + 0x004c) |
| 993 | #define AMAZON_ICU_IM4_IRSR (AMAZON_ICU + 0x005c) |
| 994 | |
| 995 | /***Interrupt Vector Value Register***/ |
| 996 | #define AMAZON_ICU_IM_VEC (AMAZON_ICU + 0x0060) |
| 997 | |
| 998 | /***Interrupt Vector Value Mask***/ |
| 999 | #define AMAZON_ICU_IM0_VEC_MASK 0x0000001f |
| 1000 | #define AMAZON_ICU_IM1_VEC_MASK 0x000003e0 |
| 1001 | #define AMAZON_ICU_IM2_VEC_MASK 0x00007c00 |
| 1002 | #define AMAZON_ICU_IM3_VEC_MASK 0x000f8000 |
| 1003 | #define AMAZON_ICU_IM4_VEC_MASK 0x01f00000 |
| 1004 | |
| 1005 | /***DMA Interrupt Mask Value***/ |
| 1006 | #define AMAZON_DMA_H_MASK 0x00000fff |
| 1007 | |
| 1008 | /***External Interrupt Control Register***/ |
| 1009 | #define AMAZON_ICU_EXTINTCR ((volatile u32*)(AMAZON_ICU + 0x0000)) |
| 1010 | #define AMAZON_ICU_IRNICR ((volatile u32*)(AMAZON_ICU + 0x0004)) |
| 1011 | #define AMAZON_ICU_IRNCR ((volatile u32*)(AMAZON_ICU + 0x0008)) |
| 1012 | #define AMAZON_ICU_IRNEN ((volatile u32*)(AMAZON_ICU + 0x000c)) |
| 1013 | |
| 1014 | /***********************************************************************/ |
| 1015 | /* Module : PCI/Card-BUS/PC-Card register address and bits */ |
| 1016 | /***********************************************************************/ |
| 1017 | |
| 1018 | #define AMAZON_PCI (KSEG1+0x10105400) |
| 1019 | #define AMAZON_PCI_CFG_BASE (KSEG1+0x11000000) |
| 1020 | #define AMAZON_PCI_MEM_BASE (KSEG1+0x12000000) |
| 1021 | |
| 1022 | #define CLOCK_CONTROL AMAZON_PCI + 0x00000000 |
| 1023 | #define ARB_CTRL_bit 1 |
| 1024 | #define IDENTIFICATION AMAZON_PCI + 0x00000004 |
| 1025 | #define SOFTRESET AMAZON_PCI + 0x00000010 |
| 1026 | #define PCI_FPI_ERROR_ADDRESS AMAZON_PCI + 0x00000014 |
| 1027 | #define FPI_PCI_ERROR_ADDRESS AMAZON_PCI + 0x00000018 |
| 1028 | #define FPI_ERROR_TAG AMAZON_PCI + 0x0000001c |
| 1029 | #define IRR AMAZON_PCI + 0x00000020 |
| 1030 | #define IRA_IR AMAZON_PCI + 0x00000024 |
| 1031 | #define IRM AMAZON_PCI + 0x00000028 |
| 1032 | #define DMA_COMPLETE_BIT 0 |
| 1033 | #define PCI_POWER_CHANGE_BIT 16 |
| 1034 | #define PCI_MASTER0_BROKEN_INT_BIT 24 |
| 1035 | #define PCI_MASTER1_BROKEN_INT_BIT 25 |
| 1036 | #define PCI_MASTER2_BROKEN_INT_BIT 26 |
| 1037 | #define EOI AMAZON_PCI + 0x0000002c |
| 1038 | #define PCI_MODE AMAZON_PCI + 0x00000030 |
| 1039 | #define PCI_MODE_cfgok_bit 24 |
| 1040 | #define DEVICE_VENDOR_ID AMAZON_PCI + 0x00000034 |
| 1041 | #define SUBSYSTEM_VENDOR_ID AMAZON_PCI + 0x00000038 |
| 1042 | #define POWER_MANAGEMENT AMAZON_PCI + 0x0000003c |
| 1043 | #define CLASS_CODE1 AMAZON_PCI + 0x00000040 |
| 1044 | #define BAR11_MASK AMAZON_PCI + 0x00000044 |
| 1045 | #define BAR12_MASK AMAZON_PCI + 0x00000048 |
| 1046 | #define BAR13_MASK AMAZON_PCI + 0x0000004c |
| 1047 | #define BAR14_MASK AMAZON_PCI + 0x00000050 |
| 1048 | #define BAR15_MASK AMAZON_PCI + 0x00000054 |
| 1049 | #define BAR16_MASK AMAZON_PCI + 0x00000058 |
| 1050 | #define CARDBUS_CIS_POINTER1 AMAZON_PCI + 0x0000005c |
| 1051 | #define SUBSYSTEM_ID1 AMAZON_PCI + 0x00000060 |
| 1052 | #define PCI_ADDRESS_MAP_11 AMAZON_PCI + 0x00000064 |
| 1053 | #define PCI_ADDRESS_MAP_12 AMAZON_PCI + 0x00000068 |
| 1054 | #define PCI_ADDRESS_MAP_13 AMAZON_PCI + 0x0000006c |
| 1055 | #define PCI_ADDRESS_MAP_14 AMAZON_PCI + 0x00000070 |
| 1056 | #define PCI_ADDRESS_MAP_15 AMAZON_PCI + 0x00000074 |
| 1057 | #define PCI_ADDRESS_MAP_16 AMAZON_PCI + 0x00000078 |
| 1058 | #define FPI_SEGMENT_ENABLE AMAZON_PCI + 0x0000007c |
| 1059 | #define CLASS_CODE2 AMAZON_PCI + 0x00000080 |
| 1060 | #define BAR21_MASK AMAZON_PCI + 0x00000084 |
| 1061 | #define BAR22_MASK AMAZON_PCI + 0x00000088 |
| 1062 | #define BAR23_MASK AMAZON_PCI + 0x0000008c |
| 1063 | #define BAR24_MASK AMAZON_PCI + 0x00000090 |
| 1064 | #define BAR25_MASK AMAZON_PCI + 0x00000094 |
| 1065 | #define BAR26_MASK AMAZON_PCI + 0x00000098 |
| 1066 | #define CARDBUS_CIS_POINTER2 AMAZON_PCI + 0x0000009c |
| 1067 | #define SUBSYSTEM_ID2 AMAZON_PCI + 0x000000a0 |
| 1068 | #define PCI_ADDRESS_MAP_21 AMAZON_PCI + 0x000000a4 |
| 1069 | #define PCI_ADDRESS_MAP_22 AMAZON_PCI + 0x000000a8 |
| 1070 | #define PCI_ADDRESS_MAP_23 AMAZON_PCI + 0x000000ac |
| 1071 | #define PCI_ADDRESS_MAP_24 AMAZON_PCI + 0x000000b0 |
| 1072 | #define PCI_ADDRESS_MAP_25 AMAZON_PCI + 0x000000b4 |
| 1073 | #define PCI_ADDRESS_MAP_26 AMAZON_PCI + 0x000000b8 |
| 1074 | #define FPI_ADDRESS_MASK11LOW AMAZON_PCI + 0x000000bc |
| 1075 | #define FPI_ADDRESS_MAP_0 AMAZON_PCI + 0x000000c0 |
| 1076 | #define FPI_ADDRESS_MAP_1 AMAZON_PCI + 0x000000c4 |
| 1077 | #define FPI_ADDRESS_MAP_2 AMAZON_PCI + 0x000000c8 |
| 1078 | #define FPI_ADDRESS_MAP_3 AMAZON_PCI + 0x000000cc |
| 1079 | #define FPI_ADDRESS_MAP_4 AMAZON_PCI + 0x000000d0 |
| 1080 | #define FPI_ADDRESS_MAP_5 AMAZON_PCI + 0x000000d4 |
| 1081 | #define FPI_ADDRESS_MAP_6 AMAZON_PCI + 0x000000d8 |
| 1082 | #define FPI_ADDRESS_MAP_7 AMAZON_PCI + 0x000000dc |
| 1083 | #define FPI_ADDRESS_MAP_11LOW AMAZON_PCI + 0x000000e0 |
| 1084 | #define FPI_ADDRESS_MAP_11HIGH AMAZON_PCI + 0x000000e4 |
| 1085 | #define FPI_BURST_LENGTH AMAZON_PCI + 0x000000e8 |
| 1086 | #define SET_PCI_SERR AMAZON_PCI + 0x000000ec |
| 1087 | #define DMA_FPI_START_ADDR AMAZON_PCI + 0x000000f0 |
| 1088 | #define DMA_PCI_START_ADDR AMAZON_PCI + 0x000000f4 |
| 1089 | #define DMA_TRANSFER_COUNT AMAZON_PCI + 0x000000f8 |
| 1090 | #define DMA_CONTROL_STATUS AMAZON_PCI + 0x000000fc |
| 1091 | |
| 1092 | #define EXT_PCI1_CONFIG_SPACE_BASE_ADDR AMAZON_PCI_CFG_BASE + 0x0800 |
| 1093 | #define EXT_PCI2_CONFIG_SPACE_BASE_ADDR AMAZON_PCI_CFG_BASE + 0x1000 |
| 1094 | #define EXT_PCI3_CONFIG_SPACE_BASE_ADDR AMAZON_PCI_CFG_BASE + 0x1800 |
| 1095 | #define EXT_PCI4_CONFIG_SPACE_BASE_ADDR AMAZON_PCI_CFG_BASE + 0x2000 |
| 1096 | #define EXT_PCI5_CONFIG_SPACE_BASE_ADDR AMAZON_PCI_CFG_BASE + 0x2800 |
| 1097 | #define EXT_PCI6_CONFIG_SPACE_BASE_ADDR AMAZON_PCI_CFG_BASE + 0x3000 |
| 1098 | #define EXT_PCI7_CONFIG_SPACE_BASE_ADDR AMAZON_PCI_CFG_BASE + 0x3800 |
| 1099 | #define EXT_PCI8_CONFIG_SPACE_BASE_ADDR AMAZON_PCI_CFG_BASE + 0x4000 |
| 1100 | #define EXT_PCI9_CONFIG_SPACE_BASE_ADDR AMAZON_PCI_CFG_BASE + 0x4800 |
| 1101 | #define EXT_PCI10_CONFIG_SPACE_BASE_ADDR AMAZON_PCI_CFG_BASE + 0x5000 |
| 1102 | #define EXT_PCI11_CONFIG_SPACE_BASE_ADDR AMAZON_PCI_CFG_BASE + 0x5800 |
| 1103 | #define EXT_PCI12_CONFIG_SPACE_BASE_ADDR AMAZON_PCI_CFG_BASE + 0x6000 |
| 1104 | #define EXT_PCI13_CONFIG_SPACE_BASE_ADDR AMAZON_PCI_CFG_BASE + 0x6800 |
| 1105 | #define EXT_PCI14_CONFIG_SPACE_BASE_ADDR AMAZON_PCI_CFG_BASE + 0x7000 |
| 1106 | #define EXT_PCI15_CONFIG_SPACE_BASE_ADDR AMAZON_PCI_CFG_BASE + 0x7800 |
| 1107 | #define EXT_CARDBUS_CONFIG_SPACE_BASE_ADDR AMAZON_PCI_CFG_BASE + 0XF000 |
| 1108 | #define EXT_PCI_BAR1_ADDR 0x10 |
| 1109 | #define EXT_PCI_BAR2_ADDR 0x14 |
| 1110 | #define EXT_PCI_BAR3_ADDR 0x18 |
| 1111 | #define EXT_PCI_BAR4_ADDR 0x1C |
| 1112 | #define EXT_PCI_BAR5_ADDR 0x20 |
| 1113 | #define EXT_PCI_BAR6_ADDR 0x24 |
| 1114 | |
| 1115 | #define DEVICE_ID_VECDOR_ID_ADDR AMAZON_PCI_CFG_BASE + 0x0 |
| 1116 | #define STATUS_COMMAND_ADDR AMAZON_PCI_CFG_BASE + 0x4 |
| 1117 | #define BUS_MASTER_ENABLE_BIT 2 |
| 1118 | #define MEM_SPACE_ENABLE_BIT 1 |
| 1119 | #define CLASS_CODE_REVISION_ADDR AMAZON_PCI_CFG_BASE + 0x8 |
| 1120 | #define BIST_HEADER_TYPE_LATENCY_CAHCE_ADDR AMAZON_PCI_CFG_BASE + 0xC |
| 1121 | #define BAR1_ADDR AMAZON_PCI_CFG_BASE + 0x10 |
| 1122 | #define BAR2_ADDR AMAZON_PCI_CFG_BASE + 0x14 |
| 1123 | #define BAR3_ADDR AMAZON_PCI_CFG_BASE + 0x18 |
| 1124 | #define BAR4_ADDR AMAZON_PCI_CFG_BASE + 0x1C |
| 1125 | #define BAR3_ADDR AMAZON_PCI_CFG_BASE + 0x18 |
| 1126 | #define BAR4_ADDR AMAZON_PCI_CFG_BASE + 0x1C |
| 1127 | #define BAR5_ADDR AMAZON_PCI_CFG_BASE + 0x20 |
| 1128 | #define BAR6_ADDR AMAZON_PCI_CFG_BASE + 0x24 |
| 1129 | #define CARDBUS_CIS_POINTER_ADDR AMAZON_PCI_CFG_BASE + 0x28 |
| 1130 | #define SUBSYSTEM_ID_VENDOR_ID_ADDR AMAZON_PCI_CFG_BASE + 0x2C |
| 1131 | #define EXPANSION_ROM_BASE_ADDR AMAZON_PCI_CFG_BASE + 0x30 |
| 1132 | #define CAPABILITIES_POINTER_ADDR AMAZON_PCI_CFG_BASE + 0x34 |
| 1133 | #define RESERVED_0x38 AMAZON_PCI_CFG_BASE + 0x38 |
| 1134 | #define MAX_LAT_MIN_GNT_INT_PIN_LINE_ADDR AMAZON_PCI_CFG_BASE + 0x3C |
| 1135 | #define POWER_MNGT_NEXT_POINTER_CAP_ID_ADDR AMAZON_PCI_CFG_BASE + 0x40 |
| 1136 | #define POWER_MANAGEMENT_CTRL_STATUS_ADDR AMAZON_PCI_CFG_BASE + 0x44 |
| 1137 | #define RESERVED_0x48 AMAZON_PCI_CFG_BASE + 0x48 |
| 1138 | #define RESERVED_0x4C AMAZON_PCI_CFG_BASE + 0x4C |
| 1139 | #define ERROR_ADDR_PCI_FPI_ADDR AMAZON_PCI_CFG_BASE + 0x50 |
| 1140 | #define ERROR_ADdR_FPI_PCI_ADDR AMAZON_PCI_CFG_BASE + 0x54 |
| 1141 | #define ERROR_TAG_FPI_PCI_ADDR AMAZON_PCI_CFG_BASE + 0x58 |
| 1142 | #define PCI_ARB_CTRL_STATUS_ADDR AMAZON_PCI_CFG_BASE + 0x5C |
| 1143 | #define INTERNAL_ARB_ENABLE_BIT 0 |
| 1144 | #define ARB_SCHEME_BIT 1 |
| 1145 | #define PCI_MASTER0_PRIOR_2BITS 2 |
| 1146 | #define PCI_MASTER1_PRIOR_2BITS 4 |
| 1147 | #define PCI_MASTER2_PRIOR_2BITS 6 |
| 1148 | #define PCI_MASTER0_REQ_MASK_2BITS 8 |
| 1149 | #define PCI_MASTER1_REQ_MASK_2BITS 10 |
| 1150 | #define PCI_MASTER2_REQ_MASK_2BITS 12 |
| 1151 | #define PCI_MASTER0_GNT_MASK_2BITS 14 |
| 1152 | #define PCI_MASTER1_GNT_MASK_2BITS 16 |
| 1153 | #define PCI_MASTER2_GNT_MASK_2BITS 18 |
| 1154 | #define FPI_PCI_INT_STATUS_ADDR AMAZON_PCI_CFG_BASE + 0x60 |
| 1155 | #define FPI_PCI_INT_ACK_ADDR AMAZON_PCI_CFG_BASE + 0x64 |
| 1156 | #define FPI_PCI_INT_MASK_ADDR AMAZON_PCI_CFG_BASE + 0x68 |
| 1157 | #define CARDBUS_CTRL_STATUS_ADDR AMAZON_PCI_CFG_BASE + 0x6C |
| 1158 | #define CARDBUS_CFRAME_ENABLE 0 |
| 1159 | |
| 1160 | #define CLOCK_CONTROL_default 0x00000000 |
| 1161 | #define CLOCK_CONTROL_mask 0x00000003 |
| 1162 | |
| 1163 | #define IDENTIFICATION_default 0x0011C002 |
| 1164 | #define IDENTIFICATION_mask 0x00000000 |
| 1165 | |
| 1166 | #define SOFTRESET_default 0x00000000 |
| 1167 | // SOFTRESET bit 0 is writable but will be reset to 0 after software reset is over |
| 1168 | #define SOFTRESET_mask 0x00000000 |
| 1169 | |
| 1170 | #define PCI_FPI_ERROR_ADDRESS_default 0xFFFFFFFF |
| 1171 | #define PCI_FPI_ERROR_ADDRESS_mask 0x00000000 |
| 1172 | |
| 1173 | #define FPI_PCI_ERROR_ADDRESS_default 0xFFFFFFFF |
| 1174 | #define FPI_PCI_ERROR_ADDRESS_mask 0x00000000 |
| 1175 | |
| 1176 | #define FPI_ERROR_TAG_default 0x0000000F |
| 1177 | #define FPI_ERROR_TAG_mask 0x00000000 |
| 1178 | |
| 1179 | #define IRR_default 0x00000000 |
| 1180 | #define IRR_mask 0x07013b2F |
| 1181 | |
| 1182 | #define IRA_IR_default 0x00000000 |
| 1183 | #define IRA_IR_mask 0x07013b2F |
| 1184 | |
| 1185 | #define IRM_default 0x00000000 |
| 1186 | #define IRM_mask 0xFFFFFFFF |
| 1187 | |
| 1188 | #define EOI_default 0x00000000 |
| 1189 | #define EOI_mask 0x00000000 |
| 1190 | |
| 1191 | #define PCI_MODE_default 0x01000103 |
| 1192 | #define PCI_MODE_mask 0x1107070F |
| 1193 | |
| 1194 | #define DEVICE_VENDOR_ID_default 0x000C15D1 |
| 1195 | #define DEVICE_VENDOR_ID_mask 0xFFFFFFFF |
| 1196 | |
| 1197 | #define SUBSYSTEM_VENDOR_ID_default 0x000015D1 |
| 1198 | #define SUBSYSTEM_VENDOR_ID_mask 0x0000FFFF |
| 1199 | |
| 1200 | #define POWER_MANAGEMENT_default 0x0000001B |
| 1201 | #define POWER_MANAGEMENT_mask 0x0000001F |
| 1202 | |
| 1203 | #define CLASS_CODE1_default 0x00028000 |
| 1204 | #define CLASS_CODE1_mask 0x00FFFFFF |
| 1205 | |
| 1206 | #define BAR11_MASK_default 0x0FF00008 |
| 1207 | #define BAR11_MASK_mask 0x8FF00008 |
| 1208 | |
| 1209 | #define BAR12_MASK_default 0x80001800 |
| 1210 | #define BAR12_MASK_mask 0x80001F08 |
| 1211 | |
| 1212 | #define BAR13_MASK_default 0x8FF00008 |
| 1213 | #define BAR13_MASK_mask 0x8FF00008 |
| 1214 | |
| 1215 | #define BAR14_MASK_default 0x8F000000 |
| 1216 | #define BAR14_MASK_mask 0x8FFFFF08 |
| 1217 | |
| 1218 | #define BAR15_MASK_default 0x80000000 |
| 1219 | #define BAR15_MASK_mask 0x8FFFFF08 |
| 1220 | |
| 1221 | #define BAR16_MASK_default 0x80000001 |
| 1222 | // bit 0 and bit 3 is mutually exclusive |
| 1223 | #define BAR16_MASK_mask 0x8FFFFFF9 |
| 1224 | |
| 1225 | #define CARDBUS_CIS_POINTER1_default 0x00000000 |
| 1226 | #define CARDBUS_CIS_POINTER1_mask 0x03FFFFFF |
| 1227 | |
| 1228 | #define SUBSYSTEM_ID1_default 0x0000000C |
| 1229 | #define SUBSYSTEM_ID1_mask 0x0000FFFF |
| 1230 | |
| 1231 | #define PCI_ADDRESS_MAP_11_default 0x18000000 |
| 1232 | #define PCI_ADDRESS_MAP_11_mask 0x7FFFFFF1 |
| 1233 | |
| 1234 | #define PCI_ADDRESS_MAP_12_default 0x18100000 |
| 1235 | #define PCI_ADDRESS_MAP_12_mask 0x7FFFFF01 |
| 1236 | |
| 1237 | #define PCI_ADDRESS_MAP_13_default 0x18200000 |
| 1238 | #define PCI_ADDRESS_MAP_13_mask 0x7FF00001 |
| 1239 | |
| 1240 | #define PCI_ADDRESS_MAP_14_default 0x70000000 |
| 1241 | #define PCI_ADDRESS_MAP_14_mask 0x7FFFFF01 |
| 1242 | |
| 1243 | #define PCI_ADDRESS_MAP_15_default 0x00000001 |
| 1244 | #define PCI_ADDRESS_MAP_15_mask 0x7FFFFF01 |
| 1245 | |
| 1246 | #define PCI_ADDRESS_MAP_16_default 0x60000000 |
| 1247 | #define PCI_ADDRESS_MAP_16_mask 0x7FF00001 |
| 1248 | |
| 1249 | #define FPI_SEGMENT_ENABLE_default 0x000003FF |
| 1250 | #define FPI_SEGMENT_ENABLE_mask 0x000003FF |
| 1251 | |
| 1252 | #define CLASS_CODE2_default 0x00FF0000 |
| 1253 | #define CLASS_CODE2_mask 0x00FFFFFF |
| 1254 | |
| 1255 | #define BAR21_MASK_default 0x80000008 |
| 1256 | #define BAR21_MASK_mask 0x8FFFFFF8 |
| 1257 | |
| 1258 | #define BAR22_MASK_default 0x80000008 |
| 1259 | #define BAR22_MASK_mask 0x80001F08 |
| 1260 | |
| 1261 | #define BAR23_MASK_default 0x80000008 |
| 1262 | #define BAR23_MASK_mask 0x8FF00008 |
| 1263 | |
| 1264 | #define BAR24_MASK_default 0x8FE00000 |
| 1265 | #define BAR24_MASK_mask 0x8FFFFF08 |
| 1266 | |
| 1267 | #define BAR25_MASK_default 0x8FFFF000 |
| 1268 | #define BAR25_MASK_mask 0x8FFFFF08 |
| 1269 | |
| 1270 | #define BAR26_MASK_default 0x8FFFFFE1 |
| 1271 | #define BAR26_MASK_mask 0x8FFFFFF1 |
| 1272 | |
| 1273 | #define CARDBUS_CIS_POINTER2_default 0x00000000 |
| 1274 | #define CARDBUS_CIS_POINTER2_mask 0x03FFFFFF |
| 1275 | |
| 1276 | #define SUBSYSTEM_ID2_default 0x0000000C |
| 1277 | #define SUBSYSTEM_ID2_mask 0x0000FFFF |
| 1278 | |
| 1279 | #define PCI_ADDRESS_MAP_21_default 0x3FE00000 |
| 1280 | #define PCI_ADDRESS_MAP_21_mask 0x7FFFFFF1 |
| 1281 | |
| 1282 | #define PCI_ADDRESS_MAP_22_default 0x68000000 |
| 1283 | #define PCI_ADDRESS_MAP_22_mask 0x7FFFFF01 |
| 1284 | |
| 1285 | #define PCI_ADDRESS_MAP_23_default 0x20000000 |
| 1286 | #define PCI_ADDRESS_MAP_23_mask 0x7FF00001 |
| 1287 | |
| 1288 | #define PCI_ADDRESS_MAP_24_default 0x70000001 |
| 1289 | #define PCI_ADDRESS_MAP_24_mask 0x7FFFFF01 |
| 1290 | |
| 1291 | #define PCI_ADDRESS_MAP_25_default 0x78000001 |
| 1292 | #define PCI_ADDRESS_MAP_25_mask 0x7FFFFF01 |
| 1293 | |
| 1294 | #define PCI_ADDRESS_MAP_26_default 0x20000000 |
| 1295 | #define PCI_ADDRESS_MAP_26_mask 0x7FF00001 |
| 1296 | |
| 1297 | #define FPI_ADDRESS_MASK11LOW_default 0x00000000 |
| 1298 | #define FPI_ADDRESS_MASK11LOW_mask 0x00070000 |
| 1299 | |
| 1300 | #define FPI_ADDRESS_MAP_0_default 0x00000000 |
| 1301 | #define FPI_ADDRESS_MAP_0_mask 0xFFF00000 |
| 1302 | |
| 1303 | #define FPI_ADDRESS_MAP_1_default 0x10000000 |
| 1304 | #define FPI_ADDRESS_MAP_1_mask 0xFFF00000 |
| 1305 | |
| 1306 | #define FPI_ADDRESS_MAP_2_default 0x20000000 |
| 1307 | #define FPI_ADDRESS_MAP_2_mask 0xFFF00000 |
| 1308 | |
| 1309 | #define FPI_ADDRESS_MAP_3_default 0x30000000 |
| 1310 | #define FPI_ADDRESS_MAP_3_mask 0xFFF00000 |
| 1311 | |
| 1312 | #define FPI_ADDRESS_MAP_4_default 0x40000000 |
| 1313 | #define FPI_ADDRESS_MAP_4_mask 0xFFF00000 |
| 1314 | |
| 1315 | #define FPI_ADDRESS_MAP_5_default 0x50000000 |
| 1316 | #define FPI_ADDRESS_MAP_5_mask 0xFFF00000 |
| 1317 | |
| 1318 | #define FPI_ADDRESS_MAP_6_default 0x60000000 |
| 1319 | #define FPI_ADDRESS_MAP_6_mask 0xFFF00000 |
| 1320 | |
| 1321 | #define FPI_ADDRESS_MAP_7_default 0x70000000 |
| 1322 | #define FPI_ADDRESS_MAP_7_mask 0xFFF00000 |
| 1323 | |
| 1324 | #define FPI_ADDRESS_MAP_11LOW_default 0xB0000000 |
| 1325 | #define FPI_ADDRESS_MAP_11LOW_mask 0xFFFF0000 |
| 1326 | |
| 1327 | #define FPI_ADDRESS_MAP_11HIGH_default 0xB8000000 |
| 1328 | #define FPI_ADDRESS_MAP_11HIGH_mask 0xFFF80000 |
| 1329 | |
| 1330 | #define FPI_BURST_LENGTH_default 0x00000000 |
| 1331 | #define FPI_BURST_LENGTH_mask 0x00000303 |
| 1332 | |
| 1333 | #define SET_PCI_SERR_default 0x00000000 |
| 1334 | #define SET_PCI_SERR_mask 0x00000000 |
| 1335 | |
| 1336 | #define DMA_FPI_START_ADDRESS_default 0x00000000 |
| 1337 | #define DMA_FPI_START_ADDRESS_mask 0xFFFFFFFF |
| 1338 | |
| 1339 | #define DMA_PCI_START_ADDRESS_default 0x00000000 |
| 1340 | #define DMA_PCI_START_ADDRESS_mask 0xFFFFFFFF |
| 1341 | |
| 1342 | #define DMA_TRANSFER_COUNT_default 0x00000000 |
| 1343 | #define DMA_TRANSFER_COUNT_mask 0x0000FFFF |
| 1344 | |
| 1345 | #define DMA_CONTROL_STATUS_default 0x00000000 |
| 1346 | #define DMA_CONTROL_STATUS_mask 0x00000000 // bit 0,1 is writable |
| 1347 | |
| 1348 | /***********************************************************************/ |
| 1349 | #undef IKOS_MINI_BOOT //don't run a full booting |
| 1350 | #ifdef CONFIG_USE_IKOS |
| 1351 | #define CONFIG_USE_VENUS //Faster, 10M CPU and 192k baudrate |
| 1352 | #ifdef CONFIG_USE_VENUS |
| 1353 | #define IKOS_CPU_SPEED 10000000 |
| 1354 | #else |
| 1355 | #define IKOS_CPU_SPEED 180000 //IKOS is slow |
| 1356 | #endif |
| 1357 | #endif //CONFIG_USE_IKOS |
| 1358 | |
| 1359 | /* 165001:henryhsu:20050603:Source Modify form Bing Tao */ |
| 1360 | |
| 1361 | #if defined(CONFIG_NET_WIRELESS_SPURS) || defined(CONFIG_NET_WIRELESS_SPURS_MODULE) |
| 1362 | #define EBU_PCI_SOFTWARE_ARBITOR |
| 1363 | #endif |
| 1364 | |
| 1365 | #define AMAZON_B11 |
| 1366 | #ifdef AMAZON_B11 |
| 1367 | #define SWITCH_BUF_FPI_ADDR (0x10110000) |
| 1368 | #define SWITCH_BUF_ADDR (KSEG1+SWITCH_BUF_FPI_ADDR) |
| 1369 | #define SWITCH_BUF_SIZE (0x2800) |
| 1370 | #define AMAZON_B11_CBM_QD_ADDR (SWITCH_BUF_ADDR+0x0) |
| 1371 | #define AMAZON_B11_BOND_CELL_ADDR (SWITCH_BUF_ADDR+0x000) |
| 1372 | #endif |
| 1373 | #define AMAZON_REFERENCE_BOARD |
| 1374 | //for AMAZON ATM bonding application |
| 1375 | #ifdef AMAZON_REFERENCE_BOARD |
| 1376 | #define GPIO_DETECT_LOW |
| 1377 | #else |
| 1378 | #undef GPIO_DETECT_LOW |
| 1379 | #endif |
| 1380 | |
| 1381 | /* 165001 */ |
| 1382 | |
| 1383 | #undef AMAZON_IKOS_DEBUG_MSG |
| 1384 | #undef AMAZON_INT_DEBUG_MSG |
| 1385 | #undef AMAZON_ATM_DEBUG_MSG |
| 1386 | #undef AMAZON_DMA_DEBUG_MSG |
| 1387 | #undef AMAZON_SW_DEBUG_MSG |
| 1388 | #undef AMAZON_WDT_DEBUG_MSG |
| 1389 | #undef AMAZON_MTD_DEBUG_MSG |
| 1390 | #undef AMAZON_SSC_DEBUG_MSG |
| 1391 | #undef AMAZON_MEI_DEBUG_MSG |
| 1392 | |
| 1393 | #ifdef AMAZON_IKOS_DEBUG_MSG |
| 1394 | #define AMAZON_IKOS_DMSG(fmt,args...) printk("%s:" fmt, __FUNCTION__, ##args) |
| 1395 | #else |
| 1396 | #define AMAZON_IKOS_DMSG(fmt,args...) |
| 1397 | #endif |
| 1398 | |
| 1399 | #ifdef AMAZON_WDT_DEBUG_MSG |
| 1400 | #define AMAZON_WDT_DMSG(fmt, args...) printk( "%s: " fmt, __FUNCTION__ , ##args) |
| 1401 | #else |
| 1402 | #define AMAZON_WDT_DMSG(fm,args...) |
| 1403 | #endif |
| 1404 | |
| 1405 | #ifdef AMAZON_SSC_DEBUG_MSG |
| 1406 | #define AMAZON_SSC_DMSG(fmt, args...) printk( "%s: " fmt, __FUNCTION__ , ##args) |
| 1407 | #else |
| 1408 | #define AMAZON_SSC_DMSG(fm,args...) |
| 1409 | #endif |
| 1410 | |
| 1411 | #ifdef AMAZON_DMA_DEBUG_MSG |
| 1412 | #define AMAZON_DMA_DMSG(fmt, args...) printk( "%s: " fmt, __FUNCTION__ , ##args) |
| 1413 | #else |
| 1414 | #define AMAZON_DMA_DMSG(fm,args...) |
| 1415 | #endif |
| 1416 | |
| 1417 | #ifdef AMAZON_ATM_DEBUG_MSG |
| 1418 | #define AMAZON_TPE_DMSG(fmt, args...) printk( "%s: " fmt, __FUNCTION__ , ##args) |
| 1419 | #else //not AMAZON_ATM_DEBUG |
| 1420 | #define AMAZON_TPE_DMSG(fmt, args...) |
| 1421 | #endif //AMAZON_ATM_DEBUG |
| 1422 | |
| 1423 | #ifdef AMAZON_SW_DEBUG_MSG |
| 1424 | #define AMAZON_SW_DMSG(fmt,args...) printk("%s: " fmt, __FUNCTION__ , ##args) |
| 1425 | #else |
| 1426 | #define AMAZON_SW_DMSG(fmt,args...) |
| 1427 | #endif |
| 1428 | |
| 1429 | #ifdef AMAZON_MTD_DEBUG_MSG |
| 1430 | #define AMAZON_MTD_DMSG(fmt,args...) printk("%s: " fmt, __FUNCTION__ , ##args) |
| 1431 | #else |
| 1432 | #define AMAZON_MTD_DMSG(fmt,args...) |
| 1433 | #endif |
| 1434 | |
| 1435 | #ifdef AMAZON_INT_DEBUG_MSG |
| 1436 | #define AMAZON_INT_DMSG(x...) printk(x) |
| 1437 | #else |
| 1438 | #define AMAZON_INT_DMSG(x...) |
| 1439 | #endif |
| 1440 | |
| 1441 | #ifdef AMAZON_MEI_DEBUG_MSG |
| 1442 | #define AMAZON_MEI_DMSG(fmt,args...) printk("%s:" fmt, __FUNCTION__, ##args) |
| 1443 | #else |
| 1444 | #define AMAZON_MEI_DMSG(fmt,args...) |
| 1445 | #endif |
| 1446 | |
| 1447 | #endif //AMAZON_H |
| 1448 | |
