| 1 | #ifndef AMAZON_SW_H |
| 2 | #define AMAZON_SW_H |
| 3 | #define SET_ETH_SPEED_AUTO SIOCDEVPRIVATE |
| 4 | #define SET_ETH_SPEED_10 SIOCDEVPRIVATE+1 |
| 5 | #define SET_ETH_SPEED_100 SIOCDEVPRIVATE+2 |
| 6 | #define SET_ETH_DUPLEX_AUTO SIOCDEVPRIVATE+3 |
| 7 | #define SET_ETH_DUPLEX_HALF SIOCDEVPRIVATE+4 |
| 8 | #define SET_ETH_DUPLEX_FULL SIOCDEVPRIVATE+5 |
| 9 | #define SET_ETH_REG SIOCDEVPRIVATE+6 |
| 10 | #define VLAN_TOOLS SIOCDEVPRIVATE+7 |
| 11 | #define MAC_TABLE_TOOLS SIOCDEVPRIVATE+8 |
| 12 | |
| 13 | |
| 14 | /*===mac table commands==*/ |
| 15 | #define RESET_MAC_TABLE 0 |
| 16 | #define READ_MAC_ENTRY 1 |
| 17 | #define WRITE_MAC_ENTRY 2 |
| 18 | #define ADD_MAC_ENTRY 3 |
| 19 | |
| 20 | /*====vlan commands===*/ |
| 21 | |
| 22 | #define CHANGE_VLAN_CTRL 0 |
| 23 | #define READ_VLAN_ENTRY 1 |
| 24 | #define UPDATE_VLAN_ENTRY 2 |
| 25 | #define CLEAR_VLAN_ENTRY 3 |
| 26 | #define RESET_VLAN_TABLE 4 |
| 27 | #define ADD_VLAN_ENTRY 5 |
| 28 | |
| 29 | /* |
| 30 | ** MDIO constants. |
| 31 | */ |
| 32 | |
| 33 | #define MDIO_BASE_STATUS_REG 0x1 |
| 34 | #define MDIO_BASE_CONTROL_REG 0x0 |
| 35 | #define MDIO_PHY_ID_HIGH_REG 0x2 |
| 36 | #define MDIO_PHY_ID_LOW_REG 0x3 |
| 37 | #define MDIO_BC_NEGOTIATE 0x0200 |
| 38 | #define MDIO_BC_FULL_DUPLEX_MASK 0x0100 |
| 39 | #define MDIO_BC_AUTO_NEG_MASK 0x1000 |
| 40 | #define MDIO_BC_SPEED_SELECT_MASK 0x2000 |
| 41 | #define MDIO_STATUS_100_FD 0x4000 |
| 42 | #define MDIO_STATUS_100_HD 0x2000 |
| 43 | #define MDIO_STATUS_10_FD 0x1000 |
| 44 | #define MDIO_STATUS_10_HD 0x0800 |
| 45 | #define MDIO_STATUS_SPEED_DUPLEX_MASK 0x7800 |
| 46 | #define MDIO_ADVERTISMENT_REG 0x4 |
| 47 | #define MDIO_ADVERT_100_FD 0x100 |
| 48 | #define MDIO_ADVERT_100_HD 0x080 |
| 49 | #define MDIO_ADVERT_10_FD 0x040 |
| 50 | #define MDIO_ADVERT_10_HD 0x020 |
| 51 | #define MDIO_LINK_UP_MASK 0x4 |
| 52 | #define MDIO_START 0x1 |
| 53 | #define MDIO_READ 0x2 |
| 54 | #define MDIO_WRITE 0x1 |
| 55 | #define MDIO_PREAMBLE 0xfffffffful |
| 56 | |
| 57 | #define PHY_RESET 0x8000 |
| 58 | #define AUTO_NEGOTIATION_ENABLE 0X1000 |
| 59 | #define AUTO_NEGOTIATION_COMPLETE 0x20 |
| 60 | #define RESTART_AUTO_NEGOTIATION 0X200 |
| 61 | |
| 62 | |
| 63 | #define PHY0_ADDR 0 |
| 64 | #define PHY1_ADDR 1 |
| 65 | #define P1M 0 |
| 66 | |
| 67 | #define AMAZON_SW_REG32(reg_num) *((volatile u32*)(reg_num)) |
| 68 | |
| 69 | #define OK 0; |
| 70 | |
| 71 | #ifdef CONFIG_CPU_LITTLE_ENDIAN |
| 72 | typedef struct mac_table_entry{ |
| 73 | u64 mac_address:48; |
| 74 | u64 p0:1; |
| 75 | u64 p1:1; |
| 76 | u64 p2:1; |
| 77 | u64 cr:1; |
| 78 | u64 ma_st:3; |
| 79 | u64 res:9; |
| 80 | }_mac_table_entry; |
| 81 | |
| 82 | typedef struct IFX_Switch_VLanTableEntry{ |
| 83 | u32 vlan_id:12; |
| 84 | u32 mp0:1; |
| 85 | u32 mp1:1; |
| 86 | u32 mp2:1; |
| 87 | u32 v:1; |
| 88 | u32 res:16; |
| 89 | }_IFX_Switch_VLanTableEntry; |
| 90 | |
| 91 | typedef struct mac_table_req{ |
| 92 | int cmd; |
| 93 | int index; |
| 94 | u32 data; |
| 95 | u64 entry_value; |
| 96 | }_mac_table_req; |
| 97 | |
| 98 | #else //not CONFIG_CPU_LITTLE_ENDIAN |
| 99 | typedef struct mac_table_entry{ |
| 100 | u64 mac_address:48; |
| 101 | u64 p0:1; |
| 102 | u64 p1:1; |
| 103 | u64 p2:1; |
| 104 | u64 cr:1; |
| 105 | u64 ma_st:3; |
| 106 | u64 res:9; |
| 107 | }_mac_table_entry; |
| 108 | |
| 109 | typedef struct IFX_Switch_VLanTableEntry{ |
| 110 | u32 vlan_id:12; |
| 111 | u32 mp0:1; |
| 112 | u32 mp1:1; |
| 113 | u32 mp2:1; |
| 114 | u32 v:1; |
| 115 | u32 res:16; |
| 116 | }_IFX_Switch_VLanTableEntry; |
| 117 | |
| 118 | |
| 119 | typedef struct mac_table_req{ |
| 120 | int cmd; |
| 121 | int index; |
| 122 | u32 data; |
| 123 | u64 entry_value; |
| 124 | }_mac_table_req; |
| 125 | |
| 126 | #endif //CONFIG_CPU_LITTLE_ENDIAN |
| 127 | |
| 128 | |
| 129 | |
| 130 | typedef struct vlan_req{ |
| 131 | int cmd; |
| 132 | int index; |
| 133 | u32 data; |
| 134 | u32 entry_value; |
| 135 | }_vlan_req; |
| 136 | |
| 137 | typedef struct data_req{ |
| 138 | int index; |
| 139 | u32 value; |
| 140 | }_data_req; |
| 141 | |
| 142 | enum duplex |
| 143 | { |
| 144 | half, |
| 145 | full, |
| 146 | autoneg |
| 147 | }; |
| 148 | |
| 149 | struct switch_priv { |
| 150 | struct net_device_stats stats; |
| 151 | int rx_packetlen; |
| 152 | u8 *rx_packetdata; |
| 153 | int rx_status; |
| 154 | int tx_packetlen; |
| 155 | #ifdef CONFIG_NET_HW_FLOWCONTROL |
| 156 | int fc_bit; |
| 157 | #endif //CONFIG_NET_HW_FLOWCONTROL |
| 158 | u8 *tx_packetdata; |
| 159 | int tx_status; |
| 160 | struct dma_device_info *dma_device; |
| 161 | struct sk_buff *skb; |
| 162 | spinlock_t lock; |
| 163 | int mdio_phy_addr; |
| 164 | int current_speed; |
| 165 | int current_speed_selection; |
| 166 | int rx_queue_len; |
| 167 | int full_duplex; |
| 168 | enum duplex current_duplex; |
| 169 | int num; |
| 170 | }; |
| 171 | |
| 172 | #endif //AMAZON_SW_H |
| 173 | |
| 174 | |
| 175 | |
| 176 | |
| 177 | |
| 178 | |
