| 1 | #ifndef ATM_DEFINES_H |
| 2 | #define ATM_DEFINES_H |
| 3 | |
| 4 | //Registers Base Address |
| 5 | #define IO_BASE_ADDR 0xA0000000 |
| 6 | #define AAL5_BASE_ADDRESS 0x10104400+IO_BASE_ADDR |
| 7 | #define CBM_BASE_ADDRESS 0x10104000+IO_BASE_ADDR |
| 8 | #define HTU_BASE_ADDRESS 0x10105100+IO_BASE_ADDR |
| 9 | #define QSB_BASE_ADDRESS 0x10105000+IO_BASE_ADDR |
| 10 | #define SWIE_BASE_ADDRESS 0x10105200+IO_BASE_ADDR |
| 11 | |
| 12 | //AAL5 Registers |
| 13 | #define AAL5_SISR0_ADDR AAL5_BASE_ADDRESS+0x20 |
| 14 | #define AAL5_SIMR0_ADDR AAL5_BASE_ADDRESS+0x24 |
| 15 | #define AAL5_SISR1_ADDR AAL5_BASE_ADDRESS+0x28 |
| 16 | #define AAL5_SIMR1_ADDR AAL5_BASE_ADDRESS+0x2C |
| 17 | #define AAL5_SMFL_ADDR AAL5_BASE_ADDRESS+0x30 |
| 18 | #define AAL5_SATMHD_ADDR AAL5_BASE_ADDRESS+0x34 |
| 19 | #define AAL5_SCON_ADDR AAL5_BASE_ADDRESS+0x38 |
| 20 | #define AAL5_SCMD_ADDR AAL5_BASE_ADDRESS+0x3C |
| 21 | #define AAL5_RISR0_ADDR AAL5_BASE_ADDRESS+0x40 |
| 22 | #define AAL5_RIMR0_ADDR AAL5_BASE_ADDRESS+0x44 |
| 23 | #define AAL5_RISR1_ADDR AAL5_BASE_ADDRESS+0x48 |
| 24 | #define AAL5_RIMR1_ADDR AAL5_BASE_ADDRESS+0x4C |
| 25 | #define AAL5_RMFL_ADDR AAL5_BASE_ADDRESS+0x50 |
| 26 | #define AAL5_RINTINF0_ADDR AAL5_BASE_ADDRESS+0x54 |
| 27 | #define AAL5_RINTINF1_ADDR AAL5_BASE_ADDRESS+0x58 |
| 28 | #define AAL5_RES5C_ADDR AAL5_BASE_ADDRESS+0x5C |
| 29 | #define AAL5_RIOL_ADDR AAL5_BASE_ADDRESS+0x60 |
| 30 | #define AAL5_RIOM_ADDR AAL5_BASE_ADDRESS+0x64 |
| 31 | #define AAL5_SOOL_ADDR AAL5_BASE_ADDRESS+0x68 |
| 32 | #define AAL5_SOOM_ADDR AAL5_BASE_ADDRESS+0x6C |
| 33 | #define AAL5_RES70_ADDR AAL5_BASE_ADDRESS+0x70 |
| 34 | #define AAL5_RES74_ADDR AAL5_BASE_ADDRESS+0x74 |
| 35 | #define AAL5_RES78_ADDR AAL5_BASE_ADDRESS+0x78 |
| 36 | #define AAL5_RES7C_ADDR AAL5_BASE_ADDRESS+0x7C |
| 37 | #define AAL5_RES80_ADDR AAL5_BASE_ADDRESS+0x80 |
| 38 | #define AAL5_RES84_ADDR AAL5_BASE_ADDRESS+0x84 |
| 39 | #define AAL5_RES88_ADDR AAL5_BASE_ADDRESS+0x88 |
| 40 | #define AAL5_RES8C_ADDR AAL5_BASE_ADDRESS+0x8C |
| 41 | #define AAL5_RES90_ADDR AAL5_BASE_ADDRESS+0x90 |
| 42 | #define AAL5_RES94_ADDR AAL5_BASE_ADDRESS+0x94 |
| 43 | #define AAL5_RES98_ADDR AAL5_BASE_ADDRESS+0x98 |
| 44 | #define AAL5_RES9C_ADDR AAL5_BASE_ADDRESS+0x9C |
| 45 | #define AAL5_RESA0_ADDR AAL5_BASE_ADDRESS+0xA0 |
| 46 | #define AAL5_RESA4_ADDR AAL5_BASE_ADDRESS+0xA4 |
| 47 | #define AAL5_RESA8_ADDR AAL5_BASE_ADDRESS+0xA8 |
| 48 | #define AAL5_RESAC_ADDR AAL5_BASE_ADDRESS+0xAC |
| 49 | #define AAL5_RESB0_ADDR AAL5_BASE_ADDRESS+0xB0 |
| 50 | #define AAL5_RESB4_ADDR AAL5_BASE_ADDRESS+0xB4 |
| 51 | #define AAL5_RESB8_ADDR AAL5_BASE_ADDRESS+0xB8 |
| 52 | #define AAL5_RESBC_ADDR AAL5_BASE_ADDRESS+0xBC |
| 53 | #define AAL5_RESC0_ADDR AAL5_BASE_ADDRESS+0xC0 |
| 54 | #define AAL5_RESC4_ADDR AAL5_BASE_ADDRESS+0xC4 |
| 55 | #define AAL5_RESC8_ADDR AAL5_BASE_ADDRESS+0xC8 |
| 56 | #define AAL5_RESCC_ADDR AAL5_BASE_ADDRESS+0xCC |
| 57 | #define AAL5_RESD0_ADDR AAL5_BASE_ADDRESS+0xD0 |
| 58 | #define AAL5_RESD4_ADDR AAL5_BASE_ADDRESS+0xD4 |
| 59 | #define AAL5_RESD8_ADDR AAL5_BASE_ADDRESS+0xD8 |
| 60 | #define AAL5_RESDC_ADDR AAL5_BASE_ADDRESS+0xDC |
| 61 | #define AAL5_RESE0_ADDR AAL5_BASE_ADDRESS+0xE0 |
| 62 | #define AAL5_RESE4_ADDR AAL5_BASE_ADDRESS+0xE4 |
| 63 | #define AAL5_RESE8_ADDR AAL5_BASE_ADDRESS+0xE8 |
| 64 | #define AAL5_RESEC_ADDR AAL5_BASE_ADDRESS+0xEC |
| 65 | #define AAL5_SSRC0_ADDR AAL5_BASE_ADDRESS+0xF0 |
| 66 | #define AAL5_SSRC1_ADDR AAL5_BASE_ADDRESS+0xF4 |
| 67 | #define AAL5_RSRC0_ADDR AAL5_BASE_ADDRESS+0xF8 |
| 68 | #define AAL5_RSRC1_ADDR AAL5_BASE_ADDRESS+0xFC |
| 69 | |
| 70 | #define AAL5S_ISR_QID_MASK 0xFF000000 |
| 71 | #define AAL5S_ISR_SAB 0x00000100 |
| 72 | #define AAL5S_ISR_SE 0x00000080 |
| 73 | #define AAL5S_ISR_MFLE 0x00000040 |
| 74 | #define AAL5S_ISR_SBE0 0x00000020 |
| 75 | #define AAL5S_ISR_SEG0 0x00000010 |
| 76 | #define AAL5S_ISR_TAB 0x00000004 |
| 77 | |
| 78 | #define AAL5_SIMR_MASK 0x000001c7 |
| 79 | #define AAL5_SIMR_SAB 0x00000100 |
| 80 | #define AAL5_SIMR_SE 0x00000080 |
| 81 | #define AAL5_SIMR_MFLE 0x00000040 |
| 82 | #define AAL5_SIMR_TAB 0x00000004 |
| 83 | #define AAL5_SIMR_SBE0 0x00000002 |
| 84 | #define AAL5_SIMR_SEG0 0x00000001 |
| 85 | |
| 86 | #define AAL5_SCMD_SEQCOUNT_MASK 0x0000ff00 |
| 87 | #define AAL5_SCMD_MODE_POLL 0x00000008 |
| 88 | #define AAL5_SCMD_MODE_COUNT 0x00000000 |
| 89 | #define AAL5_SCMD_AS 0x00000004 |
| 90 | #define AAL5_SCMD_SS 0x00000002 |
| 91 | #define AAL5_SCMD_AR 0x00000001 |
| 92 | |
| 93 | #define AAL5R_ISR_CID_MASK 0xFF000000//ConnectionID |
| 94 | #define AAL5R_ISR_DBC_MASK 0x00FF0000//DiscardedByteCounter |
| 95 | #define AAL5R_ISR_END 0x00002000//End |
| 96 | #define AAL5R_ISR_ICID 0x00001000//InvalidConnectionID |
| 97 | #define AAL5R_ISR_CLP 0x00000800//CellLossPriority |
| 98 | #define AAL5R_ISR_CGST 0x00000400//Congestion |
| 99 | #define AAL5R_ISR_UUE 0x00000200//CPCSUUError |
| 100 | #define AAL5R_ISR_CPIE 0x00000100//CPIError |
| 101 | #define AAL5R_ISR_FE 0x00000080//FrameEnd |
| 102 | #define AAL5R_ISR_MFLE 0x00000040//MaximumFrameLengthExceeded |
| 103 | #define AAL5R_ISR_DBCE 0x00000020//DiscardedByteCounterExceeded |
| 104 | #define AAL5R_ISR_CRC 0x00000010//CRCError |
| 105 | #define AAL5R_ISR_ILEN 0x00000008//InvalidLength |
| 106 | #define AAL5R_ISR_RAB 0x00000004//ReceiveAbort |
| 107 | |
| 108 | #define AAL5_RIMR1_MASK 0x00003ffc |
| 109 | #define AAL5_RIMR1_END 0x00002000//End |
| 110 | #define AAL5_RIMR1_ICID 0x00001000//InvalidConnectionID |
| 111 | #define AAL5_RIMR1_CLP 0x00000800//CellLossPriority |
| 112 | #define AAL5_RIMR1_CGST 0x00000400//Congestion |
| 113 | #define AAL5_RIMR1_UUE 0x00000200//CPCSUUError |
| 114 | #define AAL5_RIMR1_CPIE 0x00000100//CPIError |
| 115 | #define AAL5_RIMR1_FE 0x00000080//FrameEnd |
| 116 | #define AAL5_RIMR1_MFLE 0x00000040//MaximumFrameLengthExceeded |
| 117 | #define AAL5_RIMR1_DBCE 0x00000020//DiscardedByteCounterExceeded |
| 118 | #define AAL5_RIMR1_CRC 0x00000010//CRCError |
| 119 | #define AAL5_RIMR1_ILEN 0x00000008//InvalidLength |
| 120 | #define AAL5_RIMR1_RAB 0x00000004//ReceiveAbort |
| 121 | |
| 122 | //AAL5 Reassambly Errors |
| 123 | #define AAL5_STW1_MASK 0x33//Error mask |
| 124 | #define AAL5_STW0_MASK 0x5c//Error mask |
| 125 | #define AAL5_STW0_BE 0x3//padding bytes mask |
| 126 | #define AAL5_STW1_CBM 0x20//Transfer from CBM to A5R abnormally ended |
| 127 | #define AAL5_STW1_CH 0x10//Invalid Channel number error |
| 128 | #define AAL5_STW1_CLP 0x8//CLP value of cells in packet is 1 |
| 129 | #define AAL5_STW1_CG 0x4//Cell in packet expired congestion |
| 130 | #define AAL5_STW1_UU 0x2//CPCS-UU value error |
| 131 | #define AAL5_STW1_CPI 0x1//CPI value error |
| 132 | #define AAL5_STW0_FE 0x80//Frame end |
| 133 | #define AAL5_STW0_MFL 0x40//Maximum frame length error |
| 134 | #define AAL5_STW0_CRC 0x10//CRC error |
| 135 | #define AAL5_STW0_IL 0x8//Invalid length |
| 136 | #define AAL5_STW0_RA 0x4//Received abort |
| 137 | |
| 138 | |
| 139 | |
| 140 | //CBM Registers |
| 141 | #define CBM_NRTTHR_ADDR CBM_BASE_ADDRESS+0x10//NonRealTimeThreshold |
| 142 | #define CBM_CLP0THR_ADDR CBM_BASE_ADDRESS+0x14//CLP0Threshold |
| 143 | #define CBM_CLP1THR_ADDR CBM_BASE_ADDRESS+0x18//CLP1Threshold |
| 144 | #define CBM_QDOFF_ADDR CBM_BASE_ADDRESS+0x1C//QueueDescriptorOffset |
| 145 | #define CBM_CFG_ADDR CBM_BASE_ADDRESS+0x20//Configuration |
| 146 | #define CBM_HWEXPAR0_ADDR CBM_BASE_ADDRESS+0x24//HWExtractParameter0 |
| 147 | #define CBM_RES28_ADDR CBM_BASE_ADDRESS+0x28 |
| 148 | #define CBM_WMSTAT0_ADDR CBM_BASE_ADDRESS+0x2C |
| 149 | #define CBM_HWEXCMD_ADDR CBM_BASE_ADDRESS+0x30//HWExtractCommand0 |
| 150 | #define CBM_RES34_ADDR CBM_BASE_ADDRESS+0x34 |
| 151 | #define CBM_HWEXSTAT0_ADDR CBM_BASE_ADDRESS+0x38//HWExtractStatus0 |
| 152 | #define CBM_RES3C_ADDR CBM_BASE_ADDRESS+0x3C |
| 153 | #define CBM_RES40_ADDR CBM_BASE_ADDRESS+0x40 |
| 154 | #define CBM_CNT_ADDR CBM_BASE_ADDRESS+0x44//CellCount |
| 155 | #define CBM_RES48_ADDR CBM_BASE_ADDRESS+0x48 |
| 156 | #define CBM_LFR_ADDR CBM_BASE_ADDRESS+0x4C//PointertolastCellinfreeCellQueue |
| 157 | #define CBM_FFR_ADDR CBM_BASE_ADDRESS+0x50//PointertofirstCellinfreeCellQueue |
| 158 | #define CBM_RES54_ADDR CBM_BASE_ADDRESS+0x54 |
| 159 | #define CBM_RES58_ADDR CBM_BASE_ADDRESS+0x58 |
| 160 | #define CBM_RES5C_ADDR CBM_BASE_ADDRESS+0x5C |
| 161 | #define CBM_RES60_ADDR CBM_BASE_ADDRESS+0x60 |
| 162 | #define CBM_RES64_ADDR CBM_BASE_ADDRESS+0x64 |
| 163 | #define CBM_RES68_ADDR CBM_BASE_ADDRESS+0x68 |
| 164 | #define CBM_RES6C_ADDR CBM_BASE_ADDRESS+0x6C |
| 165 | #define CBM_RES70_ADDR CBM_BASE_ADDRESS+0x70 |
| 166 | #define CBM_RES74_ADDR CBM_BASE_ADDRESS+0x74 |
| 167 | #define CBM_RES78_ADDR CBM_BASE_ADDRESS+0x78 |
| 168 | #define CBM_RES7C_ADDR CBM_BASE_ADDRESS+0x7C |
| 169 | #define CBM_RES80_ADDR CBM_BASE_ADDRESS+0x80 |
| 170 | #define CBM_RES84_ADDR CBM_BASE_ADDRESS+0x84 |
| 171 | #define CBM_RES88_ADDR CBM_BASE_ADDRESS+0x88 |
| 172 | #define CBM_RES8C_ADDR CBM_BASE_ADDRESS+0x8C |
| 173 | #define CBM_RES90_ADDR CBM_BASE_ADDRESS+0x90 |
| 174 | #define CBM_RES94_ADDR CBM_BASE_ADDRESS+0x94 |
| 175 | #define CBM_RES98_ADDR CBM_BASE_ADDRESS+0x98 |
| 176 | #define CBM_RES9C_ADDR CBM_BASE_ADDRESS+0x9C |
| 177 | #define CBM_RESA0_ADDR CBM_BASE_ADDRESS+0xA0 |
| 178 | #define CBM_RESA4_ADDR CBM_BASE_ADDRESS+0xA4 |
| 179 | #define CBM_RESA8_ADDR CBM_BASE_ADDRESS+0xA8 |
| 180 | #define CBM_RESAC_ADDR CBM_BASE_ADDRESS+0xAC |
| 181 | #define CBM_RESB0_ADDR CBM_BASE_ADDRESS+0xB0 |
| 182 | #define CBM_RESB4_ADDR CBM_BASE_ADDRESS+0xB4 |
| 183 | #define CBM_RESB8_ADDR CBM_BASE_ADDRESS+0xB8 |
| 184 | #define CBM_RESBC_ADDR CBM_BASE_ADDRESS+0xBC |
| 185 | #define CBM_INTINF0_ADDR CBM_BASE_ADDRESS+0xC0//InterruptInfo0 |
| 186 | #define CBM_INTCMD_ADDR CBM_BASE_ADDRESS+0xC4//InterruptCommand0 |
| 187 | #define CBM_IMR0_ADDR CBM_BASE_ADDRESS+0xC8//InterruptMask |
| 188 | #define CBM_SRC0_ADDR CBM_BASE_ADDRESS+0xCC//ServiceRequestControl |
| 189 | #define CBM_RESD0_ADDR CBM_BASE_ADDRESS+0xD0 |
| 190 | #define CBM_RESD4_ADDR CBM_BASE_ADDRESS+0xD4 |
| 191 | #define CBM_RESD8_ADDR CBM_BASE_ADDRESS+0xD8 |
| 192 | #define CBM_RESDC_ADDR CBM_BASE_ADDRESS+0xDC |
| 193 | #define CBM_RESE0_ADDR CBM_BASE_ADDRESS+0xE0 |
| 194 | #define CBM_AAL5IDIS_ADDR CBM_BASE_ADDRESS+0xE4//MIB-No.EPDdiscardedpacketsupstream |
| 195 | #define CBM_AAL5ODIS_ADDR CBM_BASE_ADDRESS+0xE8//MIB-No.PPDdiscardedpacketsupstream |
| 196 | #define CBM_RESEC_ADDR CBM_BASE_ADDRESS+0xEC |
| 197 | #define CBM_RESF0_ADDR CBM_BASE_ADDRESS+0xF0 |
| 198 | #define CBM_RESF4_ADDR CBM_BASE_ADDRESS+0xF4 |
| 199 | #define CBM_RESF8_ADDR CBM_BASE_ADDRESS+0xF8 |
| 200 | #define CBM_RESFC_ADDR CBM_BASE_ADDRESS+0xFC |
| 201 | |
| 202 | //CBMCFG |
| 203 | #define CBM_CFG_INTLCK0EN 0x00000008 |
| 204 | #define CBM_CFG_INT0HLT 0x00000004 |
| 205 | #define CBM_CFG_START 0x00000001 |
| 206 | |
| 207 | #define CBM_HWEXPAR_PN_A5 0x00002000 |
| 208 | #define CBM_HWEXPAR_PN_CM 0x00000000 |
| 209 | #define CBM_HWEXPAR_SUBADD_PORTMASK 0x00000070 |
| 210 | #define CBM_HWEXPAR_SUBADD_ADU 0x00000000 |
| 211 | #define CBM_HWEXPAR_SUBADD_AAL2 0x00000080 |
| 212 | #define CBM_HWEXPAR_SUBADD_SWIE 0x00000100 |
| 213 | |
| 214 | #define CBM_HWEXCMD_SFE2 0x00000100 |
| 215 | #define CBM_HWEXCMD_FE2 0x00000080 |
| 216 | #define CBM_HWEXCMD_SCE2 0x00000040 |
| 217 | #define CBM_HWEXCMD_SFE1 0x00000020 |
| 218 | #define CBM_HWEXCMD_FE1 0x00000010 |
| 219 | #define CBM_HWEXCMD_SCE1 0x00000008 |
| 220 | #define CBM_HWEXCMD_SFE0 0x00000004 |
| 221 | #define CBM_HWEXCMD_FE0 0x00000002 |
| 222 | #define CBM_HWEXCMD_SCE0 0x00000001 |
| 223 | |
| 224 | #define CBM_INTINF0_QID_MASK 0xFF000000 |
| 225 | #define CBM_INTINF0_ORIGIN_MASK 0x00F00000 |
| 226 | #define CBM_INTINF0_EF 0x00004000 |
| 227 | #define CBM_INTINF0_ACA 0x00002000 |
| 228 | #define CBM_INTINF0_ERR 0x00001000 |
| 229 | #define CBM_INTINF0_DISC 0x00000800 |
| 230 | #define CBM_INTINF0_QSBV 0x00000400 |
| 231 | #define CBM_INTINF0_Q0E 0x00000200 |
| 232 | #define CBM_INTINF0_Q0I 0x00000100 |
| 233 | #define CBM_INTINF0_RDE 0x00000080 |
| 234 | #define CBM_INTINF0_OPF 0x00000040 |
| 235 | #define CBM_INTINF0_NFCA 0x00000020 |
| 236 | #define CBM_INTINF0_CLP1TR 0x00000010 |
| 237 | #define CBM_INTINF0_CLP0TR 0x00000008 |
| 238 | #define CBM_INTINF0_NRTTR 0x00000004 |
| 239 | #define CBM_INTINF0_QFD 0x00000002 |
| 240 | #define CBM_INTINF0_QTR 0x00000001 |
| 241 | #define CBM_INTINF0_QID_SHIFT 24 |
| 242 | //CBM QD Word 3 |
| 243 | #define CBM_QD_W3_QOS_0 0x00000000 |
| 244 | #define CBM_QD_W3_QOS_1 0x40000000 |
| 245 | #define CBM_QD_W3_QOS_2 0x80000000 |
| 246 | #define CBM_QD_W3_QOS_3 0xc0000000 |
| 247 | |
| 248 | #define CBM_QD_W3_DIR_UP 0x20000000 |
| 249 | #define CBM_QD_W3_DIR_DOWN 0x00000000 |
| 250 | |
| 251 | #define CBM_QD_W3_CLPt 0x10000000 |
| 252 | #define CBM_QD_W3_RT 0x08000000 |
| 253 | #define CBM_QD_W3_AAL5 0x04000000 |
| 254 | |
| 255 | #define CBM_QD_W3_INT_NOINT 0x00000000 |
| 256 | #define CBM_QD_W3_INT_ACA 0x01000000 |
| 257 | #define CBM_QD_W3_INT_EOF 0x02000000 |
| 258 | #define CBM_QD_W3_INT_BOTH 0x03000000 |
| 259 | |
| 260 | #define CBM_QD_W3_THRESHOLD_MASK 0x00ff0000 |
| 261 | #define CBM_QD_W3_WM_EN 0x00000010 |
| 262 | #define CBM_QD_W3_HCR 0x00000008 |
| 263 | #define CBM_QD_W3_SBID_MASK 0x00000001 |
| 264 | |
| 265 | #define CBM_QD_W3_THRESHOLD_SHIFT 16 |
| 266 | |
| 267 | //WATER MARK STATUS |
| 268 | #define CBM_WM_NRT_MASK 0x00040000 |
| 269 | #define CBM_WM_CLP0_MASK 0x00020000 |
| 270 | #define CBM_WM_CLP1_MASK 0x00010000 |
| 271 | |
| 272 | //CBMNRTTHR, CBMCLP0THR, CBMCLP0THR |
| 273 | #define CBM_NRT_WM_NONE 0x00000000//no water mark |
| 274 | #define CBM_WM_3_1 0x00010000//3/4 to set, 1/4 to release |
| 275 | #define CBM_WM_3_2 0x00020000//3/4 to set, 2/4 to release |
| 276 | #define CBM_WM_2_1 0x00030000//2/4 to set, 1/4 to release |
| 277 | #define CBM_THR_MASK 0x0000FFFF |
| 278 | |
| 279 | #define CBM_IMR_MASK 0x0000fbff |
| 280 | #define CBM_IMR_reserved 0xFFFF0400 |
| 281 | #define CBM_IMR_RFULL 0x00008000//EndofFrame |
| 282 | #define CBM_IMR_EF 0x00004000//EndofFrame |
| 283 | #define CBM_IMR_ACA 0x00002000//AnyCellArrived |
| 284 | #define CBM_IMR_ERR 0x00001000//FPI Error |
| 285 | #define CBM_IMR_DISC 0x00000800//Discard |
| 286 | #define CBM_IMR_reserved1 0x00000400//reserved |
| 287 | #define CBM_IMR_Q0E 0x00000200//Queue0Extract |
| 288 | #define CBM_IMR_Q0I 0x00000100//Queue0Insert |
| 289 | #define CBM_IMR_RDE 0x00000080//ReadEmptyQueue |
| 290 | #define CBM_IMR_OPF 0x00000040//OncePerFrame |
| 291 | #define CBM_IMR_NFCA 0x00000020//NoFreeCellAvailable |
| 292 | #define CBM_IMR_CLP1TR 0x00000010//CLP1ThresholdReached |
| 293 | #define CBM_IMR_CLP0TR 0x00000008//CLP0ThresholdReached |
| 294 | #define CBM_IMR_NRTTR 0x00000004//NonRealTimeThresholdReached |
| 295 | #define CBM_IMR_QFD 0x00000002//QueueFrameDiscard |
| 296 | #define CBM_IMR_QTR 0x00000001//QueueThresholdReached |
| 297 | |
| 298 | #define CBM_EXSTAT_FB 0x00000010 |
| 299 | #define CBM_EXSTAT_SCB 0x00000008 |
| 300 | #define CBM_EXSTAT_Q0 0x00000004 |
| 301 | #define CBM_EXSTAT_RDE 0x00000002 |
| 302 | #define CBM_EXSTAT_QV 0x00000001 |
| 303 | |
| 304 | //HTU Registers |
| 305 | #define HTU_RX0_ADDR HTU_BASE_ADDRESS+0x10 |
| 306 | #define HTU_RX1_ADDR HTU_BASE_ADDRESS+0x14 |
| 307 | #define HTU_RES18_ADDR HTU_BASE_ADDRESS+0x18 |
| 308 | #define HTU_RES1C_ADDR HTU_BASE_ADDRESS+0x1C |
| 309 | #define HTU_RES20_ADDR HTU_BASE_ADDRESS+0x20 |
| 310 | #define HTU_RES24_ADDR HTU_BASE_ADDRESS+0x24 |
| 311 | #define HTU_RES28_ADDR HTU_BASE_ADDRESS+0x28 |
| 312 | #define HTU_RES2C_ADDR HTU_BASE_ADDRESS+0x2C |
| 313 | #define HTU_PCF0PAT_ADDR HTU_BASE_ADDRESS+0x30 |
| 314 | #define HTU_PCF1PAT_ADDR HTU_BASE_ADDRESS+0x34 |
| 315 | #define HTU_RES38_ADDR HTU_BASE_ADDRESS+0x38 |
| 316 | #define HTU_RES3C_ADDR HTU_BASE_ADDRESS+0x3C |
| 317 | #define HTU_RES40_ADDR HTU_BASE_ADDRESS+0x40 |
| 318 | #define HTU_RES44_ADDR HTU_BASE_ADDRESS+0x44 |
| 319 | #define HTU_RES48_ADDR HTU_BASE_ADDRESS+0x48 |
| 320 | #define HTU_RES4C_ADDR HTU_BASE_ADDRESS+0x4C |
| 321 | #define HTU_PCF0MASK_ADDR HTU_BASE_ADDRESS+0x50 |
| 322 | #define HTU_PCF1MASK_ADDR HTU_BASE_ADDRESS+0x54 |
| 323 | #define HTU_RES58_ADDR HTU_BASE_ADDRESS+0x58 |
| 324 | #define HTU_RES5C_ADDR HTU_BASE_ADDRESS+0x5C |
| 325 | #define HTU_RES60_ADDR HTU_BASE_ADDRESS+0x60 |
| 326 | #define HTU_RES64_ADDR HTU_BASE_ADDRESS+0x64 |
| 327 | #define HTU_RES68_ADDR HTU_BASE_ADDRESS+0x68 |
| 328 | #define HTU_RES6C_ADDR HTU_BASE_ADDRESS+0x6C |
| 329 | #define HTU_TIMEOUT_ADDR HTU_BASE_ADDRESS+0x70 |
| 330 | #define HTU_DESTOAM_ADDR HTU_BASE_ADDRESS+0x74 |
| 331 | #define HTU_DESTRM_ADDR HTU_BASE_ADDRESS+0x78 |
| 332 | #define HTU_DESTOTHER_ADDR HTU_BASE_ADDRESS+0x7C |
| 333 | #define HTU_CFG_ADDR HTU_BASE_ADDRESS+0x80 |
| 334 | #define HTU_RES84_ADDR HTU_BASE_ADDRESS+0x84 |
| 335 | #define HTU_RES88_ADDR HTU_BASE_ADDRESS+0x88 |
| 336 | #define HTU_RES8C_ADDR HTU_BASE_ADDRESS+0x8C |
| 337 | #define HTU_INFNOENTRY_ADDR HTU_BASE_ADDRESS+0x90 |
| 338 | #define HTU_INFTIMEOUT_ADDR HTU_BASE_ADDRESS+0x94 |
| 339 | #define HTU_RES98_STAT HTU_BASE_ADDRESS+0x98 |
| 340 | #define HTU_RES9C_ADDR HTU_BASE_ADDRESS+0x9C |
| 341 | #define HTU_MIBCIUP HTU_BASE_ADDRESS+0xA0//MIB Counter In Unknown Protoc Register |
| 342 | #define HTU_CNTTIMEOUT_ADDR HTU_BASE_ADDRESS+0xA4 |
| 343 | #define HTU_RESA8_ADDR HTU_BASE_ADDRESS+0xA8 |
| 344 | #define HTU_RESAC_ADDR HTU_BASE_ADDRESS+0xAC |
| 345 | #define HTU_RAMADDR_ADDR HTU_BASE_ADDRESS+0xB0 |
| 346 | #define HTU_RAMCMD_ADDR HTU_BASE_ADDRESS+0xB4 |
| 347 | #define HTU_RAMSTAT_ADDR HTU_BASE_ADDRESS+0xB8 |
| 348 | #define HTU_RESBC_ADDR HTU_BASE_ADDRESS+0xBC |
| 349 | #define HTU_RAMDAT1_ADDR HTU_BASE_ADDRESS+0xC0 |
| 350 | #define HTU_RAMDAT2_ADDR HTU_BASE_ADDRESS+0xC4 |
| 351 | #define HTU_RESCC_ADDR HTU_BASE_ADDRESS+0xCC |
| 352 | #define HTU_RESD0_ADDR HTU_BASE_ADDRESS+0xD0 |
| 353 | #define HTU_RESD4_ADDR HTU_BASE_ADDRESS+0xD4 |
| 354 | #define HTU_RESD8_ADDR HTU_BASE_ADDRESS+0xD8 |
| 355 | #define HTU_RESDC_ADDR HTU_BASE_ADDRESS+0xDC |
| 356 | #define HTU_RESE0_ADDR HTU_BASE_ADDRESS+0xE0 |
| 357 | #define HTU_RESE4_ADDR HTU_BASE_ADDRESS+0xE4 |
| 358 | #define HTU_IMR0_ADDR HTU_BASE_ADDRESS+0xE8 |
| 359 | #define HTU_RESEC_ADDR HTU_BASE_ADDRESS+0xEC |
| 360 | #define HTU_ISR0_ADDR HTU_BASE_ADDRESS+0xF0 |
| 361 | #define HTU_RESF4_ADDR HTU_BASE_ADDRESS+0xF4 |
| 362 | #define HTU_SRC0_ADDR HTU_BASE_ADDRESS+0xF8 |
| 363 | #define HTU_RESFC_ADDR HTU_BASE_ADDRESS+0xFC |
| 364 | |
| 365 | //HTU_CFG |
| 366 | #define HTU_CFG_START 0x00000001 |
| 367 | |
| 368 | #define HTU_RAMCMD_RMW 0x00000004 |
| 369 | #define HTU_RAMCMD_RD 0x00000002 |
| 370 | #define HTU_RAMCMD_WR 0x00000001 |
| 371 | |
| 372 | #define HTU_RAMDAT1_VCON 0x00000080//validconnection |
| 373 | #define HTU_RAMDAT1_VCT 0x00000040//vcivalueistransparent |
| 374 | #define HTU_RAMDAT1_QIDS 0x00000020//qid selects a cell in cbm |
| 375 | #define HTU_RAMDAT1_VCI3 0x00000010//vci3->oamqueue |
| 376 | #define HTU_RAMDAT1_VCI4 0x00000008//vci4->oamqueue |
| 377 | #define HTU_RAMDAT1_VCI6 0x00000004//vci6->rmqueue |
| 378 | #define HTU_RAMDAT1_PTI4 0x00000002//pti4->oamqueue |
| 379 | #define HTU_RAMDAT1_PTI5 0x00000001//pti5->oamqueue |
| 380 | |
| 381 | #define HTU_RAMDAT2_PTI6 0x00000800 |
| 382 | #define HTU_RAMDAT2_PTI7 0x00000400 |
| 383 | #define HTU_RAMDAT2_F4U 0x00000200 |
| 384 | #define HTU_RAMDAT2_F5U 0x00000100 |
| 385 | #define HTU_RAMDAT2_QID_MASK 0x000000ff |
| 386 | |
| 387 | #define HTU_ISR_NE 0x00000001 |
| 388 | #define HTU_ISR_TORD 0x00000002 |
| 389 | #define HTU_ISR_IT 0x00000008 |
| 390 | #define HTU_ISR_OTOC 0x00000010 |
| 391 | #define HTU_ISR_ONEC 0x00000020 |
| 392 | #define HTU_ISR_PNE 0x00000040 |
| 393 | #define HTU_ISR_PT 0x00000080 |
| 394 | #define HTU_ISR_MASK 0x000000ff |
| 395 | |
| 396 | |
| 397 | //QSB Registers |
| 398 | #define QSB_BIP0_ADDR QSB_BASE_ADDRESS+0x00 |
| 399 | #define QSB_BIP1_ADDR QSB_BASE_ADDRESS+0x04 |
| 400 | #define QSB_BIP2_ADDR QSB_BASE_ADDRESS+0x08 |
| 401 | #define QSB_BIP3_ADDR QSB_BASE_ADDRESS+0x0C |
| 402 | #define QSB_RSVP_ADDR QSB_BASE_ADDRESS+0x10 |
| 403 | #define QSB_TNOW_ADDR QSB_BASE_ADDRESS+0x14 |
| 404 | #define QSB_TNOWCYC_ADDR QSB_BASE_ADDRESS+0x18 |
| 405 | #define QSB_TAU_ADDR QSB_BASE_ADDRESS+0x1C |
| 406 | #define QSB_L1BRS_ADDR QSB_BASE_ADDRESS+0x20 |
| 407 | #define QSB_SBL_ADDR QSB_BASE_ADDRESS+0x24 |
| 408 | #define QSB_CONFIG_ADDR QSB_BASE_ADDRESS+0x28 |
| 409 | #define QSB_RTM_ADDR QSB_BASE_ADDRESS+0x2C |
| 410 | #define QSB_RTD_ADDR QSB_BASE_ADDRESS+0x30 |
| 411 | #define QSB_RAMAC_ADDR QSB_BASE_ADDRESS+0x34 |
| 412 | #define QSB_ISR_ADDR QSB_BASE_ADDRESS+0x38 |
| 413 | #define QSB_IMR_ADDR QSB_BASE_ADDRESS+0x3C |
| 414 | #define QSB_SRC_ADDR QSB_BASE_ADDRESS+0x40 |
| 415 | |
| 416 | #define QSB_TABLESEL_QVPT 8 |
| 417 | #define QSB_TABLESEL_QPT 1 |
| 418 | #define QSB_TABLESEL_SCT 2 |
| 419 | #define QSB_TABLESEL_SPT 3 |
| 420 | #define QSB_TABLESEL_CALENDARWFQ 4/*notusedbyFW*/ |
| 421 | #define QSB_TABLESEL_L2WFQ 5/*notusedbyFW*/ |
| 422 | #define QSB_TABLESEL_CALENDARRS 6/*notusedbyFW*/ |
| 423 | #define QSB_TABLESEL_L2BITMAPRS 7/*notusedbyFW*/ |
| 424 | #define QSB_TABLESEL_SHIFT 24 |
| 425 | #define QSB_TWFQ_MASK 0x3FFF0000 |
| 426 | #define QSB_TPRS_MASK 0x0000FFFF |
| 427 | #define QSB_SBID_MASK 0xF |
| 428 | #define QSB_TWFQ_SHIFT 16 |
| 429 | #define QSB_SCDRATE_MASK 0x00007FFF |
| 430 | #define QSB_SBVALID_MASK 0x80000000 |
| 431 | |
| 432 | #define QSB_ISR_WFQLE 0x00000001 |
| 433 | #define QSB_ISR_WFQBE 0x00000002 |
| 434 | #define QSB_ISR_RSLE 0x00000004 |
| 435 | #define QSB_ISR_RSBE 0x00000008 |
| 436 | #define QSB_ISR_MUXOV 0x00000010 |
| 437 | #define QSB_ISR_CDVOV 0x00000020 |
| 438 | #define QSB_ISR_PARAMI 0x00000040 |
| 439 | #define QSB_ISR_SLOSS 0x00000080 |
| 440 | #define QSB_ISR_IIPS 0x00000100 |
| 441 | |
| 442 | #define QSB_IMR_WFQLE 0x00000001 |
| 443 | #define QSB_IMR_WFQBE 0x00000002 |
| 444 | #define QSB_IMR_RSLE 0x00000004 |
| 445 | #define QSB_IMR_RSBE 0x00000008 |
| 446 | #define QSB_IMR_MUXOV 0x00000010 |
| 447 | #define QSB_IMR_CDVOV 0x00000020 |
| 448 | #define QSB_IMR_PARAMI 0x00000040 |
| 449 | #define QSB_IMR_SLOSS 0x00000080 |
| 450 | #define QSB_IMR_IIPS 0x00000100 |
| 451 | |
| 452 | #define QSB_READ 0x0 |
| 453 | #define QSB_WRITE 0x80000000 |
| 454 | #define QSB_READ_ALL 0xFFFFFFFF |
| 455 | |
| 456 | #if 1 //some bug with QSB access mask |
| 457 | #define QSB_QPT_SET_MASK 0x0 |
| 458 | #define QSB_QVPT_SET_MASK 0x0 |
| 459 | #define QSB_SET_SCT_MASK 0x0 |
| 460 | #define QSB_SET_SPT_MASK 0x0 |
| 461 | #define QSB_SET_SPT_SBVALID_MASK 0x7FFFFFFF |
| 462 | #else //some bug with QSB access mask |
| 463 | #define QSB_QPT_SET_MASK 0x80000000 |
| 464 | #define QSB_QVPT_SET_MASK 0x0 |
| 465 | #define QSB_SET_SCT_MASK 0xFFFFFFE0 |
| 466 | #define QSB_SET_SPT_MASK 0x7FF8C000 |
| 467 | #define QSB_SET_SPT_SBVALID_MASK 0x7FFFFFFF |
| 468 | #endif //some bug with QSB access mask |
| 469 | |
| 470 | #define QSB_SPT_SBVALID 0x80000000 |
| 471 | |
| 472 | #define QSB_RAMAC_REG_LOW 0x0 |
| 473 | #define QSB_RAMAC_REG_HIGH 0x00010000 |
| 474 | |
| 475 | #define SRC_SRE_ENABLE 0x1000 |
| 476 | #define SRC_CLRR 0x4000 //request clear bit |
| 477 | |
| 478 | |
| 479 | |
| 480 | //SWIE Registers |
| 481 | #define SWIE_IQID_ADDR SWIE_BASE_ADDRESS+0x0c//SWIEInsertQueueDescriptor |
| 482 | #define SWIE_ICMD_ADDR SWIE_BASE_ADDRESS+0x10//SWIEInsertCommand |
| 483 | #define SWIE_ISTAT_ADDR SWIE_BASE_ADDRESS+0x14//SWIEInsertStatus |
| 484 | #define SWIE_ESTAT_ADDR SWIE_BASE_ADDRESS+0x18//SWIEExtractStatus |
| 485 | #define SWIE_ISRC_ADDR SWIE_BASE_ADDRESS+0x74//SWIEInsertServiceRequestControl |
| 486 | #define SWIE_ESRC_ADDR SWIE_BASE_ADDRESS+0x78//SWIEExtractServiceRequestControl |
| 487 | #define SWIE_ICELL_ADDR SWIE_BASE_ADDRESS+0x80//SWIEInsertCell(0x80-0xb4) |
| 488 | #define SWIE_ECELL_ADDR SWIE_BASE_ADDRESS+0xc0//SWIEExtractCell(0xc0-0xf4) |
| 489 | |
| 490 | #define SWIE_ISTAT_DONE 0x1 |
| 491 | #define SWIE_ESTAT_DONE 0x1 |
| 492 | #define SWIE_ICMD_START 0x00000001//Startcommandforinsertion |
| 493 | #define SWIE_CBM_SCE0 CBM_HWEXCMD_SCE0//CBMcommandforSingle-Cell-Extract |
| 494 | #define SWIE_CBM_PID_SUBADDR 0x00001000//CBMPortIDandSubAddressforUTOPIA |
| 495 | |
| 496 | //Extracted cell format |
| 497 | //52bytes AAL0 PDU + "Input cell additional data"(14bits) |
| 498 | #define SWIE_ADDITION_DATA_MASK 0x7fff |
| 499 | #define SWIE_EPORT_MASK 0x7000//Source ID (000 AUB0, 001 AUB1) |
| 500 | #define SWIE_EF4USER_MASK 0x800 |
| 501 | #define SWIE_EF5USER_MASK 0x400 |
| 502 | #define SWIE_EOAM_MASK 0x200 |
| 503 | #define SWIE_EAUU_MASK 0x100 |
| 504 | #define SWIE_EVCI3_MASK 0x80 |
| 505 | #define SWIE_EVCI4_MASK 0x40 |
| 506 | #define SWIE_EVCI6_MASK 0x20 |
| 507 | #define SWIE_EPTI4_MASK 0x10 |
| 508 | #define SWIE_EPTI5_MASK 0x8 |
| 509 | #define SWIE_EPTI6_MASK 0x4 |
| 510 | #define SWIE_EPTI7_MASK 0x2 |
| 511 | #define SWIE_ECRC10ERROR_MASK 0x1 |
| 512 | |
| 513 | #define CBM_CELL_SIZE 0x40 |
| 514 | #define CBM_QD_SIZE 0x10 |
| 515 | #define AAL5R_TRAILER_LEN 12 |
| 516 | #define AAL5S_INBOUND_HEADER 8 |
| 517 | |
| 518 | //constants |
| 519 | //TODO: to be finalized by system guys |
| 520 | //DMA QOS defined by ATM QoS Service type |
| 521 | #define DMA_RX_CH0 0 |
| 522 | #define DMA_RX_CH1 1 |
| 523 | #define DMA_TX_CH0 0 |
| 524 | #define DMA_TX_CH1 1 |
| 525 | #define CBR_DMA_QOS CBM_QD_W3_QOS_0 |
| 526 | #define VBR_RT_DMA_QOS CBM_QD_W3_QOS_0 |
| 527 | #define VBR_NRT_DMA_QOS CBM_QD_W3_QOS_0 |
| 528 | #define UBR_PLUS_DMA_QOS CBM_QD_W3_QOS_0 |
| 529 | #define UBR_DMA_QOS CBM_QD_W3_QOS_0 |
| 530 | |
| 531 | #define SRC_TOS_MIPS 0 |
| 532 | #define AAL5R_SRPN 0x00000006//a5rneedshigherprioritythanDR |
| 533 | #define AAL5S_SRPN 0x00000005 |
| 534 | #define CBM_MIPS_SRPN 0x00000004 |
| 535 | #define QSB_SRPN 0x00000023 |
| 536 | #define HTU_SRPN1 0x00000022 |
| 537 | #define HTU_SRPN0 0x00000021 |
| 538 | |
| 539 | #endif //ATM_DEFINES_H |
| 540 | |
| 541 | |
