| 1 | #ifndef IFX_SSC_DEFINES_H |
| 2 | #define IFX_SSC_DEFINES_H |
| 3 | |
| 4 | #include "ifx_peripheral_definitions.h" |
| 5 | |
| 6 | /* maximum SSC FIFO size */ |
| 7 | #define IFX_SSC_MAX_FIFO_SIZE 32 |
| 8 | |
| 9 | /* register map of SSC */ |
| 10 | |
| 11 | /* address of the Clock Control Register of the SSC */ |
| 12 | #define IFX_SSC_CLC 0x00000000 |
| 13 | /* IFX_SSC_CLC register is significant in bits 23 downto 8 and in bits 5, 3, 2, 0 |
| 14 | bit 1 is hardware modified*/ |
| 15 | #define IFX_SSC_CLC_readmask 0x00FFFFEF |
| 16 | #define IFX_SSC_CLC_writemask 0x00FFFF3D |
| 17 | #define IFX_SSC_CLC_hwmask 0x00000002 |
| 18 | #define IFX_SSC_CLC_dontcare (IFX_SSC_CLC_readmask & IFX_SSC_CLC_writemask & ~IFX_SSC_CLC_hwmask) |
| 19 | |
| 20 | /* address of Port Input Select Register of the SSC */ |
| 21 | #define IFX_SSC_PISEL 0x00000004 |
| 22 | /* IFX_SSC_PISEL register is significant in lowest three bits only */ |
| 23 | #define IFX_SSC_PISEL_readmask 0x00000007 |
| 24 | #define IFX_SSC_PISEL_writemask 0x00000007 |
| 25 | #define IFX_SSC_PISEL_hwmask 0x00000000 |
| 26 | #define IFX_SSC_PISEL_dontcare (IFX_SSC_PISEL_readmask & IFX_SSC_PISEL_writemask & ~IFX_SSC_PISEL_hwmask) |
| 27 | |
| 28 | /* address of Identification Register of the SSC */ |
| 29 | #define IFX_SSC_ID 0x00000008 |
| 30 | /* IFX_SSC_ID register is significant in no bit */ |
| 31 | #define IFX_SSC_ID_readmask 0x0000FF3F |
| 32 | #define IFX_SSC_ID_writemask 0x00000000 |
| 33 | #define IFX_SSC_ID_hwmask 0x00000000 |
| 34 | #define IFX_SSC_ID_dontcare (IFX_SSC_ID_readmask & IFX_SSC_ID_writemask & ~IFX_SSC_ID_hwmask) |
| 35 | |
| 36 | /* address of the Control Register of the SSC */ |
| 37 | #define IFX_SSC_CON 0x00000010 |
| 38 | /* IFX_SSC_CON register is significant in bits 23:22, 20:16 and 12:0 */ |
| 39 | #define IFX_SSC_CON_readmask 0x01DF1FFF |
| 40 | #define IFX_SSC_CON_writemask 0x01DF1FFF |
| 41 | #define IFX_SSC_CON_hwmask 0x00000000 |
| 42 | #define IFX_SSC_CON_dontcare (IFX_SSC_CON_readmask & IFX_SSC_CON_writemask & ~IFX_SSC_CON_hwmask) |
| 43 | |
| 44 | |
| 45 | /* address of the Status Register of the SSC */ |
| 46 | #define IFX_SSC_STATE 0x00000014 |
| 47 | /* IFX_SSC_STATE register is readable in bits 30:28, 26:24, 20:16, 12:7 and 2:0 |
| 48 | all bits except 1:0 are hardware modified */ |
| 49 | #define IFX_SSC_STATE_readmask 0x771F3F87 |
| 50 | #define IFX_SSC_STATE_writemask 0x00000000 |
| 51 | #define IFX_SSC_STATE_hwmask 0x771F3F84 |
| 52 | #define IFX_SSC_STATE_dontcare (IFX_SSC_STATE_readmask & IFX_SSC_STATE_writemask & ~IFX_SSC_STATE_hwmask) |
| 53 | |
| 54 | /* address of the Write Hardware Modified Control Register Bits of the SSC */ |
| 55 | #define IFX_SSC_WHBSTATE 0x00000018 |
| 56 | /* IFX_SSC_WHBSTATE register is write only */ |
| 57 | #define IFX_SSC_WHBSTATE_readmask 0x00000000 |
| 58 | #define IFX_SSC_WHBSTATE_writemask 0x0000FFFF |
| 59 | #define IFX_SSC_WHBSTATE_hwmask 0x00000000 |
| 60 | #define IFX_SSC_WHBSTATE_dontcare (IFX_SSC_WHBSTATE_readmask & IFX_SSC_WHBSTATE_writemask & ~IFX_SSC_WHBSTATE_hwmask) |
| 61 | |
| 62 | /* address of the Baudrate Timer Reload Register of the SSC */ |
| 63 | #define IFX_SSC_BR 0x00000040 |
| 64 | /* IFX_SSC_BR register is significant in bit 15 downto 0*/ |
| 65 | #define IFX_SSC_BR_readmask 0x0000FFFF |
| 66 | #define IFX_SSC_BR_writemask 0x0000FFFF |
| 67 | #define IFX_SSC_BR_hwmask 0x00000000 |
| 68 | #define IFX_SSC_BR_dontcare (IFX_SSC_BR_readmask & IFX_SSC_BR_writemask & ~IFX_SSC_BR_hwmask) |
| 69 | |
| 70 | /* address of the Baudrate Timer Status Register of the SSC */ |
| 71 | #define IFX_SSC_BRSTAT 0x00000044 |
| 72 | /* IFX_SSC_BRSTAT register is significant in bit 15 downto 0*/ |
| 73 | #define IFX_SSC_BRSTAT_readmask 0x0000FFFF |
| 74 | #define IFX_SSC_BRSTAT_writemask 0x00000000 |
| 75 | #define IFX_SSC_BRSTAT_hwmask 0x0000FFFF |
| 76 | #define IFX_SSC_BRSTAT_dontcare (IFX_SSC_BRSTAT_readmask & IFX_SSC_BRSTAT_writemask & ~IFX_SSC_BRSTAT_hwmask) |
| 77 | |
| 78 | /* address of the Transmitter Buffer Register of the SSC */ |
| 79 | #define IFX_SSC_TB 0x00000020 |
| 80 | /* IFX_SSC_TB register is significant in bit 31 downto 0*/ |
| 81 | #define IFX_SSC_TB_readmask 0xFFFFFFFF |
| 82 | #define IFX_SSC_TB_writemask 0xFFFFFFFF |
| 83 | #define IFX_SSC_TB_hwmask 0x00000000 |
| 84 | #define IFX_SSC_TB_dontcare (IFX_SSC_TB_readmask & IFX_SSC_TB_writemask & ~IFX_SSC_TB_hwmask) |
| 85 | |
| 86 | /* address of the Reciver Buffer Register of the SSC */ |
| 87 | #define IFX_SSC_RB 0x00000024 |
| 88 | /* IFX_SSC_RB register is significant in no bits*/ |
| 89 | #define IFX_SSC_RB_readmask 0xFFFFFFFF |
| 90 | #define IFX_SSC_RB_writemask 0x00000000 |
| 91 | #define IFX_SSC_RB_hwmask 0xFFFFFFFF |
| 92 | #define IFX_SSC_RB_dontcare (IFX_SSC_RB_readmask & IFX_SSC_RB_writemask & ~IFX_SSC_RB_hwmask) |
| 93 | |
| 94 | /* address of the Receive FIFO Control Register of the SSC */ |
| 95 | #define IFX_SSC_RXFCON 0x00000030 |
| 96 | /* IFX_SSC_RXFCON register is significant in bit 13 downto 8 and bit 1 downto 0 */ |
| 97 | #define IFX_SSC_RXFCON_readmask 0x00003F03 |
| 98 | #define IFX_SSC_RXFCON_writemask 0x00003F03 |
| 99 | #define IFX_SSC_RXFCON_hwmask 0x00000000 |
| 100 | #define IFX_SSC_RXFCON_dontcare (IFX_SSC_RXFCON_readmask & IFX_SSC_RXFCON_writemask & ~IFX_SSC_RXFCON_hwmask) |
| 101 | |
| 102 | /* address of the Transmit FIFO Control Register of the SSC */ |
| 103 | #define IFX_SSC_TXFCON 0x00000034 |
| 104 | /* IFX_SSC_TXFCON register is significant in bit 13 downto 8 and bit 1 downto 0 */ |
| 105 | #define IFX_SSC_TXFCON_readmask 0x00003F03 |
| 106 | #define IFX_SSC_TXFCON_writemask 0x00003F03 |
| 107 | #define IFX_SSC_TXFCON_hwmask 0x00000000 |
| 108 | #define IFX_SSC_TXFCON_dontcare (IFX_SSC_TXFCON_readmask & IFX_SSC_TXFCON_writemask & ~IFX_SSC_TXFCON_hwmask) |
| 109 | |
| 110 | /* address of the FIFO Status Register of the SSC */ |
| 111 | #define IFX_SSC_FSTAT 0x00000038 |
| 112 | /* IFX_SSC_FSTAT register is significant in no bit*/ |
| 113 | #define IFX_SSC_FSTAT_readmask 0x00003F3F |
| 114 | #define IFX_SSC_FSTAT_writemask 0x00000000 |
| 115 | #define IFX_SSC_FSTAT_hwmask 0x00003F3F |
| 116 | #define IFX_SSC_FSTAT_dontcare (IFX_SSC_FSTAT_readmask & IFX_SSC_FSTAT_writemask & ~IFX_SSC_FSTAT_hwmask) |
| 117 | |
| 118 | /* address of the Data Frame Control register of the SSC */ |
| 119 | #define IFX_SSC_SFCON 0x00000060 |
| 120 | #define IFX_SSC_SFCON_readmask 0xFFDFFFFD |
| 121 | #define IFX_SSC_SFCON_writemask 0xFFDFFFFD |
| 122 | #define IFX_SSC_SFCON_hwmask 0x00000000 |
| 123 | #define IFX_SSC_SFCON_dontcare (IFX_SSC_SFCON_readmask & IFX_SSC_SFCON_writemask & ~IFX_SSC_SFCON_hwmask) |
| 124 | |
| 125 | /* address of the Data Frame Status register of the SSC */ |
| 126 | #define IFX_SSC_SFSTAT 0x00000064 |
| 127 | #define IFX_SSC_SFSTAT_readmask 0xFFC0FFF3 |
| 128 | #define IFX_SSC_SFSTAT_writemask 0x00000000 |
| 129 | #define IFX_SSC_SFSTAT_hwmask 0xFFC0FFF3 |
| 130 | #define IFX_SSC_SFSTAT_dontcare (IFX_SSC_SFSTAT_readmask & IFX_SSC_SFSTAT_writemask & ~IFX_SSC_SFSTAT_hwmask) |
| 131 | |
| 132 | /* address of the General Purpose Output Control register of the SSC */ |
| 133 | #define IFX_SSC_GPOCON 0x00000070 |
| 134 | #define IFX_SSC_GPOCON_readmask 0x0000FFFF |
| 135 | #define IFX_SSC_GPOCON_writemask 0x0000FFFF |
| 136 | #define IFX_SSC_GPOCON_hwmask 0x00000000 |
| 137 | #define IFX_SSC_GPOCON_dontcare (IFX_SSC_GPOCON_readmask & IFX_SSC_GPOCON_writemask & ~IFX_SSC_GPOCON_hwmask) |
| 138 | |
| 139 | /* address of the General Purpose Output Status register of the SSC */ |
| 140 | #define IFX_SSC_GPOSTAT 0x00000074 |
| 141 | #define IFX_SSC_GPOSTAT_readmask 0x000000FF |
| 142 | #define IFX_SSC_GPOSTAT_writemask 0x00000000 |
| 143 | #define IFX_SSC_GPOSTAT_hwmask 0x00000000 |
| 144 | #define IFX_SSC_GPOSTAT_dontcare (IFX_SSC_GPOSTAT_readmask & IFX_SSC_GPOSTAT_writemask & ~IFX_SSC_GPOSTAT_hwmask) |
| 145 | |
| 146 | /* address of the Force GPO Status register of the SSC */ |
| 147 | #define IFX_SSC_WHBGPOSTAT 0x00000078 |
| 148 | #define IFX_SSC_WHBGPOSTAT_readmask 0x00000000 |
| 149 | #define IFX_SSC_WHBGPOSTAT_writemask 0x0000FFFF |
| 150 | #define IFX_SSC_WHBGPOSTAT_hwmask 0x00000000 |
| 151 | #define IFX_SSC_WHBGPOSTAT_dontcare (IFX_SSC_WHBGPOSTAT_readmask & IFX_SSC_WHBGPOSTAT_writemask & ~IFX_SSC_WHBGPOSTAT_hwmask) |
| 152 | |
| 153 | /* address of the Receive Request Register of the SSC */ |
| 154 | #define IFX_SSC_RXREQ 0x00000080 |
| 155 | #define IFX_SSC_RXREQ_readmask 0x0000FFFF |
| 156 | #define IFX_SSC_RXREQ_writemask 0x0000FFFF |
| 157 | #define IFX_SSC_RXREQ_hwmask 0x00000000 |
| 158 | #define IFX_SSC_RXREQ_dontcare (IFX_SSC_RXREQ_readmask & IFX_SSC_RXREQ_writemask & ~IFX_SSC_RXREQ_hwmask) |
| 159 | |
| 160 | /* address of the Receive Count Register of the SSC */ |
| 161 | #define IFX_SSC_RXCNT 0x00000084 |
| 162 | #define IFX_SSC_RXCNT_readmask 0x0000FFFF |
| 163 | #define IFX_SSC_RXCNT_writemask 0x00000000 |
| 164 | #define IFX_SSC_RXCNT_hwmask 0x0000FFFF |
| 165 | #define IFX_SSC_RXCNT_dontcare (IFX_SSC_RXCNT_readmask & IFX_SSC_RXCNT_writemask & ~IFX_SSC_RXCNT_hwmask) |
| 166 | |
| 167 | /* address of the DMA Configuration Register of the SSC */ |
| 168 | #define IFX_SSC_DMACON 0x000000EC |
| 169 | #define IFX_SSC_DMACON_readmask 0x0000FFFF |
| 170 | #define IFX_SSC_DMACON_writemask 0x00000000 |
| 171 | #define IFX_SSC_DMACON_hwmask 0x0000FFFF |
| 172 | #define IFX_SSC_DMACON_dontcare (IFX_SSC_DMACON_readmask & IFX_SSC_DMACON_writemask & ~IFX_SSC_DMACON_hwmask) |
| 173 | |
| 174 | //------------------------------------------------------ |
| 175 | // interrupt register for enabling interrupts, mask register of irq_reg |
| 176 | #define IFX_SSC_IRN_EN 0xF4 |
| 177 | // read/write |
| 178 | #define IFX_SSC_IRN_EN_readmask 0x0000000F |
| 179 | #define IFX_SSC_IRN_EN_writemask 0x0000000F |
| 180 | #define IFX_SSC_IRN_EN_hwmask 0x00000000 |
| 181 | #define IFX_SSC_IRN_EN_dontcare (IFX_SSC_IRN_EN_readmask & IFX_SSC_IRN_EN_writemask & ~IFX_SSC_IRN_EN_hwmask) |
| 182 | |
| 183 | // interrupt register for accessing interrupts |
| 184 | #define IFX_SSC_IRN_CR 0xF8 |
| 185 | // read/write |
| 186 | #define IFX_SSC_IRN_CR_readmask 0x0000000F |
| 187 | #define IFX_SSC_IRN_CR_writemask 0x0000000F |
| 188 | #define IFX_SSC_IRN_CR_hwmask 0x0000000F |
| 189 | #define IFX_SSC_IRN_CR_dontcare (IFX_SSC_IRN_CR_readmask & IFX_SSC_IRN_CR_writemask & ~IFX_SSC_IRN_CR_hwmask) |
| 190 | |
| 191 | // interrupt register for stimulating interrupts |
| 192 | #define IFX_SSC_IRN_ICR 0xFC |
| 193 | // read/write |
| 194 | #define IFX_SSC_IRN_ICR_readmask 0x0000000F |
| 195 | #define IFX_SSC_IRN_ICR_writemask 0x0000000F |
| 196 | #define IFX_SSC_IRN_ICR_hwmask 0x00000000 |
| 197 | #define IFX_SSC_IRN_ICR_dontcare (IFX_SSC_IRN_ICR_readmask & IFX_SSC_IRN_ICR_writemask & ~IFX_SSC_IRN_ICR_hwmask) |
| 198 | |
| 199 | //--------------------------------------------------------------------- |
| 200 | // Number of IRQs and bitposition of IRQ |
| 201 | #define IFX_SSC_NUM_IRQ 4 |
| 202 | #define IFX_SSC_T_BIT 0x00000001 |
| 203 | #define IFX_SSC_R_BIT 0x00000002 |
| 204 | #define IFX_SSC_E_BIT 0x00000004 |
| 205 | #define IFX_SSC_F_BIT 0x00000008 |
| 206 | |
| 207 | /* bit masks for SSC registers */ |
| 208 | |
| 209 | /* ID register */ |
| 210 | #define IFX_SSC_PERID_REV_MASK 0x0000001F |
| 211 | #define IFX_SSC_PERID_CFG_MASK 0x00000020 |
| 212 | #define IFX_SSC_PERID_ID_MASK 0x0000FF00 |
| 213 | #define IFX_SSC_PERID_REV_OFFSET 0 |
| 214 | #define IFX_SSC_PERID_CFG_OFFSET 5 |
| 215 | #define IFX_SSC_PERID_ID_OFFSET 8 |
| 216 | #define IFX_SSC_PERID_ID 0x45 |
| 217 | #define IFX_SSC_PERID_DMA_ON 0x00000020 |
| 218 | #define IFX_SSC_PERID_RXFS_MASK 0x003F0000 |
| 219 | #define IFX_SSC_PERID_RXFS_OFFSET 16 |
| 220 | #define IFX_SSC_PERID_TXFS_MASK 0x3F000000 |
| 221 | #define IFX_SSC_PERID_TXFS_OFFSET 24 |
| 222 | |
| 223 | /* PISEL register */ |
| 224 | #define IFX_SSC_PISEL_MASTER_IN_A 0x0000 |
| 225 | #define IFX_SSC_PISEL_MASTER_IN_B 0x0001 |
| 226 | #define IFX_SSC_PISEL_SLAVE_IN_A 0x0000 |
| 227 | #define IFX_SSC_PISEL_SLAVE_IN_B 0x0002 |
| 228 | #define IFX_SSC_PISEL_CLOCK_IN_A 0x0000 |
| 229 | #define IFX_SSC_PISEL_CLOCK_IN_B 0x0004 |
| 230 | |
| 231 | |
| 232 | /* IFX_SSC_CON register */ |
| 233 | #define IFX_SSC_CON_ECHO_MODE_ON 0x01000000 |
| 234 | #define IFX_SSC_CON_ECHO_MODE_OFF 0x00000000 |
| 235 | #define IFX_SSC_CON_IDLE_HIGH 0x00800000 |
| 236 | #define IFX_SSC_CON_IDLE_LOW 0x00000000 |
| 237 | #define IFX_SSC_CON_ENABLE_BYTE_VALID 0x00400000 |
| 238 | #define IFX_SSC_CON_DISABLE_BYTE_VALID 0x00000000 |
| 239 | #define IFX_SSC_CON_DATA_WIDTH_OFFSET 16 |
| 240 | #define IFX_SSC_CON_DATA_WIDTH_MASK 0x001F0000 |
| 241 | #define IFX_SSC_ENCODE_DATA_WIDTH(width) (((width - 1) << IFX_SSC_CON_DATA_WIDTH_OFFSET) & IFX_SSC_CON_DATA_WIDTH_MASK) |
| 242 | |
| 243 | #define IFX_SSC_CON_RESET_ON_BAUDERR 0x00002000 |
| 244 | #define IFX_SSC_CON_GO_ON_ON_BAUDERR 0x00000000 |
| 245 | |
| 246 | #define IFX_SSC_CON_RX_UFL_CHECK 0x00001000 |
| 247 | #define IFX_SSC_CON_RX_UFL_IGNORE 0x00000000 |
| 248 | #define IFX_SSC_CON_TX_UFL_CHECK 0x00000800 |
| 249 | #define IFX_SSC_CON_TX_UFL_IGNORE 0x00000000 |
| 250 | #define IFX_SSC_CON_ABORT_ERR_CHECK 0x00000400 |
| 251 | #define IFX_SSC_CON_ABORT_ERR_IGNORE 0x00000000 |
| 252 | #define IFX_SSC_CON_RX_OFL_CHECK 0x00000200 |
| 253 | #define IFX_SSC_CON_RX_OFL_IGNORE 0x00000000 |
| 254 | #define IFX_SSC_CON_TX_OFL_CHECK 0x00000100 |
| 255 | #define IFX_SSC_CON_TX_OFL_IGNORE 0x00000000 |
| 256 | #define IFX_SSC_CON_ALL_ERR_CHECK 0x00001F00 |
| 257 | #define IFX_SSC_CON_ALL_ERR_IGNORE 0x00000000 |
| 258 | |
| 259 | #define IFX_SSC_CON_LOOPBACK_MODE 0x00000080 |
| 260 | #define IFX_SSC_CON_NO_LOOPBACK 0x00000000 |
| 261 | #define IFX_SSC_CON_HALF_DUPLEX 0x00000080 |
| 262 | #define IFX_SSC_CON_FULL_DUPLEX 0x00000000 |
| 263 | #define IFX_SSC_CON_CLOCK_FALL 0x00000040 |
| 264 | #define IFX_SSC_CON_CLOCK_RISE 0x00000000 |
| 265 | #define IFX_SSC_CON_SHIFT_THEN_LATCH 0x00000000 |
| 266 | #define IFX_SSC_CON_LATCH_THEN_SHIFT 0x00000020 |
| 267 | #define IFX_SSC_CON_MSB_FIRST 0x00000010 |
| 268 | #define IFX_SSC_CON_LSB_FIRST 0x00000000 |
| 269 | #define IFX_SSC_CON_ENABLE_CSB 0x00000008 |
| 270 | #define IFX_SSC_CON_DISABLE_CSB 0x00000000 |
| 271 | #define IFX_SSC_CON_INVERT_CSB 0x00000004 |
| 272 | #define IFX_SSC_CON_TRUE_CSB 0x00000000 |
| 273 | #define IFX_SSC_CON_RX_OFF 0x00000002 |
| 274 | #define IFX_SSC_CON_RX_ON 0x00000000 |
| 275 | #define IFX_SSC_CON_TX_OFF 0x00000001 |
| 276 | #define IFX_SSC_CON_TX_ON 0x00000000 |
| 277 | |
| 278 | |
| 279 | /* IFX_SSC_STATE register */ |
| 280 | #define IFX_SSC_STATE_RX_BYTE_VALID_OFFSET 28 |
| 281 | #define IFX_SSC_STATE_RX_BYTE_VALID_MASK 0x70000000 |
| 282 | #define IFX_SSC_DECODE_RX_BYTE_VALID(con_state) ((con_state & IFX_SSC_STATE_RX_BYTE_VALID_MASK) >> IFX_SSC_STATE_RX_BYTE_VALID_OFFSET) |
| 283 | #define IFX_SSC_STATE_TX_BYTE_VALID_OFFSET 24 |
| 284 | #define IFX_SSC_STATE_TX_BYTE_VALID_MASK 0x07000000 |
| 285 | #define IFX_SSC_DECODE_TX_BYTE_VALID(con_state) ((con_state & IFX_SSC_STATE_TX_BYTE_VALID_MASK) >> IFX_SSC_STATE_TX_BYTE_VALID_OFFSET) |
| 286 | #define IFX_SSC_STATE_BIT_COUNT_OFFSET 16 |
| 287 | #define IFX_SSC_STATE_BIT_COUNT_MASK 0x001F0000 |
| 288 | #define IFX_SSC_DECODE_DATA_WIDTH(con_state) (((con_state & IFX_SSC_STATE_BIT_COUNT_MASK) >> IFX_SSC_STATE_BIT_COUNT_OFFSET) + 1) |
| 289 | #define IFX_SSC_STATE_BUSY 0x00002000 |
| 290 | #define IFX_SSC_STATE_RX_UFL 0x00001000 |
| 291 | #define IFX_SSC_STATE_TX_UFL 0x00000800 |
| 292 | #define IFX_SSC_STATE_ABORT_ERR 0x00000400 |
| 293 | #define IFX_SSC_STATE_RX_OFL 0x00000200 |
| 294 | #define IFX_SSC_STATE_TX_OFL 0x00000100 |
| 295 | #define IFX_SSC_STATE_MODE_ERR 0x00000080 |
| 296 | #define IFX_SSC_STATE_SLAVE_IS_SELECTED 0x00000004 |
| 297 | #define IFX_SSC_STATE_IS_MASTER 0x00000002 |
| 298 | #define IFX_SSC_STATE_IS_ENABLED 0x00000001 |
| 299 | |
| 300 | /* WHBSTATE register */ |
| 301 | #define IFX_SSC_WHBSTATE_DISABLE_SSC 0x0001 |
| 302 | #define IFX_SSC_WHBSTATE_CONFIGURATION_MODE 0x0001 |
| 303 | #define IFX_SSC_WHBSTATE_CLR_ENABLE 0x0001 |
| 304 | |
| 305 | #define IFX_SSC_WHBSTATE_ENABLE_SSC 0x0002 |
| 306 | #define IFX_SSC_WHBSTATE_RUN_MODE 0x0002 |
| 307 | #define IFX_SSC_WHBSTATE_SET_ENABLE 0x0002 |
| 308 | |
| 309 | #define IFX_SSC_WHBSTATE_SLAVE_MODE 0x0004 |
| 310 | #define IFX_SSC_WHBSTATE_CLR_MASTER_SELECT 0x0004 |
| 311 | |
| 312 | #define IFX_SSC_WHBSTATE_MASTER_MODE 0x0008 |
| 313 | #define IFX_SSC_WHBSTATE_SET_MASTER_SELECT 0x0008 |
| 314 | |
| 315 | #define IFX_SSC_WHBSTATE_CLR_RX_UFL_ERROR 0x0010 |
| 316 | #define IFX_SSC_WHBSTATE_SET_RX_UFL_ERROR 0x0020 |
| 317 | |
| 318 | #define IFX_SSC_WHBSTATE_CLR_MODE_ERROR 0x0040 |
| 319 | #define IFX_SSC_WHBSTATE_SET_MODE_ERROR 0x0080 |
| 320 | |
| 321 | #define IFX_SSC_WHBSTATE_CLR_TX_OFL_ERROR 0x0100 |
| 322 | #define IFX_SSC_WHBSTATE_CLR_RX_OFL_ERROR 0x0200 |
| 323 | #define IFX_SSC_WHBSTATE_CLR_ABORT_ERROR 0x0400 |
| 324 | #define IFX_SSC_WHBSTATE_CLR_TX_UFL_ERROR 0x0800 |
| 325 | #define IFX_SSC_WHBSTATE_SET_TX_OFL_ERROR 0x1000 |
| 326 | #define IFX_SSC_WHBSTATE_SET_RX_OFL_ERROR 0x2000 |
| 327 | #define IFX_SSC_WHBSTATE_SET_ABORT_ERROR 0x4000 |
| 328 | #define IFX_SSC_WHBSTATE_SET_TX_UFL_ERROR 0x8000 |
| 329 | #define IFX_SSC_WHBSTATE_CLR_ALL_ERROR 0x0F50 |
| 330 | #define IFX_SSC_WHBSTATE_SET_ALL_ERROR 0xF0A0 |
| 331 | |
| 332 | /* BR register */ |
| 333 | #define IFX_SSC_BR_BAUDRATE_OFFSET 0 |
| 334 | #define IFX_SSC_BR_BAUDRATE_MASK 0xFFFF |
| 335 | |
| 336 | /* BR_STAT register */ |
| 337 | #define IFX_SSC_BRSTAT_BAUDTIMER_OFFSET 0 |
| 338 | #define IFX_SSC_BRSTAT_BAUDTIMER_MASK 0xFFFF |
| 339 | |
| 340 | /* TB register */ |
| 341 | #define IFX_SSC_TB_DATA_OFFSET 0 |
| 342 | #define IFX_SSC_TB_DATA_MASK 0xFFFFFFFF |
| 343 | |
| 344 | /* RB register */ |
| 345 | #define IFX_SSC_RB_DATA_OFFSET 0 |
| 346 | #define IFX_SSC_RB_DATA_MASK 0xFFFFFFFF |
| 347 | |
| 348 | |
| 349 | /* RXFCON and TXFCON registers */ |
| 350 | #define IFX_SSC_XFCON_FIFO_DISABLE 0x0000 |
| 351 | #define IFX_SSC_XFCON_FIFO_ENABLE 0x0001 |
| 352 | #define IFX_SSC_XFCON_FIFO_FLUSH 0x0002 |
| 353 | #define IFX_SSC_XFCON_ITL_MASK 0x00003F00 |
| 354 | #define IFX_SSC_XFCON_ITL_OFFSET 8 |
| 355 | |
| 356 | /* FSTAT register */ |
| 357 | #define IFX_SSC_FSTAT_RECEIVED_WORDS_OFFSET 0 |
| 358 | #define IFX_SSC_FSTAT_RECEIVED_WORDS_MASK 0x003F |
| 359 | #define IFX_SSC_FSTAT_TRANSMIT_WORDS_OFFSET 8 |
| 360 | #define IFX_SSC_FSTAT_TRANSMIT_WORDS_MASK 0x3F00 |
| 361 | |
| 362 | /* GPOCON register */ |
| 363 | #define IFX_SSC_GPOCON_INVOUT0_POS 0 |
| 364 | #define IFX_SSC_GPOCON_INV_OUT0 0x00000001 |
| 365 | #define IFX_SSC_GPOCON_TRUE_OUT0 0x00000000 |
| 366 | #define IFX_SSC_GPOCON_INVOUT1_POS 1 |
| 367 | #define IFX_SSC_GPOCON_INV_OUT1 0x00000002 |
| 368 | #define IFX_SSC_GPOCON_TRUE_OUT1 0x00000000 |
| 369 | #define IFX_SSC_GPOCON_INVOUT2_POS 2 |
| 370 | #define IFX_SSC_GPOCON_INV_OUT2 0x00000003 |
| 371 | #define IFX_SSC_GPOCON_TRUE_OUT2 0x00000000 |
| 372 | #define IFX_SSC_GPOCON_INVOUT3_POS 3 |
| 373 | #define IFX_SSC_GPOCON_INV_OUT3 0x00000008 |
| 374 | #define IFX_SSC_GPOCON_TRUE_OUT3 0x00000000 |
| 375 | #define IFX_SSC_GPOCON_INVOUT4_POS 4 |
| 376 | #define IFX_SSC_GPOCON_INV_OUT4 0x00000010 |
| 377 | #define IFX_SSC_GPOCON_TRUE_OUT4 0x00000000 |
| 378 | #define IFX_SSC_GPOCON_INVOUT5_POS 5 |
| 379 | #define IFX_SSC_GPOCON_INV_OUT5 0x00000020 |
| 380 | #define IFX_SSC_GPOCON_TRUE_OUT5 0x00000000 |
| 381 | #define IFX_SSC_GPOCON_INVOUT6_POS 6 |
| 382 | #define IFX_SSC_GPOCON_INV_OUT6 0x00000040 |
| 383 | #define IFX_SSC_GPOCON_TRUE_OUT6 0x00000000 |
| 384 | #define IFX_SSC_GPOCON_INVOUT7_POS 7 |
| 385 | #define IFX_SSC_GPOCON_INV_OUT7 0x00000080 |
| 386 | #define IFX_SSC_GPOCON_TRUE_OUT7 0x00000000 |
| 387 | #define IFX_SSC_GPOCON_INV_OUT_ALL 0x000000FF |
| 388 | #define IFX_SSC_GPOCON_TRUE_OUT_ALL 0x00000000 |
| 389 | |
| 390 | #define IFX_SSC_GPOCON_ISCSB0_POS 8 |
| 391 | #define IFX_SSC_GPOCON_IS_CSB0 0x00000100 |
| 392 | #define IFX_SSC_GPOCON_IS_GPO0 0x00000000 |
| 393 | #define IFX_SSC_GPOCON_ISCSB1_POS 9 |
| 394 | #define IFX_SSC_GPOCON_IS_CSB1 0x00000200 |
| 395 | #define IFX_SSC_GPOCON_IS_GPO1 0x00000000 |
| 396 | #define IFX_SSC_GPOCON_ISCSB2_POS 10 |
| 397 | #define IFX_SSC_GPOCON_IS_CSB2 0x00000400 |
| 398 | #define IFX_SSC_GPOCON_IS_GPO2 0x00000000 |
| 399 | #define IFX_SSC_GPOCON_ISCSB3_POS 11 |
| 400 | #define IFX_SSC_GPOCON_IS_CSB3 0x00000800 |
| 401 | #define IFX_SSC_GPOCON_IS_GPO3 0x00000000 |
| 402 | #define IFX_SSC_GPOCON_ISCSB4_POS 12 |
| 403 | #define IFX_SSC_GPOCON_IS_CSB4 0x00001000 |
| 404 | #define IFX_SSC_GPOCON_IS_GPO4 0x00000000 |
| 405 | #define IFX_SSC_GPOCON_ISCSB5_POS 13 |
| 406 | #define IFX_SSC_GPOCON_IS_CSB5 0x00002000 |
| 407 | #define IFX_SSC_GPOCON_IS_GPO5 0x00000000 |
| 408 | #define IFX_SSC_GPOCON_ISCSB6_POS 14 |
| 409 | #define IFX_SSC_GPOCON_IS_CSB6 0x00004000 |
| 410 | #define IFX_SSC_GPOCON_IS_GPO6 0x00000000 |
| 411 | #define IFX_SSC_GPOCON_ISCSB7_POS 15 |
| 412 | #define IFX_SSC_GPOCON_IS_CSB7 0x00008000 |
| 413 | #define IFX_SSC_GPOCON_IS_GPO7 0x00000000 |
| 414 | #define IFX_SSC_GPOCON_IS_CSB_ALL 0x0000FF00 |
| 415 | #define IFX_SSC_GPOCON_IS_GPO_ALL 0x00000000 |
| 416 | |
| 417 | /* GPOSTAT register */ |
| 418 | #define IFX_SSC_GPOSTAT_OUT0 0x00000001 |
| 419 | #define IFX_SSC_GPOSTAT_OUT1 0x00000002 |
| 420 | #define IFX_SSC_GPOSTAT_OUT2 0x00000004 |
| 421 | #define IFX_SSC_GPOSTAT_OUT3 0x00000008 |
| 422 | #define IFX_SSC_GPOSTAT_OUT4 0x00000010 |
| 423 | #define IFX_SSC_GPOSTAT_OUT5 0x00000020 |
| 424 | #define IFX_SSC_GPOSTAT_OUT6 0x00000040 |
| 425 | #define IFX_SSC_GPOSTAT_OUT7 0x00000080 |
| 426 | #define IFX_SSC_GPOSTAT_OUT_ALL 0x000000FF |
| 427 | |
| 428 | /* WHBGPOSTAT register */ |
| 429 | #define IFX_SSC_WHBGPOSTAT_CLROUT0_POS 0 |
| 430 | #define IFX_SSC_WHBGPOSTAT_CLR_OUT0 0x00000001 |
| 431 | #define IFX_SSC_WHBGPOSTAT_CLROUT1_POS 1 |
| 432 | #define IFX_SSC_WHBGPOSTAT_CLR_OUT1 0x00000002 |
| 433 | #define IFX_SSC_WHBGPOSTAT_CLROUT2_POS 2 |
| 434 | #define IFX_SSC_WHBGPOSTAT_CLR_OUT2 0x00000004 |
| 435 | #define IFX_SSC_WHBGPOSTAT_CLROUT3_POS 3 |
| 436 | #define IFX_SSC_WHBGPOSTAT_CLR_OUT3 0x00000008 |
| 437 | #define IFX_SSC_WHBGPOSTAT_CLROUT4_POS 4 |
| 438 | #define IFX_SSC_WHBGPOSTAT_CLR_OUT4 0x00000010 |
| 439 | #define IFX_SSC_WHBGPOSTAT_CLROUT5_POS 5 |
| 440 | #define IFX_SSC_WHBGPOSTAT_CLR_OUT5 0x00000020 |
| 441 | #define IFX_SSC_WHBGPOSTAT_CLROUT6_POS 6 |
| 442 | #define IFX_SSC_WHBGPOSTAT_CLR_OUT6 0x00000040 |
| 443 | #define IFX_SSC_WHBGPOSTAT_CLROUT7_POS 7 |
| 444 | #define IFX_SSC_WHBGPOSTAT_CLR_OUT7 0x00000080 |
| 445 | #define IFX_SSC_WHBGPOSTAT_CLR_OUT_ALL 0x000000FF |
| 446 | |
| 447 | #define IFX_SSC_WHBGPOSTAT_OUT0_POS 0 |
| 448 | #define IFX_SSC_WHBGPOSTAT_OUT1_POS 1 |
| 449 | #define IFX_SSC_WHBGPOSTAT_OUT2_POS 2 |
| 450 | #define IFX_SSC_WHBGPOSTAT_OUT3_POS 3 |
| 451 | #define IFX_SSC_WHBGPOSTAT_OUT4_POS 4 |
| 452 | #define IFX_SSC_WHBGPOSTAT_OUT5_POS 5 |
| 453 | #define IFX_SSC_WHBGPOSTAT_OUT6_POS 6 |
| 454 | #define IFX_SSC_WHBGPOSTAT_OUT7_POS 7 |
| 455 | |
| 456 | |
| 457 | #define IFX_SSC_WHBGPOSTAT_SETOUT0_POS 8 |
| 458 | #define IFX_SSC_WHBGPOSTAT_SET_OUT0 0x00000100 |
| 459 | #define IFX_SSC_WHBGPOSTAT_SETOUT1_POS 9 |
| 460 | #define IFX_SSC_WHBGPOSTAT_SET_OUT1 0x00000200 |
| 461 | #define IFX_SSC_WHBGPOSTAT_SETOUT2_POS 10 |
| 462 | #define IFX_SSC_WHBGPOSTAT_SET_OUT2 0x00000400 |
| 463 | #define IFX_SSC_WHBGPOSTAT_SETOUT3_POS 11 |
| 464 | #define IFX_SSC_WHBGPOSTAT_SET_OUT3 0x00000800 |
| 465 | #define IFX_SSC_WHBGPOSTAT_SETOUT4_POS 12 |
| 466 | #define IFX_SSC_WHBGPOSTAT_SET_OUT4 0x00001000 |
| 467 | #define IFX_SSC_WHBGPOSTAT_SETOUT5_POS 13 |
| 468 | #define IFX_SSC_WHBGPOSTAT_SET_OUT5 0x00002000 |
| 469 | #define IFX_SSC_WHBGPOSTAT_SETOUT6_POS 14 |
| 470 | #define IFX_SSC_WHBGPOSTAT_SET_OUT6 0x00004000 |
| 471 | #define IFX_SSC_WHBGPOSTAT_SETOUT7_POS 15 |
| 472 | #define IFX_SSC_WHBGPOSTAT_SET_OUT7 0x00008000 |
| 473 | #define IFX_SSC_WHBGPOSTAT_SET_OUT_ALL 0x0000FF00 |
| 474 | |
| 475 | /* SFCON register */ |
| 476 | #define IFX_SSC_SFCON_SF_ENABLE 0x00000001 |
| 477 | #define IFX_SSC_SFCON_SF_DISABLE 0x00000000 |
| 478 | #define IFX_SSC_SFCON_FIR_ENABLE_BEFORE_PAUSE 0x00000004 |
| 479 | #define IFX_SSC_SFCON_FIR_DISABLE_BEFORE_PAUSE 0x00000000 |
| 480 | #define IFX_SSC_SFCON_FIR_ENABLE_AFTER_PAUSE 0x00000008 |
| 481 | #define IFX_SSC_SFCON_FIR_DISABLE_AFTER_PAUSE 0x00000000 |
| 482 | #define IFX_SSC_SFCON_DATA_LENGTH_MASK 0x0000FFF0 |
| 483 | #define IFX_SSC_SFCON_DATA_LENGTH_OFFSET 4 |
| 484 | #define IFX_SSC_SFCON_PAUSE_DATA_MASK 0x00030000 |
| 485 | #define IFX_SSC_SFCON_PAUSE_DATA_OFFSET 16 |
| 486 | #define IFX_SSC_SFCON_PAUSE_DATA_0 0x00000000 |
| 487 | #define IFX_SSC_SFCON_PAUSE_DATA_1 0x00010000 |
| 488 | #define IFX_SSC_SFCON_PAUSE_DATA_IDLE 0x00020000 |
| 489 | #define IFX_SSC_SFCON_PAUSE_CLOCK_MASK 0x000C0000 |
| 490 | #define IFX_SSC_SFCON_PAUSE_CLOCK_OFFSET 18 |
| 491 | #define IFX_SSC_SFCON_PAUSE_CLOCK_0 0x00000000 |
| 492 | #define IFX_SSC_SFCON_PAUSE_CLOCK_1 0x00040000 |
| 493 | #define IFX_SSC_SFCON_PAUSE_CLOCK_IDLE 0x00080000 |
| 494 | #define IFX_SSC_SFCON_PAUSE_CLOCK_RUN 0x000C0000 |
| 495 | #define IFX_SSC_SFCON_STOP_AFTER_PAUSE 0x00100000 |
| 496 | #define IFX_SSC_SFCON_CONTINUE_AFTER_PAUSE 0x00000000 |
| 497 | #define IFX_SSC_SFCON_PAUSE_LENGTH_MASK 0xFFC00000 |
| 498 | #define IFX_SSC_SFCON_PAUSE_LENGTH_OFFSET 22 |
| 499 | #define IFX_SSC_SFCON_DATA_LENGTH_MAX 4096 |
| 500 | #define IFX_SSC_SFCON_PAUSE_LENGTH_MAX 1024 |
| 501 | |
| 502 | #define IFX_SSC_SFCON_EXTRACT_DATA_LENGTH(sfcon) ((sfcon & IFX_SSC_SFCON_DATA_LENGTH_MASK) >> IFX_SSC_SFCON_DATA_LENGTH_OFFSET) |
| 503 | #define IFX_SSC_SFCON_EXTRACT_PAUSE_LENGTH(sfcon) ((sfcon & IFX_SSC_SFCON_PAUSE_LENGTH_MASK) >> IFX_SSC_SFCON_PAUSE_LENGTH_OFFSET) |
| 504 | #define IFX_SSC_SFCON_SET_DATA_LENGTH(value) ((value << IFX_SSC_SFCON_DATA_LENGTH_OFFSET) & IFX_SSC_SFCON_DATA_LENGTH_MASK) |
| 505 | #define IFX_SSC_SFCON_SET_PAUSE_LENGTH(value) ((value << IFX_SSC_SFCON_PAUSE_LENGTH_OFFSET) & IFX_SSC_SFCON_PAUSE_LENGTH_MASK) |
| 506 | |
| 507 | /* SFSTAT register */ |
| 508 | #define IFX_SSC_SFSTAT_IN_DATA 0x00000001 |
| 509 | #define IFX_SSC_SFSTAT_IN_PAUSE 0x00000002 |
| 510 | #define IFX_SSC_SFSTAT_DATA_COUNT_MASK 0x0000FFF0 |
| 511 | #define IFX_SSC_SFSTAT_DATA_COUNT_OFFSET 4 |
| 512 | #define IFX_SSC_SFSTAT_PAUSE_COUNT_MASK 0xFFF00000 |
| 513 | #define IFX_SSC_SFSTAT_PAUSE_COUNT_OFFSET 20 |
| 514 | |
| 515 | #define IFX_SSC_SFSTAT_EXTRACT_DATA_COUNT(sfstat) ((sfstat & IFX_SSC_SFSTAT_DATA_COUNT_MASK) >> IFX_SSC_SFSTAT_DATA_COUNT_OFFSET) |
| 516 | #define IFX_SSC_SFSTAT_EXTRACT_PAUSE_COUNT(sfstat) ((sfstat & IFX_SSC_SFSTAT_PAUSE_COUNT_MASK) >> IFX_SSC_SFSTAT_PAUSE_COUNT_OFFSET) |
| 517 | |
| 518 | /* RXREQ register */ |
| 519 | #define IFX_SSC_RXREQ_RXCOUNT_MASK 0x0000FFFF |
| 520 | #define IFX_SSC_RXREQ_RXCOUNT_OFFSET 0 |
| 521 | |
| 522 | /* RXCNT register */ |
| 523 | #define IFX_SSC_RXCNT_TODO_MASK 0x0000FFFF |
| 524 | #define IFX_SSC_RXCNT_TODO_OFFSET 0 |
| 525 | |
| 526 | /* DMACON register */ |
| 527 | #define IFX_SSC_DMACON_RXON 0x00000001 |
| 528 | #define IFX_SSC_DMACON_RXOFF 0x00000000 |
| 529 | #define IFX_SSC_DMACON_TXON 0x00000002 |
| 530 | #define IFX_SSC_DMACON_TXOFF 0x00000000 |
| 531 | #define IFX_SSC_DMACON_DMAON 0x00000003 |
| 532 | #define IFX_SSC_DMACON_DMAOFF 0x00000000 |
| 533 | #define IFX_SSC_DMACON_CLASS_MASK 0x0000000C |
| 534 | #define IFX_SSC_DMACON_CLASS_OFFSET 2 |
| 535 | |
| 536 | /* register access macros */ |
| 537 | #define ifx_ssc_fstat_received_words(status) (status & 0x003F) |
| 538 | #define ifx_ssc_fstat_words_to_transmit(status) ((status & 0x3F00) >> 8) |
| 539 | |
| 540 | #define ifx_ssc_change_status(data, addr) WRITE_PERIPHERAL_REGISTER(data, (PHYS_OFFSET + addr + IFX_SSC_WHBSTATE)) |
| 541 | #define ifx_ssc_set_config(data, addr) WRITE_PERIPHERAL_REGISTER(data, (PHYS_OFFSET + addr + IFX_SSC_CON)) |
| 542 | #define ifx_ssc_get_config(addr) READ_PERIPHERAL_REGISTER((PHYS_OFFSET + addr + IFX_SSC_CON)) |
| 543 | #define ifx_ssc_get_status(addr) READ_PERIPHERAL_REGISTER((PHYS_OFFSET + addr + IFX_SSC_STATE)) |
| 544 | #define ifx_ssc_receive(addr) READ_PERIPHERAL_REGISTER((PHYS_OFFSET + addr + IFX_SSC_RB)) |
| 545 | #define ifx_ssc_transmit(data, addr) WRITE_PERIPHERAL_REGISTER(data, (PHYS_OFFSET + addr + IFX_SSC_TB)) |
| 546 | #define ifx_ssc_fifo_status(addr) READ_PERIPHERAL_REGISTER((PHYS_OFFSET + addr + IFX_SSC_FSTAT)) |
| 547 | #define ifx_ssc_set_baudrate(data, addr) WRITE_PERIPHERAL_REGISTER(data, (PHYS_OFFSET + addr + IFX_SSC_BR)) |
| 548 | |
| 549 | #define ifx_ssc_extract_rx_fifo_size(id) ((id & IFX_SSC_PERID_RXFS_MASK) >> IFX_SSC_PERID_RXFS_OFFSET) |
| 550 | #define ifx_ssc_extract_tx_fifo_size(id) ((id & IFX_SSC_PERID_TXFS_MASK) >> IFX_SSC_PERID_TXFS_OFFSET) |
| 551 | |
| 552 | #endif |
| 553 | |
