| 1 | /* |
| 2 | * Atheros PB42 board support |
| 3 | * |
| 4 | * Copyright (C) 2008-2012 Gabor Juhos <juhosg@openwrt.org> |
| 5 | * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org> |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify it |
| 8 | * under the terms of the GNU General Public License version 2 as published |
| 9 | * by the Free Software Foundation. |
| 10 | */ |
| 11 | |
| 12 | #include <asm/mach-ath79/ath79.h> |
| 13 | |
| 14 | #include "dev-eth.h" |
| 15 | #include "dev-gpio-buttons.h" |
| 16 | #include "dev-m25p80.h" |
| 17 | #include "dev-usb.h" |
| 18 | #include "machtypes.h" |
| 19 | #include "pci.h" |
| 20 | |
| 21 | #define PB42_KEYS_POLL_INTERVAL 20 /* msecs */ |
| 22 | #define PB42_KEYS_DEBOUNCE_INTERVAL (3 * PB42_KEYS_POLL_INTERVAL) |
| 23 | |
| 24 | #define PB42_GPIO_BTN_SW4 8 |
| 25 | #define PB42_GPIO_BTN_SW5 3 |
| 26 | |
| 27 | static struct gpio_keys_button pb42_gpio_keys[] __initdata = { |
| 28 | { |
| 29 | .desc = "sw4", |
| 30 | .type = EV_KEY, |
| 31 | .code = BTN_0, |
| 32 | .debounce_interval = PB42_KEYS_DEBOUNCE_INTERVAL, |
| 33 | .gpio = PB42_GPIO_BTN_SW4, |
| 34 | .active_low = 1, |
| 35 | }, { |
| 36 | .desc = "sw5", |
| 37 | .type = EV_KEY, |
| 38 | .code = BTN_1, |
| 39 | .debounce_interval = PB42_KEYS_DEBOUNCE_INTERVAL, |
| 40 | .gpio = PB42_GPIO_BTN_SW5, |
| 41 | .active_low = 1, |
| 42 | } |
| 43 | }; |
| 44 | |
| 45 | static const char *pb42_part_probes[] = { |
| 46 | "RedBoot", |
| 47 | NULL, |
| 48 | }; |
| 49 | |
| 50 | static struct flash_platform_data pb42_flash_data = { |
| 51 | .part_probes = pb42_part_probes, |
| 52 | }; |
| 53 | |
| 54 | #define PB42_WAN_PHYMASK BIT(20) |
| 55 | #define PB42_LAN_PHYMASK (BIT(16) | BIT(17) | BIT(18) | BIT(19)) |
| 56 | #define PB42_MDIO_PHYMASK (PB42_LAN_PHYMASK | PB42_WAN_PHYMASK) |
| 57 | |
| 58 | static void __init pb42_init(void) |
| 59 | { |
| 60 | ath79_register_m25p80(&pb42_flash_data); |
| 61 | |
| 62 | ath79_register_mdio(0, ~PB42_MDIO_PHYMASK); |
| 63 | |
| 64 | ath79_init_mac(ath79_eth0_data.mac_addr, ath79_mac_base, 0); |
| 65 | ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII; |
| 66 | ath79_eth0_data.phy_mask = PB42_WAN_PHYMASK; |
| 67 | |
| 68 | ath79_init_mac(ath79_eth1_data.mac_addr, ath79_mac_base, 1); |
| 69 | ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RMII; |
| 70 | ath79_eth1_data.speed = SPEED_100; |
| 71 | ath79_eth1_data.duplex = DUPLEX_FULL; |
| 72 | |
| 73 | ath79_register_eth(0); |
| 74 | ath79_register_eth(1); |
| 75 | |
| 76 | ath79_register_gpio_keys_polled(-1, PB42_KEYS_POLL_INTERVAL, |
| 77 | ARRAY_SIZE(pb42_gpio_keys), |
| 78 | pb42_gpio_keys); |
| 79 | |
| 80 | ath79_register_pci(); |
| 81 | } |
| 82 | |
| 83 | MIPS_MACHINE(ATH79_MACH_PB42, "PB42", "Atheros PB42", pb42_init); |
| 84 | |
