| 1 | /* |
| 2 | * Linksys WRT400N board support |
| 3 | * |
| 4 | * Copyright (C) 2009-2012 Gabor Juhos <juhosg@openwrt.org> |
| 5 | * Copyright (C) 2009 Imre Kaloz <kaloz@openwrt.org> |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify it |
| 8 | * under the terms of the GNU General Public License version 2 as published |
| 9 | * by the Free Software Foundation. |
| 10 | */ |
| 11 | |
| 12 | #include <linux/mtd/mtd.h> |
| 13 | #include <linux/mtd/partitions.h> |
| 14 | |
| 15 | #include <asm/mach-ath79/ath79.h> |
| 16 | |
| 17 | #include "dev-ap9x-pci.h" |
| 18 | #include "dev-eth.h" |
| 19 | #include "dev-gpio-buttons.h" |
| 20 | #include "dev-leds-gpio.h" |
| 21 | #include "dev-m25p80.h" |
| 22 | #include "machtypes.h" |
| 23 | |
| 24 | #define WRT400N_GPIO_LED_POWER 1 |
| 25 | #define WRT400N_GPIO_LED_WPS_BLUE 4 |
| 26 | #define WRT400N_GPIO_LED_WPS_AMBER 5 |
| 27 | #define WRT400N_GPIO_LED_WLAN 6 |
| 28 | |
| 29 | #define WRT400N_GPIO_BTN_RESET 8 |
| 30 | #define WRT400N_GPIO_BTN_WLSEC 3 |
| 31 | |
| 32 | #define WRT400N_KEYS_POLL_INTERVAL 20 /* msecs */ |
| 33 | #define WRT400N_KEYS_DEBOUNE_INTERVAL (3 * WRT400N_KEYS_POLL_INTERVAL) |
| 34 | |
| 35 | #define WRT400N_MAC_ADDR_OFFSET 0x120c |
| 36 | #define WRT400N_CALDATA0_OFFSET 0x1000 |
| 37 | #define WRT400N_CALDATA1_OFFSET 0x5000 |
| 38 | |
| 39 | static struct mtd_partition wrt400n_partitions[] = { |
| 40 | { |
| 41 | .name = "uboot", |
| 42 | .offset = 0, |
| 43 | .size = 0x030000, |
| 44 | .mask_flags = MTD_WRITEABLE, |
| 45 | }, { |
| 46 | .name = "env", |
| 47 | .offset = 0x030000, |
| 48 | .size = 0x010000, |
| 49 | .mask_flags = MTD_WRITEABLE, |
| 50 | }, { |
| 51 | .name = "linux", |
| 52 | .offset = 0x040000, |
| 53 | .size = 0x140000, |
| 54 | }, { |
| 55 | .name = "rootfs", |
| 56 | .offset = 0x180000, |
| 57 | .size = 0x630000, |
| 58 | }, { |
| 59 | .name = "nvram", |
| 60 | .offset = 0x7b0000, |
| 61 | .size = 0x010000, |
| 62 | .mask_flags = MTD_WRITEABLE, |
| 63 | }, { |
| 64 | .name = "factory", |
| 65 | .offset = 0x7c0000, |
| 66 | .size = 0x010000, |
| 67 | .mask_flags = MTD_WRITEABLE, |
| 68 | }, { |
| 69 | .name = "language", |
| 70 | .offset = 0x7d0000, |
| 71 | .size = 0x020000, |
| 72 | .mask_flags = MTD_WRITEABLE, |
| 73 | }, { |
| 74 | .name = "caldata", |
| 75 | .offset = 0x7f0000, |
| 76 | .size = 0x010000, |
| 77 | .mask_flags = MTD_WRITEABLE, |
| 78 | }, { |
| 79 | .name = "firmware", |
| 80 | .offset = 0x040000, |
| 81 | .size = 0x770000, |
| 82 | } |
| 83 | }; |
| 84 | |
| 85 | static struct flash_platform_data wrt400n_flash_data = { |
| 86 | .parts = wrt400n_partitions, |
| 87 | .nr_parts = ARRAY_SIZE(wrt400n_partitions), |
| 88 | }; |
| 89 | |
| 90 | static struct gpio_led wrt400n_leds_gpio[] __initdata = { |
| 91 | { |
| 92 | .name = "wrt400n:blue:wps", |
| 93 | .gpio = WRT400N_GPIO_LED_WPS_BLUE, |
| 94 | .active_low = 1, |
| 95 | }, { |
| 96 | .name = "wrt400n:amber:wps", |
| 97 | .gpio = WRT400N_GPIO_LED_WPS_AMBER, |
| 98 | .active_low = 1, |
| 99 | }, { |
| 100 | .name = "wrt400n:blue:wlan", |
| 101 | .gpio = WRT400N_GPIO_LED_WLAN, |
| 102 | .active_low = 1, |
| 103 | }, { |
| 104 | .name = "wrt400n:blue:power", |
| 105 | .gpio = WRT400N_GPIO_LED_POWER, |
| 106 | .active_low = 0, |
| 107 | .default_trigger = "default-on", |
| 108 | } |
| 109 | }; |
| 110 | |
| 111 | static struct gpio_keys_button wrt400n_gpio_keys[] __initdata = { |
| 112 | { |
| 113 | .desc = "reset", |
| 114 | .type = EV_KEY, |
| 115 | .code = KEY_RESTART, |
| 116 | .debounce_interval = WRT400N_KEYS_DEBOUNE_INTERVAL, |
| 117 | .gpio = WRT400N_GPIO_BTN_RESET, |
| 118 | .active_low = 1, |
| 119 | }, { |
| 120 | .desc = "wlsec", |
| 121 | .type = EV_KEY, |
| 122 | .code = KEY_WPS_BUTTON, |
| 123 | .debounce_interval = WRT400N_KEYS_DEBOUNE_INTERVAL, |
| 124 | .gpio = WRT400N_GPIO_BTN_WLSEC, |
| 125 | .active_low = 1, |
| 126 | } |
| 127 | }; |
| 128 | |
| 129 | static void __init wrt400n_setup(void) |
| 130 | { |
| 131 | u8 *art = (u8 *) KSEG1ADDR(0x1fff0000); |
| 132 | u8 *mac = art + WRT400N_MAC_ADDR_OFFSET; |
| 133 | |
| 134 | ath79_register_mdio(0, 0x0); |
| 135 | |
| 136 | ath79_init_mac(ath79_eth0_data.mac_addr, mac, 1); |
| 137 | ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RMII; |
| 138 | ath79_eth0_data.speed = SPEED_100; |
| 139 | ath79_eth0_data.duplex = DUPLEX_FULL; |
| 140 | |
| 141 | ath79_init_mac(ath79_eth1_data.mac_addr, mac, 2); |
| 142 | ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RMII; |
| 143 | ath79_eth1_data.phy_mask = 0x10; |
| 144 | |
| 145 | ath79_register_eth(0); |
| 146 | ath79_register_eth(1); |
| 147 | |
| 148 | ath79_register_m25p80(&wrt400n_flash_data); |
| 149 | |
| 150 | ath79_register_leds_gpio(-1, ARRAY_SIZE(wrt400n_leds_gpio), |
| 151 | wrt400n_leds_gpio); |
| 152 | |
| 153 | ath79_register_gpio_keys_polled(-1, WRT400N_KEYS_POLL_INTERVAL, |
| 154 | ARRAY_SIZE(wrt400n_gpio_keys), |
| 155 | wrt400n_gpio_keys); |
| 156 | |
| 157 | ap94_pci_init(art + WRT400N_CALDATA0_OFFSET, NULL, |
| 158 | art + WRT400N_CALDATA1_OFFSET, NULL); |
| 159 | } |
| 160 | |
| 161 | MIPS_MACHINE(ATH79_MACH_WRT400N, "WRT400N", "Linksys WRT400N", wrt400n_setup); |
| 162 | |
