Root/target/linux/ar71xx/files/drivers/mtd/nand/ar934x_nfc.c

1/*
2 * Driver for the built-in NAND controller of the Atheros AR934x SoCs
3 *
4 * Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation.
9 */
10
11#include <linux/init.h>
12#include <linux/interrupt.h>
13#include <linux/module.h>
14#include <linux/dma-mapping.h>
15#include <linux/mtd/mtd.h>
16#include <linux/mtd/nand.h>
17#include <linux/mtd/partitions.h>
18#include <linux/platform_device.h>
19#include <linux/delay.h>
20#include <linux/slab.h>
21
22#include <linux/platform/ar934x_nfc.h>
23
24#define AR934X_NFC_REG_CMD 0x00
25#define AR934X_NFC_REG_CTRL 0x04
26#define AR934X_NFC_REG_STATUS 0x08
27#define AR934X_NFC_REG_INT_MASK 0x0c
28#define AR934X_NFC_REG_INT_STATUS 0x10
29#define AR934X_NFC_REG_ECC_CTRL 0x14
30#define AR934X_NFC_REG_ECC_OFFSET 0x18
31#define AR934X_NFC_REG_ADDR0_0 0x1c
32#define AR934X_NFC_REG_ADDR0_1 0x24
33#define AR934X_NFC_REG_ADDR1_0 0x20
34#define AR934X_NFC_REG_ADDR1_1 0x28
35#define AR934X_NFC_REG_SPARE_SIZE 0x30
36#define AR934X_NFC_REG_PROTECT 0x38
37#define AR934X_NFC_REG_LOOKUP_EN 0x40
38#define AR934X_NFC_REG_LOOKUP(_x) (0x44 + (_i) * 4)
39#define AR934X_NFC_REG_DMA_ADDR 0x64
40#define AR934X_NFC_REG_DMA_COUNT 0x68
41#define AR934X_NFC_REG_DMA_CTRL 0x6c
42#define AR934X_NFC_REG_MEM_CTRL 0x80
43#define AR934X_NFC_REG_DATA_SIZE 0x84
44#define AR934X_NFC_REG_READ_STATUS 0x88
45#define AR934X_NFC_REG_TIME_SEQ 0x8c
46#define AR934X_NFC_REG_TIMINGS_ASYN 0x90
47#define AR934X_NFC_REG_TIMINGS_SYN 0x94
48#define AR934X_NFC_REG_FIFO_DATA 0x98
49#define AR934X_NFC_REG_TIME_MODE 0x9c
50#define AR934X_NFC_REG_DMA_ADDR_OFFS 0xa0
51#define AR934X_NFC_REG_FIFO_INIT 0xb0
52#define AR934X_NFC_REG_GEN_SEQ_CTRL 0xb4
53
54#define AR934X_NFC_CMD_CMD_SEQ_S 0
55#define AR934X_NFC_CMD_CMD_SEQ_M 0x3f
56#define AR934X_NFC_CMD_SEQ_1C 0x00
57#define AR934X_NFC_CMD_SEQ_ERASE 0x0e
58#define AR934X_NFC_CMD_SEQ_12 0x0c
59#define AR934X_NFC_CMD_SEQ_1C1AXR 0x21
60#define AR934X_NFC_CMD_SEQ_S 0x24
61#define AR934X_NFC_CMD_SEQ_1C3AXR 0x27
62#define AR934X_NFC_CMD_SEQ_1C5A1CXR 0x2a
63#define AR934X_NFC_CMD_SEQ_18 0x32
64#define AR934X_NFC_CMD_INPUT_SEL_SIU 0
65#define AR934X_NFC_CMD_INPUT_SEL_DMA BIT(6)
66#define AR934X_NFC_CMD_ADDR_SEL_0 0
67#define AR934X_NFC_CMD_ADDR_SEL_1 BIT(7)
68#define AR934X_NFC_CMD_CMD0_S 8
69#define AR934X_NFC_CMD_CMD0_M 0xff
70#define AR934X_NFC_CMD_CMD1_S 16
71#define AR934X_NFC_CMD_CMD1_M 0xff
72#define AR934X_NFC_CMD_CMD2_S 24
73#define AR934X_NFC_CMD_CMD2_M 0xff
74
75#define AR934X_NFC_CTRL_ADDR_CYCLE0_M 0x7
76#define AR934X_NFC_CTRL_ADDR_CYCLE0_S 0
77#define AR934X_NFC_CTRL_SPARE_EN BIT(3)
78#define AR934X_NFC_CTRL_INT_EN BIT(4)
79#define AR934X_NFC_CTRL_ECC_EN BIT(5)
80#define AR934X_NFC_CTRL_BLOCK_SIZE_S 6
81#define AR934X_NFC_CTRL_BLOCK_SIZE_M 0x3
82#define AR934X_NFC_CTRL_BLOCK_SIZE_32 0
83#define AR934X_NFC_CTRL_BLOCK_SIZE_64 1
84#define AR934X_NFC_CTRL_BLOCK_SIZE_128 2
85#define AR934X_NFC_CTRL_BLOCK_SIZE_256 3
86#define AR934X_NFC_CTRL_PAGE_SIZE_S 8
87#define AR934X_NFC_CTRL_PAGE_SIZE_M 0x7
88#define AR934X_NFC_CTRL_PAGE_SIZE_256 0
89#define AR934X_NFC_CTRL_PAGE_SIZE_512 1
90#define AR934X_NFC_CTRL_PAGE_SIZE_1024 2
91#define AR934X_NFC_CTRL_PAGE_SIZE_2048 3
92#define AR934X_NFC_CTRL_PAGE_SIZE_4096 4
93#define AR934X_NFC_CTRL_PAGE_SIZE_8192 5
94#define AR934X_NFC_CTRL_PAGE_SIZE_16384 6
95#define AR934X_NFC_CTRL_CUSTOM_SIZE_EN BIT(11)
96#define AR934X_NFC_CTRL_IO_WIDTH_8BITS 0
97#define AR934X_NFC_CTRL_IO_WIDTH_16BITS BIT(12)
98#define AR934X_NFC_CTRL_LOOKUP_EN BIT(13)
99#define AR934X_NFC_CTRL_PROT_EN BIT(14)
100#define AR934X_NFC_CTRL_WORK_MODE_ASYNC 0
101#define AR934X_NFC_CTRL_WORK_MODE_SYNC BIT(15)
102#define AR934X_NFC_CTRL_ADDR0_AUTO_INC BIT(16)
103#define AR934X_NFC_CTRL_ADDR1_AUTO_INC BIT(17)
104#define AR934X_NFC_CTRL_ADDR_CYCLE1_M 0x7
105#define AR934X_NFC_CTRL_ADDR_CYCLE1_S 18
106#define AR934X_NFC_CTRL_SMALL_PAGE BIT(21)
107
108#define AR934X_NFC_DMA_CTRL_DMA_START BIT(7)
109#define AR934X_NFC_DMA_CTRL_DMA_DIR_WRITE 0
110#define AR934X_NFC_DMA_CTRL_DMA_DIR_READ BIT(6)
111#define AR934X_NFC_DMA_CTRL_DMA_MODE_SG BIT(5)
112#define AR934X_NFC_DMA_CTRL_DMA_BURST_S 2
113#define AR934X_NFC_DMA_CTRL_DMA_BURST_0 0
114#define AR934X_NFC_DMA_CTRL_DMA_BURST_1 1
115#define AR934X_NFC_DMA_CTRL_DMA_BURST_2 2
116#define AR934X_NFC_DMA_CTRL_DMA_BURST_3 3
117#define AR934X_NFC_DMA_CTRL_DMA_BURST_4 4
118#define AR934X_NFC_DMA_CTRL_DMA_BURST_5 5
119#define AR934X_NFC_DMA_CTRL_ERR_FLAG BIT(1)
120#define AR934X_NFC_DMA_CTRL_DMA_READY BIT(0)
121
122#define AR934X_NFC_INT_DEV_RDY(_x) BIT(4 + (_x))
123#define AR934X_NFC_INT_CMD_END BIT(1)
124
125/* default timing values */
126#define AR934X_NFC_TIME_SEQ_DEFAULT 0x7fff
127#define AR934X_NFC_TIMINGS_ASYN_DEFAULT 0x22
128#define AR934X_NFC_TIMINGS_SYN_DEFAULT 0xf
129
130#define AR934X_NFC_ID_BUF_SIZE 8
131#define AR934X_NFC_DEV_READY_TIMEOUT 25 /* msecs */
132#define AR934X_NFC_DMA_READY_TIMEOUT 25 /* msecs */
133#define AR934X_NFC_DONE_TIMEOUT 1000
134#define AR934X_NFC_DMA_RETRIES 20
135
136#define AR934X_NFC_USE_IRQ true
137#define AR934X_NFC_IRQ_MASK AR934X_NFC_INT_DEV_RDY(0)
138
139#define AR934X_NFC_GENSEQ_SMALL_PAGE_READ 0x30043
140
141#undef AR934X_NFC_DEBUG_DATA
142#undef AR934X_NFC_DEBUG
143
144struct ar934x_nfc;
145
146static inline __attribute__ ((format (printf, 2, 3)))
147void _nfc_dbg(struct ar934x_nfc *nfc, const char *fmt, ...)
148{
149}
150
151#ifdef AR934X_NFC_DEBUG
152#define nfc_dbg(_nfc, fmt, ...) \
153    dev_info((_nfc)->parent, fmt, ##__VA_ARGS__)
154#else
155#define nfc_dbg(_nfc, fmt, ...) \
156    _nfc_dbg((_nfc), fmt, ##__VA_ARGS__)
157#endif /* AR934X_NFC_DEBUG */
158
159#ifdef AR934X_NFC_DEBUG_DATA
160static void
161nfc_debug_data(const char *label, void *data, int len)
162{
163    print_hex_dump(KERN_WARNING, label, DUMP_PREFIX_OFFSET, 16, 1,
164               data, len, 0);
165}
166#else
167static inline void
168nfc_debug_data(const char *label, void *data, int len) {}
169#endif /* AR934X_NFC_DEBUG_DATA */
170
171struct ar934x_nfc {
172    struct mtd_info mtd;
173    struct nand_chip nand_chip;
174    struct device *parent;
175    void __iomem *base;
176    void (*select_chip)(int chip_no);
177    bool swap_dma;
178    int irq;
179    wait_queue_head_t irq_waitq;
180
181    bool spurious_irq_expected;
182    u32 irq_status;
183
184    u32 ctrl_reg;
185    bool small_page;
186    unsigned int addr_count0;
187    unsigned int addr_count1;
188
189    u8 *buf;
190    dma_addr_t buf_dma;
191    unsigned int buf_size;
192    int buf_index;
193
194    bool read_id;
195
196    int erase1_page_addr;
197
198    int rndout_page_addr;
199    int rndout_read_cmd;
200
201    int seqin_page_addr;
202    int seqin_column;
203    int seqin_read_cmd;
204};
205
206static void ar934x_nfc_restart(struct ar934x_nfc *nfc);
207
208static inline void
209ar934x_nfc_wr(struct ar934x_nfc *nfc, unsigned reg, u32 val)
210{
211    __raw_writel(val, nfc->base + reg);
212}
213
214static inline u32
215ar934x_nfc_rr(struct ar934x_nfc *nfc, unsigned reg)
216{
217    return __raw_readl(nfc->base + reg);
218}
219
220static inline struct ar934x_nfc_platform_data *
221ar934x_nfc_get_platform_data(struct ar934x_nfc *nfc)
222{
223    return nfc->parent->platform_data;
224}
225
226static inline struct
227ar934x_nfc *mtd_to_ar934x_nfc(struct mtd_info *mtd)
228{
229    return container_of(mtd, struct ar934x_nfc, mtd);
230}
231
232static inline bool ar934x_nfc_use_irq(struct ar934x_nfc *nfc)
233{
234    return AR934X_NFC_USE_IRQ;
235}
236
237static inline void ar934x_nfc_write_cmd_reg(struct ar934x_nfc *nfc, u32 cmd_reg)
238{
239    wmb();
240
241    ar934x_nfc_wr(nfc, AR934X_NFC_REG_CMD, cmd_reg);
242    /* flush write */
243    ar934x_nfc_rr(nfc, AR934X_NFC_REG_CMD);
244}
245
246static bool
247__ar934x_nfc_dev_ready(struct ar934x_nfc *nfc)
248{
249    u32 status;
250
251    status = ar934x_nfc_rr(nfc, AR934X_NFC_REG_STATUS);
252    return (status & 0xff) == 0xff;
253}
254
255static inline bool
256__ar934x_nfc_is_dma_ready(struct ar934x_nfc *nfc)
257{
258    u32 status;
259
260    status = ar934x_nfc_rr(nfc, AR934X_NFC_REG_DMA_CTRL);
261    return (status & AR934X_NFC_DMA_CTRL_DMA_READY) != 0;
262}
263
264static int
265ar934x_nfc_wait_dev_ready(struct ar934x_nfc *nfc)
266{
267    unsigned long timeout;
268
269    timeout = jiffies + msecs_to_jiffies(AR934X_NFC_DEV_READY_TIMEOUT);
270    do {
271        if (__ar934x_nfc_dev_ready(nfc))
272            return 0;
273    } while time_before(jiffies, timeout);
274
275    nfc_dbg(nfc, "timeout waiting for device ready, status:%08x int:%08x\n",
276        ar934x_nfc_rr(nfc, AR934X_NFC_REG_STATUS),
277        ar934x_nfc_rr(nfc, AR934X_NFC_REG_INT_STATUS));
278    return -ETIMEDOUT;
279}
280
281static int
282ar934x_nfc_wait_dma_ready(struct ar934x_nfc *nfc)
283{
284    unsigned long timeout;
285
286    timeout = jiffies + msecs_to_jiffies(AR934X_NFC_DMA_READY_TIMEOUT);
287    do {
288        if (__ar934x_nfc_is_dma_ready(nfc))
289            return 0;
290    } while time_before(jiffies, timeout);
291
292    nfc_dbg(nfc, "timeout waiting for DMA ready, dma_ctrl:%08x\n",
293        ar934x_nfc_rr(nfc, AR934X_NFC_REG_DMA_CTRL));
294    return -ETIMEDOUT;
295}
296
297static int
298ar934x_nfc_wait_irq(struct ar934x_nfc *nfc)
299{
300    long timeout;
301    int ret;
302
303    timeout = wait_event_timeout(nfc->irq_waitq,
304                (nfc->irq_status & AR934X_NFC_IRQ_MASK) != 0,
305                msecs_to_jiffies(AR934X_NFC_DEV_READY_TIMEOUT));
306
307    ret = 0;
308    if (!timeout) {
309        ar934x_nfc_wr(nfc, AR934X_NFC_REG_INT_MASK, 0);
310        ar934x_nfc_wr(nfc, AR934X_NFC_REG_INT_STATUS, 0);
311        /* flush write */
312        ar934x_nfc_rr(nfc, AR934X_NFC_REG_INT_STATUS);
313
314        nfc_dbg(nfc,
315            "timeout waiting for interrupt, status:%08x\n",
316            nfc->irq_status);
317        ret = -ETIMEDOUT;
318    }
319
320    nfc->irq_status = 0;
321    return ret;
322}
323
324static int
325ar934x_nfc_wait_done(struct ar934x_nfc *nfc)
326{
327    int ret;
328
329    if (ar934x_nfc_use_irq(nfc))
330        ret = ar934x_nfc_wait_irq(nfc);
331    else
332        ret = ar934x_nfc_wait_dev_ready(nfc);
333
334    if (ret)
335        return ret;
336
337    return ar934x_nfc_wait_dma_ready(nfc);
338}
339
340static int
341ar934x_nfc_alloc_buf(struct ar934x_nfc *nfc, unsigned size)
342{
343    nfc->buf = dma_alloc_coherent(nfc->parent, size,
344                      &nfc->buf_dma, GFP_KERNEL);
345    if (nfc->buf == NULL) {
346        dev_err(nfc->parent, "no memory for DMA buffer\n");
347        return -ENOMEM;
348    }
349
350    nfc->buf_size = size;
351    nfc_dbg(nfc, "buf:%p size:%u\n", nfc->buf, nfc->buf_size);
352
353    return 0;
354}
355
356static void
357ar934x_nfc_free_buf(struct ar934x_nfc *nfc)
358{
359    dma_free_coherent(nfc->parent, nfc->buf_size, nfc->buf, nfc->buf_dma);
360}
361
362static void
363ar934x_nfc_get_addr(struct ar934x_nfc *nfc, int column, int page_addr,
364            u32 *addr0, u32 *addr1)
365{
366    u32 a0, a1;
367
368    a0 = 0;
369    a1 = 0;
370
371    if (column == -1) {
372        /* ERASE1 */
373        a0 = (page_addr & 0xffff) << 16;
374        a1 = (page_addr >> 16) & 0xf;
375    } else if (page_addr != -1) {
376        /* SEQIN, READ0, etc.. */
377
378        /* TODO: handle 16bit bus width */
379        if (nfc->small_page) {
380            a0 = column & 0xff;
381            a0 |= (page_addr & 0xff) << 8;
382            a0 |= ((page_addr >> 8) & 0xff) << 16;
383            a0 |= ((page_addr >> 16) & 0xff) << 24;
384        } else {
385            a0 = column & 0x0FFF;
386            a0 |= (page_addr & 0xffff) << 16;
387
388            if (nfc->addr_count0 > 4)
389                a1 = (page_addr >> 16) & 0xf;
390        }
391    }
392
393    *addr0 = a0;
394    *addr1 = a1;
395}
396
397static void
398ar934x_nfc_send_cmd(struct ar934x_nfc *nfc, unsigned command)
399{
400    u32 cmd_reg;
401
402    cmd_reg = AR934X_NFC_CMD_INPUT_SEL_SIU | AR934X_NFC_CMD_ADDR_SEL_0 |
403          AR934X_NFC_CMD_SEQ_1C;
404    cmd_reg |= (command & AR934X_NFC_CMD_CMD0_M) << AR934X_NFC_CMD_CMD0_S;
405
406    ar934x_nfc_wr(nfc, AR934X_NFC_REG_INT_STATUS, 0);
407    ar934x_nfc_wr(nfc, AR934X_NFC_REG_CTRL, nfc->ctrl_reg);
408
409    ar934x_nfc_write_cmd_reg(nfc, cmd_reg);
410    ar934x_nfc_wait_dev_ready(nfc);
411}
412
413static void
414ar934x_nfc_do_rw_command(struct ar934x_nfc *nfc, int column, int page_addr,
415             int len, u32 cmd_reg, u32 ctrl_reg, bool write)
416{
417    u32 addr0, addr1;
418    u32 dma_ctrl;
419    int dir;
420    int err;
421    int retries = 0;
422
423    WARN_ON(len & 3);
424
425    if (WARN_ON(len > nfc->buf_size))
426        dev_err(nfc->parent, "len=%d > buf_size=%d", len, nfc->buf_size);
427
428    if (write) {
429        dma_ctrl = AR934X_NFC_DMA_CTRL_DMA_DIR_WRITE;
430        dir = DMA_TO_DEVICE;
431    } else {
432        dma_ctrl = AR934X_NFC_DMA_CTRL_DMA_DIR_READ;
433        dir = DMA_FROM_DEVICE;
434    }
435
436    ar934x_nfc_get_addr(nfc, column, page_addr, &addr0, &addr1);
437
438    dma_ctrl |= AR934X_NFC_DMA_CTRL_DMA_START |
439            (AR934X_NFC_DMA_CTRL_DMA_BURST_3 <<
440             AR934X_NFC_DMA_CTRL_DMA_BURST_S);
441
442    cmd_reg |= AR934X_NFC_CMD_INPUT_SEL_DMA | AR934X_NFC_CMD_ADDR_SEL_0;
443    ctrl_reg |= AR934X_NFC_CTRL_INT_EN;
444
445    nfc_dbg(nfc, "%s a0:%08x a1:%08x len:%x cmd:%08x dma:%08x ctrl:%08x\n",
446        (write) ? "write" : "read",
447        addr0, addr1, len, cmd_reg, dma_ctrl, ctrl_reg);
448
449retry:
450    ar934x_nfc_wr(nfc, AR934X_NFC_REG_INT_STATUS, 0);
451    ar934x_nfc_wr(nfc, AR934X_NFC_REG_ADDR0_0, addr0);
452    ar934x_nfc_wr(nfc, AR934X_NFC_REG_ADDR0_1, addr1);
453    ar934x_nfc_wr(nfc, AR934X_NFC_REG_DMA_ADDR, nfc->buf_dma);
454    ar934x_nfc_wr(nfc, AR934X_NFC_REG_DMA_COUNT, len);
455    ar934x_nfc_wr(nfc, AR934X_NFC_REG_DATA_SIZE, len);
456    ar934x_nfc_wr(nfc, AR934X_NFC_REG_CTRL, ctrl_reg);
457    ar934x_nfc_wr(nfc, AR934X_NFC_REG_DMA_CTRL, dma_ctrl);
458
459    if (ar934x_nfc_use_irq(nfc)) {
460        ar934x_nfc_wr(nfc, AR934X_NFC_REG_INT_MASK, AR934X_NFC_IRQ_MASK);
461        /* flush write */
462        ar934x_nfc_rr(nfc, AR934X_NFC_REG_INT_MASK);
463    }
464
465    ar934x_nfc_write_cmd_reg(nfc, cmd_reg);
466    err = ar934x_nfc_wait_done(nfc);
467    if (err) {
468        dev_dbg(nfc->parent, "%s operation stuck at page %d\n",
469            (write) ? "write" : "read", page_addr);
470
471        ar934x_nfc_restart(nfc);
472        if (retries++ < AR934X_NFC_DMA_RETRIES)
473            goto retry;
474
475        dev_err(nfc->parent, "%s operation failed on page %d\n",
476            (write) ? "write" : "read", page_addr);
477    }
478}
479
480static void
481ar934x_nfc_send_readid(struct ar934x_nfc *nfc, unsigned command)
482{
483    u32 cmd_reg;
484
485    nfc_dbg(nfc, "readid, cmd:%02x\n", command);
486
487    cmd_reg = AR934X_NFC_CMD_SEQ_1C1AXR;
488    cmd_reg |= (command & AR934X_NFC_CMD_CMD0_M) << AR934X_NFC_CMD_CMD0_S;
489
490    ar934x_nfc_do_rw_command(nfc, -1, -1, AR934X_NFC_ID_BUF_SIZE, cmd_reg,
491                 nfc->ctrl_reg, false);
492
493    nfc_debug_data("[id] ", nfc->buf, AR934X_NFC_ID_BUF_SIZE);
494}
495
496static void
497ar934x_nfc_send_read(struct ar934x_nfc *nfc, unsigned command, int column,
498             int page_addr, int len)
499{
500    u32 cmd_reg;
501
502    nfc_dbg(nfc, "read, column=%d page=%d len=%d\n",
503        column, page_addr, len);
504
505    cmd_reg = (command & AR934X_NFC_CMD_CMD0_M) << AR934X_NFC_CMD_CMD0_S;
506
507    if (nfc->small_page) {
508        cmd_reg |= AR934X_NFC_CMD_SEQ_18;
509    } else {
510        cmd_reg |= NAND_CMD_READSTART << AR934X_NFC_CMD_CMD1_S;
511        cmd_reg |= AR934X_NFC_CMD_SEQ_1C5A1CXR;
512    }
513
514    ar934x_nfc_do_rw_command(nfc, column, page_addr, len,
515                 cmd_reg, nfc->ctrl_reg, false);
516
517    nfc_debug_data("[data] ", nfc->buf, len);
518}
519
520static void
521ar934x_nfc_send_erase(struct ar934x_nfc *nfc, unsigned command, int column,
522              int page_addr)
523{
524    u32 addr0, addr1;
525    u32 ctrl_reg;
526    u32 cmd_reg;
527
528    ar934x_nfc_get_addr(nfc, column, page_addr, &addr0, &addr1);
529
530    ctrl_reg = nfc->ctrl_reg;
531    if (nfc->small_page) {
532        /* override number of address cycles for the erase command */
533        ctrl_reg &= ~(AR934X_NFC_CTRL_ADDR_CYCLE0_M <<
534                  AR934X_NFC_CTRL_ADDR_CYCLE0_S);
535        ctrl_reg &= ~(AR934X_NFC_CTRL_ADDR_CYCLE1_M <<
536                  AR934X_NFC_CTRL_ADDR_CYCLE1_S);
537        ctrl_reg &= ~(AR934X_NFC_CTRL_SMALL_PAGE);
538        ctrl_reg |= (nfc->addr_count0 + 1) <<
539                AR934X_NFC_CTRL_ADDR_CYCLE0_S;
540    }
541
542    cmd_reg = NAND_CMD_ERASE1 << AR934X_NFC_CMD_CMD0_S;
543    cmd_reg |= command << AR934X_NFC_CMD_CMD1_S;
544    cmd_reg |= AR934X_NFC_CMD_SEQ_ERASE;
545
546    nfc_dbg(nfc, "erase page %d, a0:%08x a1:%08x cmd:%08x ctrl:%08x\n",
547        page_addr, addr0, addr1, cmd_reg, ctrl_reg);
548
549    ar934x_nfc_wr(nfc, AR934X_NFC_REG_INT_STATUS, 0);
550    ar934x_nfc_wr(nfc, AR934X_NFC_REG_CTRL, ctrl_reg);
551    ar934x_nfc_wr(nfc, AR934X_NFC_REG_ADDR0_0, addr0);
552    ar934x_nfc_wr(nfc, AR934X_NFC_REG_ADDR0_1, addr1);
553
554    ar934x_nfc_write_cmd_reg(nfc, cmd_reg);
555    ar934x_nfc_wait_dev_ready(nfc);
556}
557
558static void
559ar934x_nfc_send_write(struct ar934x_nfc *nfc, unsigned command, int column,
560             int page_addr, int len)
561{
562    u32 cmd_reg;
563
564    nfc_dbg(nfc, "write, column=%d page=%d len=%d\n",
565        column, page_addr, len);
566
567    nfc_debug_data("[data] ", nfc->buf, len);
568
569    cmd_reg = NAND_CMD_SEQIN << AR934X_NFC_CMD_CMD0_S;
570    cmd_reg |= command << AR934X_NFC_CMD_CMD1_S;
571    cmd_reg |= AR934X_NFC_CMD_SEQ_12;
572
573    ar934x_nfc_do_rw_command(nfc, column, page_addr, len,
574                 cmd_reg, nfc->ctrl_reg, true);
575}
576
577static void
578ar934x_nfc_read_status(struct ar934x_nfc *nfc)
579{
580    u32 cmd_reg;
581    u32 status;
582
583    cmd_reg = NAND_CMD_STATUS << AR934X_NFC_CMD_CMD0_S;
584    cmd_reg |= AR934X_NFC_CMD_SEQ_S;
585
586    ar934x_nfc_wr(nfc, AR934X_NFC_REG_INT_STATUS, 0);
587    ar934x_nfc_wr(nfc, AR934X_NFC_REG_CTRL, nfc->ctrl_reg);
588
589    ar934x_nfc_write_cmd_reg(nfc, cmd_reg);
590    ar934x_nfc_wait_dev_ready(nfc);
591
592    status = ar934x_nfc_rr(nfc, AR934X_NFC_REG_READ_STATUS);
593
594    nfc_dbg(nfc, "read status, cmd:%08x status:%02x\n",
595        cmd_reg, (status & 0xff));
596
597    if (nfc->swap_dma)
598        nfc->buf[0 ^ 3] = status;
599    else
600        nfc->buf[0] = status;
601}
602
603static void
604ar934x_nfc_cmdfunc(struct mtd_info *mtd, unsigned int command, int column,
605           int page_addr)
606{
607    struct ar934x_nfc *nfc = mtd_to_ar934x_nfc(mtd);
608
609    nfc->read_id = false;
610    if (command != NAND_CMD_PAGEPROG)
611        nfc->buf_index = 0;
612
613    switch (command) {
614    case NAND_CMD_RESET:
615        ar934x_nfc_send_cmd(nfc, command);
616        break;
617
618    case NAND_CMD_READID:
619        nfc->read_id = true;
620        ar934x_nfc_send_readid(nfc, command);
621        break;
622
623    case NAND_CMD_READ0:
624    case NAND_CMD_READ1:
625        if (nfc->small_page) {
626            ar934x_nfc_send_read(nfc, command, column, page_addr,
627                         mtd->writesize + mtd->oobsize);
628        } else {
629            ar934x_nfc_send_read(nfc, command, 0, page_addr,
630                         mtd->writesize + mtd->oobsize);
631            nfc->buf_index = column;
632            nfc->rndout_page_addr = page_addr;
633            nfc->rndout_read_cmd = command;
634        }
635        break;
636
637    case NAND_CMD_READOOB:
638        if (nfc->small_page)
639            ar934x_nfc_send_read(nfc, NAND_CMD_READOOB,
640                         column, page_addr,
641                         mtd->oobsize);
642        else
643            ar934x_nfc_send_read(nfc, NAND_CMD_READ0,
644                         mtd->writesize, page_addr,
645                         mtd->oobsize);
646        break;
647
648    case NAND_CMD_RNDOUT:
649        if (WARN_ON(nfc->small_page))
650            break;
651
652        /* emulate subpage read */
653        ar934x_nfc_send_read(nfc, nfc->rndout_read_cmd, 0,
654                     nfc->rndout_page_addr,
655                     mtd->writesize + mtd->oobsize);
656        nfc->buf_index = column;
657        break;
658
659    case NAND_CMD_ERASE1:
660        nfc->erase1_page_addr = page_addr;
661        break;
662
663    case NAND_CMD_ERASE2:
664        ar934x_nfc_send_erase(nfc, command, -1, nfc->erase1_page_addr);
665        break;
666
667    case NAND_CMD_STATUS:
668        ar934x_nfc_read_status(nfc);
669        break;
670
671    case NAND_CMD_SEQIN:
672        if (nfc->small_page) {
673            /* output read command */
674            if (column >= mtd->writesize) {
675                column -= mtd->writesize;
676                nfc->seqin_read_cmd = NAND_CMD_READOOB;
677            } else if (column < 256) {
678                nfc->seqin_read_cmd = NAND_CMD_READ0;
679            } else {
680                column -= 256;
681                nfc->seqin_read_cmd = NAND_CMD_READ1;
682            }
683        } else {
684            nfc->seqin_read_cmd = NAND_CMD_READ0;
685        }
686        nfc->seqin_column = column;
687        nfc->seqin_page_addr = page_addr;
688        break;
689
690    case NAND_CMD_PAGEPROG:
691        if (nfc->small_page)
692            ar934x_nfc_send_cmd(nfc, nfc->seqin_read_cmd);
693
694        ar934x_nfc_send_write(nfc, command, nfc->seqin_column,
695                      nfc->seqin_page_addr,
696                      nfc->buf_index);
697        break;
698
699    default:
700        dev_err(nfc->parent,
701            "unsupported command: %x, column:%d page_addr=%d\n",
702            command, column, page_addr);
703        break;
704    }
705}
706
707static int
708ar934x_nfc_dev_ready(struct mtd_info *mtd)
709{
710    struct ar934x_nfc *nfc = mtd_to_ar934x_nfc(mtd);
711
712    return __ar934x_nfc_dev_ready(nfc);
713}
714
715static void
716ar934x_nfc_select_chip(struct mtd_info *mtd, int chip_no)
717{
718    struct ar934x_nfc *nfc = mtd_to_ar934x_nfc(mtd);
719
720    if (nfc->select_chip)
721        nfc->select_chip(chip_no);
722}
723
724static u8
725ar934x_nfc_read_byte(struct mtd_info *mtd)
726{
727    struct ar934x_nfc *nfc = mtd_to_ar934x_nfc(mtd);
728    u8 data;
729
730    WARN_ON(nfc->buf_index >= nfc->buf_size);
731
732    if (nfc->swap_dma || nfc->read_id)
733        data = nfc->buf[nfc->buf_index ^ 3];
734    else
735        data = nfc->buf[nfc->buf_index];
736
737    nfc->buf_index++;
738
739    return data;
740}
741
742static void
743ar934x_nfc_write_buf(struct mtd_info *mtd, const u8 *buf, int len)
744{
745    struct ar934x_nfc *nfc = mtd_to_ar934x_nfc(mtd);
746    int i;
747
748    WARN_ON(nfc->buf_index + len > nfc->buf_size);
749
750    if (nfc->swap_dma) {
751        for (i = 0; i < len; i++) {
752            nfc->buf[nfc->buf_index ^ 3] = buf[i];
753            nfc->buf_index++;
754        }
755    } else {
756        for (i = 0; i < len; i++) {
757            nfc->buf[nfc->buf_index] = buf[i];
758            nfc->buf_index++;
759        }
760    }
761}
762
763static void
764ar934x_nfc_read_buf(struct mtd_info *mtd, u8 *buf, int len)
765{
766    struct ar934x_nfc *nfc = mtd_to_ar934x_nfc(mtd);
767    int buf_index;
768    int i;
769
770    WARN_ON(nfc->buf_index + len > nfc->buf_size);
771
772    buf_index = nfc->buf_index;
773
774    if (nfc->swap_dma || nfc->read_id) {
775        for (i = 0; i < len; i++) {
776            buf[i] = nfc->buf[buf_index ^ 3];
777            buf_index++;
778        }
779    } else {
780        for (i = 0; i < len; i++) {
781            buf[i] = nfc->buf[buf_index];
782            buf_index++;
783        }
784    }
785
786    nfc->buf_index = buf_index;
787}
788
789static void
790ar934x_nfc_hw_init(struct ar934x_nfc *nfc)
791{
792    struct ar934x_nfc_platform_data *pdata;
793
794    pdata = ar934x_nfc_get_platform_data(nfc);
795    if (pdata->hw_reset) {
796        pdata->hw_reset(true);
797        pdata->hw_reset(false);
798    }
799
800    /*
801     * setup timings
802     * TODO: make it configurable via platform data
803     */
804    ar934x_nfc_wr(nfc, AR934X_NFC_REG_TIME_SEQ,
805              AR934X_NFC_TIME_SEQ_DEFAULT);
806    ar934x_nfc_wr(nfc, AR934X_NFC_REG_TIMINGS_ASYN,
807              AR934X_NFC_TIMINGS_ASYN_DEFAULT);
808    ar934x_nfc_wr(nfc, AR934X_NFC_REG_TIMINGS_SYN,
809              AR934X_NFC_TIMINGS_SYN_DEFAULT);
810
811    /* disable WP on all chips, and select chip 0 */
812    ar934x_nfc_wr(nfc, AR934X_NFC_REG_MEM_CTRL, 0xff00);
813
814    ar934x_nfc_wr(nfc, AR934X_NFC_REG_DMA_ADDR_OFFS, 0);
815
816    /* initialize Control register */
817    nfc->ctrl_reg = AR934X_NFC_CTRL_CUSTOM_SIZE_EN;
818    ar934x_nfc_wr(nfc, AR934X_NFC_REG_CTRL, nfc->ctrl_reg);
819
820    if (nfc->small_page) {
821        /* Setup generic sequence register for small page reads. */
822        ar934x_nfc_wr(nfc, AR934X_NFC_REG_GEN_SEQ_CTRL,
823                  AR934X_NFC_GENSEQ_SMALL_PAGE_READ);
824    }
825}
826
827static void
828ar934x_nfc_restart(struct ar934x_nfc *nfc)
829{
830    u32 ctrl_reg;
831
832    if (nfc->select_chip)
833        nfc->select_chip(-1);
834
835    ctrl_reg = nfc->ctrl_reg;
836    ar934x_nfc_hw_init(nfc);
837    nfc->ctrl_reg = ctrl_reg;
838
839    if (nfc->select_chip)
840        nfc->select_chip(0);
841
842    ar934x_nfc_send_cmd(nfc, NAND_CMD_RESET);
843}
844
845static irqreturn_t
846ar934x_nfc_irq_handler(int irq, void *data)
847{
848    struct ar934x_nfc *nfc = data;
849    u32 status;
850
851    status = ar934x_nfc_rr(nfc, AR934X_NFC_REG_INT_STATUS);
852
853    ar934x_nfc_wr(nfc, AR934X_NFC_REG_INT_STATUS, 0);
854    /* flush write */
855    ar934x_nfc_rr(nfc, AR934X_NFC_REG_INT_STATUS);
856
857    status &= ar934x_nfc_rr(nfc, AR934X_NFC_REG_INT_MASK);
858    if (status) {
859        nfc_dbg(nfc, "got IRQ, status:%08x\n", status);
860
861        nfc->irq_status = status;
862        nfc->spurious_irq_expected = true;
863        wake_up(&nfc->irq_waitq);
864    } else {
865        if (nfc->spurious_irq_expected) {
866            nfc->spurious_irq_expected = false;
867        } else {
868            dev_warn(nfc->parent, "spurious interrupt\n");
869        }
870    }
871
872    return IRQ_HANDLED;
873}
874
875static int __devinit
876ar934x_nfc_init_tail(struct mtd_info *mtd)
877{
878    struct ar934x_nfc *nfc = mtd_to_ar934x_nfc(mtd);
879    struct nand_chip *chip = &nfc->nand_chip;
880    u32 ctrl;
881    u32 t;
882    int err;
883
884    switch (mtd->oobsize) {
885    case 16:
886    case 64:
887    case 128:
888        ar934x_nfc_wr(nfc, AR934X_NFC_REG_SPARE_SIZE, mtd->oobsize);
889        break;
890
891    default:
892        dev_err(nfc->parent, "unsupported OOB size: %d bytes\n",
893            mtd->oobsize);
894        return -ENXIO;
895    }
896
897    ctrl = AR934X_NFC_CTRL_CUSTOM_SIZE_EN;
898
899    switch (mtd->erasesize / mtd->writesize) {
900    case 32:
901        t = AR934X_NFC_CTRL_BLOCK_SIZE_32;
902        break;
903
904    case 64:
905        t = AR934X_NFC_CTRL_BLOCK_SIZE_64;
906        break;
907
908    case 128:
909        t = AR934X_NFC_CTRL_BLOCK_SIZE_128;
910        break;
911
912    case 256:
913        t = AR934X_NFC_CTRL_BLOCK_SIZE_256;
914        break;
915
916    default:
917        dev_err(nfc->parent, "unsupported block size: %u\n",
918            mtd->erasesize / mtd->writesize);
919        return -ENXIO;
920    }
921
922    ctrl |= t << AR934X_NFC_CTRL_BLOCK_SIZE_S;
923
924    switch (mtd->writesize) {
925    case 256:
926        nfc->small_page = 1;
927        t = AR934X_NFC_CTRL_PAGE_SIZE_256;
928        break;
929
930    case 512:
931        nfc->small_page = 1;
932        t = AR934X_NFC_CTRL_PAGE_SIZE_512;
933        break;
934
935    case 1024:
936        t = AR934X_NFC_CTRL_PAGE_SIZE_1024;
937        break;
938
939    case 2048:
940        t = AR934X_NFC_CTRL_PAGE_SIZE_2048;
941        break;
942
943    case 4096:
944        t = AR934X_NFC_CTRL_PAGE_SIZE_4096;
945        break;
946
947    case 8192:
948        t = AR934X_NFC_CTRL_PAGE_SIZE_8192;
949        break;
950
951    case 16384:
952        t = AR934X_NFC_CTRL_PAGE_SIZE_16384;
953        break;
954
955    default:
956        dev_err(nfc->parent, "unsupported write size: %d bytes\n",
957            mtd->writesize);
958        return -ENXIO;
959    }
960
961    ctrl |= t << AR934X_NFC_CTRL_PAGE_SIZE_S;
962
963    if (nfc->small_page) {
964        ctrl |= AR934X_NFC_CTRL_SMALL_PAGE;
965
966        if (chip->chipsize > (32 << 20)) {
967            nfc->addr_count0 = 4;
968            nfc->addr_count1 = 3;
969        } else if (chip->chipsize > (2 << 16)) {
970            nfc->addr_count0 = 3;
971            nfc->addr_count1 = 2;
972        } else {
973            nfc->addr_count0 = 2;
974            nfc->addr_count1 = 1;
975        }
976    } else {
977        if (chip->chipsize > (128 << 20)) {
978            nfc->addr_count0 = 5;
979            nfc->addr_count1 = 3;
980        } else if (chip->chipsize > (8 << 16)) {
981            nfc->addr_count0 = 4;
982            nfc->addr_count1 = 2;
983        } else {
984            nfc->addr_count0 = 3;
985            nfc->addr_count1 = 1;
986        }
987    }
988
989    ctrl |= nfc->addr_count0 << AR934X_NFC_CTRL_ADDR_CYCLE0_S;
990    ctrl |= nfc->addr_count1 << AR934X_NFC_CTRL_ADDR_CYCLE1_S;
991
992    nfc->ctrl_reg = ctrl;
993    ar934x_nfc_wr(nfc, AR934X_NFC_REG_CTRL, nfc->ctrl_reg);
994
995    ar934x_nfc_free_buf(nfc);
996    err = ar934x_nfc_alloc_buf(nfc, mtd->writesize + mtd->oobsize);
997
998    return err;
999}
1000
1001static int __devinit
1002ar934x_nfc_probe(struct platform_device *pdev)
1003{
1004    static const char *part_probes[] = { "cmdlinepart", NULL, };
1005    struct ar934x_nfc_platform_data *pdata;
1006    struct ar934x_nfc *nfc;
1007    struct resource *res;
1008    struct mtd_info *mtd;
1009    struct nand_chip *nand;
1010    struct mtd_part_parser_data ppdata;
1011    int ret;
1012
1013    pdata = pdev->dev.platform_data;
1014    if (pdata == NULL) {
1015        dev_err(&pdev->dev, "no platform data defined\n");
1016        return -EINVAL;
1017    }
1018
1019    res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1020    if (!res) {
1021        dev_err(&pdev->dev, "failed to get I/O memory\n");
1022        return -EINVAL;
1023    }
1024
1025    nfc = kzalloc(sizeof(struct ar934x_nfc), GFP_KERNEL);
1026    if (!nfc) {
1027        dev_err(&pdev->dev, "failed to allocate driver data\n");
1028        return -ENOMEM;
1029    }
1030
1031    nfc->base = ioremap(res->start, resource_size(res));
1032    if (nfc->base == NULL) {
1033        dev_err(&pdev->dev, "failed to remap I/O memory\n");
1034        ret = -ENXIO;
1035        goto err_free_nand;
1036    }
1037
1038    nfc->irq = platform_get_irq(pdev, 0);
1039    if (nfc->irq < 0) {
1040        dev_err(&pdev->dev, "no IRQ resource specified\n");
1041        ret = -EINVAL;
1042        goto err_unmap;
1043    }
1044
1045    init_waitqueue_head(&nfc->irq_waitq);
1046    ret = request_irq(nfc->irq, ar934x_nfc_irq_handler, IRQF_DISABLED,
1047              dev_name(&pdev->dev), nfc);
1048    if (ret) {
1049        dev_err(&pdev->dev, "requast_irq failed, err:%d\n", ret);
1050        goto err_unmap;
1051    }
1052
1053    nfc->parent = &pdev->dev;
1054    nfc->select_chip = pdata->select_chip;
1055    nfc->swap_dma = pdata->swap_dma;
1056
1057    nand = &nfc->nand_chip;
1058    mtd = &nfc->mtd;
1059
1060    mtd->priv = nand;
1061    mtd->owner = THIS_MODULE;
1062    if (pdata->name)
1063        mtd->name = pdata->name;
1064    else
1065        mtd->name = dev_name(&pdev->dev);
1066
1067    nand->chip_delay = 25;
1068    nand->ecc.mode = NAND_ECC_SOFT;
1069
1070    nand->dev_ready = ar934x_nfc_dev_ready;
1071    nand->cmdfunc = ar934x_nfc_cmdfunc;
1072    nand->read_byte = ar934x_nfc_read_byte;
1073    nand->write_buf = ar934x_nfc_write_buf;
1074    nand->read_buf = ar934x_nfc_read_buf;
1075    nand->select_chip = ar934x_nfc_select_chip;
1076
1077    ret = ar934x_nfc_alloc_buf(nfc, AR934X_NFC_ID_BUF_SIZE);
1078    if (ret)
1079        goto err_free_irq;
1080
1081    platform_set_drvdata(pdev, nfc);
1082
1083    ar934x_nfc_hw_init(nfc);
1084
1085    ret = nand_scan_ident(mtd, 1, NULL);
1086    if (ret) {
1087        dev_err(&pdev->dev, "nand_scan_ident failed, err:%d\n", ret);
1088        goto err_free_buf;
1089    }
1090
1091    ret = ar934x_nfc_init_tail(mtd);
1092    if (ret) {
1093        dev_err(&pdev->dev, "init tail failed, err:%d\n", ret);
1094        goto err_free_buf;
1095    }
1096
1097    if (pdata->scan_fixup) {
1098        ret = pdata->scan_fixup(mtd);
1099        if (ret)
1100            goto err_free_buf;
1101    }
1102
1103    ret = nand_scan_tail(mtd);
1104    if (ret) {
1105        dev_err(&pdev->dev, "scan tail failed, err:%d\n", ret);
1106        goto err_free_buf;
1107    }
1108
1109    memset(&ppdata, '\0', sizeof(ppdata));
1110    ret = mtd_device_parse_register(mtd, part_probes, &ppdata,
1111                    pdata->parts, pdata->nr_parts);
1112    if (ret) {
1113        dev_err(&pdev->dev, "unable to register mtd, err:%d\n", ret);
1114        goto err_free_buf;
1115    }
1116
1117    return 0;
1118
1119err_free_buf:
1120    ar934x_nfc_free_buf(nfc);
1121err_free_irq:
1122    free_irq(nfc->irq, nfc);
1123err_unmap:
1124    iounmap(nfc->base);
1125err_free_nand:
1126    kfree(nfc);
1127    platform_set_drvdata(pdev, NULL);
1128    return ret;
1129}
1130
1131static int __devexit
1132ar934x_nfc_remove(struct platform_device *pdev)
1133{
1134    struct ar934x_nfc *nfc;
1135
1136    nfc = platform_get_drvdata(pdev);
1137    if (nfc) {
1138        nand_release(&nfc->mtd);
1139        ar934x_nfc_free_buf(nfc);
1140        free_irq(nfc->irq, nfc);
1141        iounmap(nfc->base);
1142        kfree(nfc);
1143    }
1144
1145    return 0;
1146}
1147
1148static struct platform_driver ar934x_nfc_driver = {
1149    .probe = ar934x_nfc_probe,
1150    .remove = __devexit_p(ar934x_nfc_remove),
1151    .driver = {
1152        .name = AR934X_NFC_DRIVER_NAME,
1153        .owner = THIS_MODULE,
1154    },
1155};
1156
1157module_platform_driver(ar934x_nfc_driver);
1158
1159MODULE_LICENSE("GPL v2");
1160MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
1161MODULE_DESCRIPTION("Atheros AR934x NAND Flash Controller driver");
1162MODULE_ALIAS("platform:" AR934X_NFC_DRIVER_NAME);
1163

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