Root/target/linux/ar71xx/files/drivers/net/ethernet/atheros/ag71xx/ag71xx.h

1/*
2 * Atheros AR71xx built-in ethernet mac driver
3 *
4 * Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org>
5 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
6 *
7 * Based on Atheros' AG7100 driver
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License version 2 as published
11 * by the Free Software Foundation.
12 */
13
14#ifndef __AG71XX_H
15#define __AG71XX_H
16
17#include <linux/kernel.h>
18#include <linux/version.h>
19#include <linux/module.h>
20#include <linux/init.h>
21#include <linux/types.h>
22#include <linux/random.h>
23#include <linux/spinlock.h>
24#include <linux/interrupt.h>
25#include <linux/platform_device.h>
26#include <linux/ethtool.h>
27#include <linux/etherdevice.h>
28#include <linux/if_vlan.h>
29#include <linux/phy.h>
30#include <linux/skbuff.h>
31#include <linux/dma-mapping.h>
32#include <linux/workqueue.h>
33
34#include <linux/bitops.h>
35
36#include <asm/mach-ath79/ar71xx_regs.h>
37#include <asm/mach-ath79/ath79.h>
38#include <asm/mach-ath79/ag71xx_platform.h>
39
40#define AG71XX_DRV_NAME "ag71xx"
41#define AG71XX_DRV_VERSION "0.5.35"
42
43#define AG71XX_NAPI_WEIGHT 64
44#define AG71XX_OOM_REFILL (1 + HZ/10)
45
46#define AG71XX_INT_ERR (AG71XX_INT_RX_BE | AG71XX_INT_TX_BE)
47#define AG71XX_INT_TX (AG71XX_INT_TX_PS)
48#define AG71XX_INT_RX (AG71XX_INT_RX_PR | AG71XX_INT_RX_OF)
49
50#define AG71XX_INT_POLL (AG71XX_INT_RX | AG71XX_INT_TX)
51#define AG71XX_INT_INIT (AG71XX_INT_ERR | AG71XX_INT_POLL)
52
53#define AG71XX_TX_MTU_LEN 1540
54#define AG71XX_RX_PKT_SIZE \
55    (ETH_FRAME_LEN + ETH_FCS_LEN + VLAN_HLEN)
56#define AG71XX_RX_BUF_SIZE (AG71XX_RX_PKT_SIZE + NET_SKB_PAD + NET_IP_ALIGN)
57
58#define AG71XX_TX_RING_SIZE_DEFAULT 64
59#define AG71XX_RX_RING_SIZE_DEFAULT 128
60
61#define AG71XX_TX_RING_SIZE_MAX 256
62#define AG71XX_RX_RING_SIZE_MAX 256
63
64#ifdef CONFIG_AG71XX_DEBUG
65#define DBG(fmt, args...) pr_debug(fmt, ## args)
66#else
67#define DBG(fmt, args...) do {} while (0)
68#endif
69
70#define ag71xx_assert(_cond) \
71do { \
72    if (_cond) \
73        break; \
74    printk("%s,%d: assertion failed\n", __FILE__, __LINE__); \
75    BUG(); \
76} while (0)
77
78struct ag71xx_desc {
79    u32 data;
80    u32 ctrl;
81#define DESC_EMPTY BIT(31)
82#define DESC_MORE BIT(24)
83#define DESC_PKTLEN_M 0xfff
84    u32 next;
85    u32 pad;
86} __attribute__((aligned(4)));
87
88struct ag71xx_buf {
89    union {
90        struct sk_buff *skb;
91        void *rx_buf;
92    };
93    struct ag71xx_desc *desc;
94    dma_addr_t dma_addr;
95    unsigned long timestamp;
96};
97
98struct ag71xx_ring {
99    struct ag71xx_buf *buf;
100    u8 *descs_cpu;
101    dma_addr_t descs_dma;
102    unsigned int desc_size;
103    unsigned int curr;
104    unsigned int dirty;
105    unsigned int size;
106};
107
108struct ag71xx_mdio {
109    struct mii_bus *mii_bus;
110    int mii_irq[PHY_MAX_ADDR];
111    void __iomem *mdio_base;
112    struct ag71xx_mdio_platform_data *pdata;
113};
114
115struct ag71xx_int_stats {
116    unsigned long rx_pr;
117    unsigned long rx_be;
118    unsigned long rx_of;
119    unsigned long tx_ps;
120    unsigned long tx_be;
121    unsigned long tx_ur;
122    unsigned long total;
123};
124
125struct ag71xx_napi_stats {
126    unsigned long napi_calls;
127    unsigned long rx_count;
128    unsigned long rx_packets;
129    unsigned long rx_packets_max;
130    unsigned long tx_count;
131    unsigned long tx_packets;
132    unsigned long tx_packets_max;
133
134    unsigned long rx[AG71XX_NAPI_WEIGHT + 1];
135    unsigned long tx[AG71XX_NAPI_WEIGHT + 1];
136};
137
138struct ag71xx_debug {
139    struct dentry *debugfs_dir;
140
141    struct ag71xx_int_stats int_stats;
142    struct ag71xx_napi_stats napi_stats;
143};
144
145struct ag71xx {
146    void __iomem *mac_base;
147
148    spinlock_t lock;
149    struct platform_device *pdev;
150    struct net_device *dev;
151    struct napi_struct napi;
152    u32 msg_enable;
153
154    struct ag71xx_desc *stop_desc;
155    dma_addr_t stop_desc_dma;
156
157    struct ag71xx_ring rx_ring;
158    struct ag71xx_ring tx_ring;
159
160    struct mii_bus *mii_bus;
161    struct phy_device *phy_dev;
162    void *phy_priv;
163
164    unsigned int link;
165    unsigned int speed;
166    int duplex;
167
168    struct work_struct restart_work;
169    struct delayed_work link_work;
170    struct timer_list oom_timer;
171
172#ifdef CONFIG_AG71XX_DEBUG_FS
173    struct ag71xx_debug debug;
174#endif
175};
176
177extern struct ethtool_ops ag71xx_ethtool_ops;
178void ag71xx_link_adjust(struct ag71xx *ag);
179
180int ag71xx_mdio_driver_init(void) __init;
181void ag71xx_mdio_driver_exit(void);
182
183int ag71xx_phy_connect(struct ag71xx *ag);
184void ag71xx_phy_disconnect(struct ag71xx *ag);
185void ag71xx_phy_start(struct ag71xx *ag);
186void ag71xx_phy_stop(struct ag71xx *ag);
187
188static inline struct ag71xx_platform_data *ag71xx_get_pdata(struct ag71xx *ag)
189{
190    return ag->pdev->dev.platform_data;
191}
192
193static inline int ag71xx_desc_empty(struct ag71xx_desc *desc)
194{
195    return (desc->ctrl & DESC_EMPTY) != 0;
196}
197
198static inline int ag71xx_desc_pktlen(struct ag71xx_desc *desc)
199{
200    return desc->ctrl & DESC_PKTLEN_M;
201}
202
203/* Register offsets */
204#define AG71XX_REG_MAC_CFG1 0x0000
205#define AG71XX_REG_MAC_CFG2 0x0004
206#define AG71XX_REG_MAC_IPG 0x0008
207#define AG71XX_REG_MAC_HDX 0x000c
208#define AG71XX_REG_MAC_MFL 0x0010
209#define AG71XX_REG_MII_CFG 0x0020
210#define AG71XX_REG_MII_CMD 0x0024
211#define AG71XX_REG_MII_ADDR 0x0028
212#define AG71XX_REG_MII_CTRL 0x002c
213#define AG71XX_REG_MII_STATUS 0x0030
214#define AG71XX_REG_MII_IND 0x0034
215#define AG71XX_REG_MAC_IFCTL 0x0038
216#define AG71XX_REG_MAC_ADDR1 0x0040
217#define AG71XX_REG_MAC_ADDR2 0x0044
218#define AG71XX_REG_FIFO_CFG0 0x0048
219#define AG71XX_REG_FIFO_CFG1 0x004c
220#define AG71XX_REG_FIFO_CFG2 0x0050
221#define AG71XX_REG_FIFO_CFG3 0x0054
222#define AG71XX_REG_FIFO_CFG4 0x0058
223#define AG71XX_REG_FIFO_CFG5 0x005c
224#define AG71XX_REG_FIFO_RAM0 0x0060
225#define AG71XX_REG_FIFO_RAM1 0x0064
226#define AG71XX_REG_FIFO_RAM2 0x0068
227#define AG71XX_REG_FIFO_RAM3 0x006c
228#define AG71XX_REG_FIFO_RAM4 0x0070
229#define AG71XX_REG_FIFO_RAM5 0x0074
230#define AG71XX_REG_FIFO_RAM6 0x0078
231#define AG71XX_REG_FIFO_RAM7 0x007c
232
233#define AG71XX_REG_TX_CTRL 0x0180
234#define AG71XX_REG_TX_DESC 0x0184
235#define AG71XX_REG_TX_STATUS 0x0188
236#define AG71XX_REG_RX_CTRL 0x018c
237#define AG71XX_REG_RX_DESC 0x0190
238#define AG71XX_REG_RX_STATUS 0x0194
239#define AG71XX_REG_INT_ENABLE 0x0198
240#define AG71XX_REG_INT_STATUS 0x019c
241
242#define AG71XX_REG_FIFO_DEPTH 0x01a8
243#define AG71XX_REG_RX_SM 0x01b0
244#define AG71XX_REG_TX_SM 0x01b4
245
246#define MAC_CFG1_TXE BIT(0) /* Tx Enable */
247#define MAC_CFG1_STX BIT(1) /* Synchronize Tx Enable */
248#define MAC_CFG1_RXE BIT(2) /* Rx Enable */
249#define MAC_CFG1_SRX BIT(3) /* Synchronize Rx Enable */
250#define MAC_CFG1_TFC BIT(4) /* Tx Flow Control Enable */
251#define MAC_CFG1_RFC BIT(5) /* Rx Flow Control Enable */
252#define MAC_CFG1_LB BIT(8) /* Loopback mode */
253#define MAC_CFG1_SR BIT(31) /* Soft Reset */
254
255#define MAC_CFG2_FDX BIT(0)
256#define MAC_CFG2_CRC_EN BIT(1)
257#define MAC_CFG2_PAD_CRC_EN BIT(2)
258#define MAC_CFG2_LEN_CHECK BIT(4)
259#define MAC_CFG2_HUGE_FRAME_EN BIT(5)
260#define MAC_CFG2_IF_1000 BIT(9)
261#define MAC_CFG2_IF_10_100 BIT(8)
262
263#define FIFO_CFG0_WTM BIT(0) /* Watermark Module */
264#define FIFO_CFG0_RXS BIT(1) /* Rx System Module */
265#define FIFO_CFG0_RXF BIT(2) /* Rx Fabric Module */
266#define FIFO_CFG0_TXS BIT(3) /* Tx System Module */
267#define FIFO_CFG0_TXF BIT(4) /* Tx Fabric Module */
268#define FIFO_CFG0_ALL (FIFO_CFG0_WTM | FIFO_CFG0_RXS | FIFO_CFG0_RXF \
269            | FIFO_CFG0_TXS | FIFO_CFG0_TXF)
270
271#define FIFO_CFG0_ENABLE_SHIFT 8
272
273#define FIFO_CFG4_DE BIT(0) /* Drop Event */
274#define FIFO_CFG4_DV BIT(1) /* RX_DV Event */
275#define FIFO_CFG4_FC BIT(2) /* False Carrier */
276#define FIFO_CFG4_CE BIT(3) /* Code Error */
277#define FIFO_CFG4_CR BIT(4) /* CRC error */
278#define FIFO_CFG4_LM BIT(5) /* Length Mismatch */
279#define FIFO_CFG4_LO BIT(6) /* Length out of range */
280#define FIFO_CFG4_OK BIT(7) /* Packet is OK */
281#define FIFO_CFG4_MC BIT(8) /* Multicast Packet */
282#define FIFO_CFG4_BC BIT(9) /* Broadcast Packet */
283#define FIFO_CFG4_DR BIT(10) /* Dribble */
284#define FIFO_CFG4_LE BIT(11) /* Long Event */
285#define FIFO_CFG4_CF BIT(12) /* Control Frame */
286#define FIFO_CFG4_PF BIT(13) /* Pause Frame */
287#define FIFO_CFG4_UO BIT(14) /* Unsupported Opcode */
288#define FIFO_CFG4_VT BIT(15) /* VLAN tag detected */
289#define FIFO_CFG4_FT BIT(16) /* Frame Truncated */
290#define FIFO_CFG4_UC BIT(17) /* Unicast Packet */
291
292#define FIFO_CFG5_DE BIT(0) /* Drop Event */
293#define FIFO_CFG5_DV BIT(1) /* RX_DV Event */
294#define FIFO_CFG5_FC BIT(2) /* False Carrier */
295#define FIFO_CFG5_CE BIT(3) /* Code Error */
296#define FIFO_CFG5_LM BIT(4) /* Length Mismatch */
297#define FIFO_CFG5_LO BIT(5) /* Length Out of Range */
298#define FIFO_CFG5_OK BIT(6) /* Packet is OK */
299#define FIFO_CFG5_MC BIT(7) /* Multicast Packet */
300#define FIFO_CFG5_BC BIT(8) /* Broadcast Packet */
301#define FIFO_CFG5_DR BIT(9) /* Dribble */
302#define FIFO_CFG5_CF BIT(10) /* Control Frame */
303#define FIFO_CFG5_PF BIT(11) /* Pause Frame */
304#define FIFO_CFG5_UO BIT(12) /* Unsupported Opcode */
305#define FIFO_CFG5_VT BIT(13) /* VLAN tag detected */
306#define FIFO_CFG5_LE BIT(14) /* Long Event */
307#define FIFO_CFG5_FT BIT(15) /* Frame Truncated */
308#define FIFO_CFG5_16 BIT(16) /* unknown */
309#define FIFO_CFG5_17 BIT(17) /* unknown */
310#define FIFO_CFG5_SF BIT(18) /* Short Frame */
311#define FIFO_CFG5_BM BIT(19) /* Byte Mode */
312
313#define AG71XX_INT_TX_PS BIT(0)
314#define AG71XX_INT_TX_UR BIT(1)
315#define AG71XX_INT_TX_BE BIT(3)
316#define AG71XX_INT_RX_PR BIT(4)
317#define AG71XX_INT_RX_OF BIT(6)
318#define AG71XX_INT_RX_BE BIT(7)
319
320#define MAC_IFCTL_SPEED BIT(16)
321
322#define MII_CFG_CLK_DIV_4 0
323#define MII_CFG_CLK_DIV_6 2
324#define MII_CFG_CLK_DIV_8 3
325#define MII_CFG_CLK_DIV_10 4
326#define MII_CFG_CLK_DIV_14 5
327#define MII_CFG_CLK_DIV_20 6
328#define MII_CFG_CLK_DIV_28 7
329#define MII_CFG_CLK_DIV_34 8
330#define MII_CFG_CLK_DIV_42 9
331#define MII_CFG_CLK_DIV_50 10
332#define MII_CFG_CLK_DIV_58 11
333#define MII_CFG_CLK_DIV_66 12
334#define MII_CFG_CLK_DIV_74 13
335#define MII_CFG_CLK_DIV_82 14
336#define MII_CFG_CLK_DIV_98 15
337#define MII_CFG_RESET BIT(31)
338
339#define MII_CMD_WRITE 0x0
340#define MII_CMD_READ 0x1
341#define MII_ADDR_SHIFT 8
342#define MII_IND_BUSY BIT(0)
343#define MII_IND_INVALID BIT(2)
344
345#define TX_CTRL_TXE BIT(0) /* Tx Enable */
346
347#define TX_STATUS_PS BIT(0) /* Packet Sent */
348#define TX_STATUS_UR BIT(1) /* Tx Underrun */
349#define TX_STATUS_BE BIT(3) /* Bus Error */
350
351#define RX_CTRL_RXE BIT(0) /* Rx Enable */
352
353#define RX_STATUS_PR BIT(0) /* Packet Received */
354#define RX_STATUS_OF BIT(2) /* Rx Overflow */
355#define RX_STATUS_BE BIT(3) /* Bus Error */
356
357static inline void ag71xx_check_reg_offset(struct ag71xx *ag, unsigned reg)
358{
359    switch (reg) {
360    case AG71XX_REG_MAC_CFG1 ... AG71XX_REG_MAC_MFL:
361    case AG71XX_REG_MAC_IFCTL ... AG71XX_REG_TX_SM:
362    case AG71XX_REG_MII_CFG:
363        break;
364
365    default:
366        BUG();
367    }
368}
369
370static inline void ag71xx_wr(struct ag71xx *ag, unsigned reg, u32 value)
371{
372    ag71xx_check_reg_offset(ag, reg);
373
374    __raw_writel(value, ag->mac_base + reg);
375    /* flush write */
376    (void) __raw_readl(ag->mac_base + reg);
377}
378
379static inline u32 ag71xx_rr(struct ag71xx *ag, unsigned reg)
380{
381    ag71xx_check_reg_offset(ag, reg);
382
383    return __raw_readl(ag->mac_base + reg);
384}
385
386static inline void ag71xx_sb(struct ag71xx *ag, unsigned reg, u32 mask)
387{
388    void __iomem *r;
389
390    ag71xx_check_reg_offset(ag, reg);
391
392    r = ag->mac_base + reg;
393    __raw_writel(__raw_readl(r) | mask, r);
394    /* flush write */
395    (void)__raw_readl(r);
396}
397
398static inline void ag71xx_cb(struct ag71xx *ag, unsigned reg, u32 mask)
399{
400    void __iomem *r;
401
402    ag71xx_check_reg_offset(ag, reg);
403
404    r = ag->mac_base + reg;
405    __raw_writel(__raw_readl(r) & ~mask, r);
406    /* flush write */
407    (void) __raw_readl(r);
408}
409
410static inline void ag71xx_int_enable(struct ag71xx *ag, u32 ints)
411{
412    ag71xx_sb(ag, AG71XX_REG_INT_ENABLE, ints);
413}
414
415static inline void ag71xx_int_disable(struct ag71xx *ag, u32 ints)
416{
417    ag71xx_cb(ag, AG71XX_REG_INT_ENABLE, ints);
418}
419
420#ifdef CONFIG_AG71XX_AR8216_SUPPORT
421void ag71xx_add_ar8216_header(struct ag71xx *ag, struct sk_buff *skb);
422int ag71xx_remove_ar8216_header(struct ag71xx *ag, struct sk_buff *skb,
423                int pktlen);
424static inline int ag71xx_has_ar8216(struct ag71xx *ag)
425{
426    return ag71xx_get_pdata(ag)->has_ar8216;
427}
428#else
429static inline void ag71xx_add_ar8216_header(struct ag71xx *ag,
430                       struct sk_buff *skb)
431{
432}
433
434static inline int ag71xx_remove_ar8216_header(struct ag71xx *ag,
435                          struct sk_buff *skb,
436                          int pktlen)
437{
438    return 0;
439}
440static inline int ag71xx_has_ar8216(struct ag71xx *ag)
441{
442    return 0;
443}
444#endif
445
446#ifdef CONFIG_AG71XX_DEBUG_FS
447int ag71xx_debugfs_root_init(void);
448void ag71xx_debugfs_root_exit(void);
449int ag71xx_debugfs_init(struct ag71xx *ag);
450void ag71xx_debugfs_exit(struct ag71xx *ag);
451void ag71xx_debugfs_update_int_stats(struct ag71xx *ag, u32 status);
452void ag71xx_debugfs_update_napi_stats(struct ag71xx *ag, int rx, int tx);
453#else
454static inline int ag71xx_debugfs_root_init(void) { return 0; }
455static inline void ag71xx_debugfs_root_exit(void) {}
456static inline int ag71xx_debugfs_init(struct ag71xx *ag) { return 0; }
457static inline void ag71xx_debugfs_exit(struct ag71xx *ag) {}
458static inline void ag71xx_debugfs_update_int_stats(struct ag71xx *ag,
459                           u32 status) {}
460static inline void ag71xx_debugfs_update_napi_stats(struct ag71xx *ag,
461                            int rx, int tx) {}
462#endif /* CONFIG_AG71XX_DEBUG_FS */
463
464void ag71xx_ar7240_start(struct ag71xx *ag);
465void ag71xx_ar7240_stop(struct ag71xx *ag);
466int ag71xx_ar7240_init(struct ag71xx *ag);
467void ag71xx_ar7240_cleanup(struct ag71xx *ag);
468
469int ag71xx_mdio_mii_read(struct ag71xx_mdio *am, int addr, int reg);
470void ag71xx_mdio_mii_write(struct ag71xx_mdio *am, int addr, int reg, u16 val);
471
472u16 ar7240sw_phy_read(struct mii_bus *mii, unsigned phy_addr,
473              unsigned reg_addr);
474int ar7240sw_phy_write(struct mii_bus *mii, unsigned phy_addr,
475               unsigned reg_addr, u16 reg_val);
476
477#endif /* _AG71XX_H */
478

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