Root/target/linux/ar71xx/files/drivers/net/ethernet/atheros/ag71xx/ag71xx_ar7240.c

1/*
2 * Driver for the built-in ethernet switch of the Atheros AR7240 SoC
3 * Copyright (c) 2010 Gabor Juhos <juhosg@openwrt.org>
4 * Copyright (c) 2010 Felix Fietkau <nbd@openwrt.org>
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation.
9 *
10 */
11
12#include <linux/etherdevice.h>
13#include <linux/list.h>
14#include <linux/netdevice.h>
15#include <linux/phy.h>
16#include <linux/mii.h>
17#include <linux/bitops.h>
18#include <linux/switch.h>
19#include "ag71xx.h"
20
21#define BITM(_count) (BIT(_count) - 1)
22#define BITS(_shift, _count) (BITM(_count) << _shift)
23
24#define AR7240_REG_MASK_CTRL 0x00
25#define AR7240_MASK_CTRL_REVISION_M BITM(8)
26#define AR7240_MASK_CTRL_VERSION_M BITM(8)
27#define AR7240_MASK_CTRL_VERSION_S 8
28#define AR7240_MASK_CTRL_VERSION_AR7240 0x01
29#define AR7240_MASK_CTRL_VERSION_AR934X 0x02
30#define AR7240_MASK_CTRL_SOFT_RESET BIT(31)
31
32#define AR7240_REG_MAC_ADDR0 0x20
33#define AR7240_REG_MAC_ADDR1 0x24
34
35#define AR7240_REG_FLOOD_MASK 0x2c
36#define AR7240_FLOOD_MASK_BROAD_TO_CPU BIT(26)
37
38#define AR7240_REG_GLOBAL_CTRL 0x30
39#define AR7240_GLOBAL_CTRL_MTU_M BITM(12)
40
41#define AR7240_REG_VTU 0x0040
42#define AR7240_VTU_OP BITM(3)
43#define AR7240_VTU_OP_NOOP 0x0
44#define AR7240_VTU_OP_FLUSH 0x1
45#define AR7240_VTU_OP_LOAD 0x2
46#define AR7240_VTU_OP_PURGE 0x3
47#define AR7240_VTU_OP_REMOVE_PORT 0x4
48#define AR7240_VTU_ACTIVE BIT(3)
49#define AR7240_VTU_FULL BIT(4)
50#define AR7240_VTU_PORT BITS(8, 4)
51#define AR7240_VTU_PORT_S 8
52#define AR7240_VTU_VID BITS(16, 12)
53#define AR7240_VTU_VID_S 16
54#define AR7240_VTU_PRIO BITS(28, 3)
55#define AR7240_VTU_PRIO_S 28
56#define AR7240_VTU_PRIO_EN BIT(31)
57
58#define AR7240_REG_VTU_DATA 0x0044
59#define AR7240_VTUDATA_MEMBER BITS(0, 10)
60#define AR7240_VTUDATA_VALID BIT(11)
61
62#define AR7240_REG_ATU 0x50
63#define AR7240_ATU_FLUSH_ALL 0x1
64
65#define AR7240_REG_AT_CTRL 0x5c
66#define AR7240_AT_CTRL_AGE_TIME BITS(0, 15)
67#define AR7240_AT_CTRL_AGE_EN BIT(17)
68#define AR7240_AT_CTRL_LEARN_CHANGE BIT(18)
69#define AR7240_AT_CTRL_RESERVED BIT(19)
70#define AR7240_AT_CTRL_ARP_EN BIT(20)
71
72#define AR7240_REG_TAG_PRIORITY 0x70
73
74#define AR7240_REG_SERVICE_TAG 0x74
75#define AR7240_SERVICE_TAG_M BITM(16)
76
77#define AR7240_REG_CPU_PORT 0x78
78#define AR7240_MIRROR_PORT_S 4
79#define AR7240_CPU_PORT_EN BIT(8)
80
81#define AR7240_REG_MIB_FUNCTION0 0x80
82#define AR7240_MIB_TIMER_M BITM(16)
83#define AR7240_MIB_AT_HALF_EN BIT(16)
84#define AR7240_MIB_BUSY BIT(17)
85#define AR7240_MIB_FUNC_S 24
86#define AR7240_MIB_FUNC_M BITM(3)
87#define AR7240_MIB_FUNC_NO_OP 0x0
88#define AR7240_MIB_FUNC_FLUSH 0x1
89#define AR7240_MIB_FUNC_CAPTURE 0x3
90
91#define AR7240_REG_MDIO_CTRL 0x98
92#define AR7240_MDIO_CTRL_DATA_M BITM(16)
93#define AR7240_MDIO_CTRL_REG_ADDR_S 16
94#define AR7240_MDIO_CTRL_PHY_ADDR_S 21
95#define AR7240_MDIO_CTRL_CMD_WRITE 0
96#define AR7240_MDIO_CTRL_CMD_READ BIT(27)
97#define AR7240_MDIO_CTRL_MASTER_EN BIT(30)
98#define AR7240_MDIO_CTRL_BUSY BIT(31)
99
100#define AR7240_REG_PORT_BASE(_port) (0x100 + (_port) * 0x100)
101
102#define AR7240_REG_PORT_STATUS(_port) (AR7240_REG_PORT_BASE((_port)) + 0x00)
103#define AR7240_PORT_STATUS_SPEED_S 0
104#define AR7240_PORT_STATUS_SPEED_M BITM(2)
105#define AR7240_PORT_STATUS_SPEED_10 0
106#define AR7240_PORT_STATUS_SPEED_100 1
107#define AR7240_PORT_STATUS_SPEED_1000 2
108#define AR7240_PORT_STATUS_TXMAC BIT(2)
109#define AR7240_PORT_STATUS_RXMAC BIT(3)
110#define AR7240_PORT_STATUS_TXFLOW BIT(4)
111#define AR7240_PORT_STATUS_RXFLOW BIT(5)
112#define AR7240_PORT_STATUS_DUPLEX BIT(6)
113#define AR7240_PORT_STATUS_LINK_UP BIT(8)
114#define AR7240_PORT_STATUS_LINK_AUTO BIT(9)
115#define AR7240_PORT_STATUS_LINK_PAUSE BIT(10)
116
117#define AR7240_REG_PORT_CTRL(_port) (AR7240_REG_PORT_BASE((_port)) + 0x04)
118#define AR7240_PORT_CTRL_STATE_M BITM(3)
119#define AR7240_PORT_CTRL_STATE_DISABLED 0
120#define AR7240_PORT_CTRL_STATE_BLOCK 1
121#define AR7240_PORT_CTRL_STATE_LISTEN 2
122#define AR7240_PORT_CTRL_STATE_LEARN 3
123#define AR7240_PORT_CTRL_STATE_FORWARD 4
124#define AR7240_PORT_CTRL_LEARN_LOCK BIT(7)
125#define AR7240_PORT_CTRL_VLAN_MODE_S 8
126#define AR7240_PORT_CTRL_VLAN_MODE_KEEP 0
127#define AR7240_PORT_CTRL_VLAN_MODE_STRIP 1
128#define AR7240_PORT_CTRL_VLAN_MODE_ADD 2
129#define AR7240_PORT_CTRL_VLAN_MODE_DOUBLE_TAG 3
130#define AR7240_PORT_CTRL_IGMP_SNOOP BIT(10)
131#define AR7240_PORT_CTRL_HEADER BIT(11)
132#define AR7240_PORT_CTRL_MAC_LOOP BIT(12)
133#define AR7240_PORT_CTRL_SINGLE_VLAN BIT(13)
134#define AR7240_PORT_CTRL_LEARN BIT(14)
135#define AR7240_PORT_CTRL_DOUBLE_TAG BIT(15)
136#define AR7240_PORT_CTRL_MIRROR_TX BIT(16)
137#define AR7240_PORT_CTRL_MIRROR_RX BIT(17)
138
139#define AR7240_REG_PORT_VLAN(_port) (AR7240_REG_PORT_BASE((_port)) + 0x08)
140
141#define AR7240_PORT_VLAN_DEFAULT_ID_S 0
142#define AR7240_PORT_VLAN_DEST_PORTS_S 16
143#define AR7240_PORT_VLAN_MODE_S 30
144#define AR7240_PORT_VLAN_MODE_PORT_ONLY 0
145#define AR7240_PORT_VLAN_MODE_PORT_FALLBACK 1
146#define AR7240_PORT_VLAN_MODE_VLAN_ONLY 2
147#define AR7240_PORT_VLAN_MODE_SECURE 3
148
149
150#define AR7240_REG_STATS_BASE(_port) (0x20000 + (_port) * 0x100)
151
152#define AR7240_STATS_RXBROAD 0x00
153#define AR7240_STATS_RXPAUSE 0x04
154#define AR7240_STATS_RXMULTI 0x08
155#define AR7240_STATS_RXFCSERR 0x0c
156#define AR7240_STATS_RXALIGNERR 0x10
157#define AR7240_STATS_RXRUNT 0x14
158#define AR7240_STATS_RXFRAGMENT 0x18
159#define AR7240_STATS_RX64BYTE 0x1c
160#define AR7240_STATS_RX128BYTE 0x20
161#define AR7240_STATS_RX256BYTE 0x24
162#define AR7240_STATS_RX512BYTE 0x28
163#define AR7240_STATS_RX1024BYTE 0x2c
164#define AR7240_STATS_RX1518BYTE 0x30
165#define AR7240_STATS_RXMAXBYTE 0x34
166#define AR7240_STATS_RXTOOLONG 0x38
167#define AR7240_STATS_RXGOODBYTE 0x3c
168#define AR7240_STATS_RXBADBYTE 0x44
169#define AR7240_STATS_RXOVERFLOW 0x4c
170#define AR7240_STATS_FILTERED 0x50
171#define AR7240_STATS_TXBROAD 0x54
172#define AR7240_STATS_TXPAUSE 0x58
173#define AR7240_STATS_TXMULTI 0x5c
174#define AR7240_STATS_TXUNDERRUN 0x60
175#define AR7240_STATS_TX64BYTE 0x64
176#define AR7240_STATS_TX128BYTE 0x68
177#define AR7240_STATS_TX256BYTE 0x6c
178#define AR7240_STATS_TX512BYTE 0x70
179#define AR7240_STATS_TX1024BYTE 0x74
180#define AR7240_STATS_TX1518BYTE 0x78
181#define AR7240_STATS_TXMAXBYTE 0x7c
182#define AR7240_STATS_TXOVERSIZE 0x80
183#define AR7240_STATS_TXBYTE 0x84
184#define AR7240_STATS_TXCOLLISION 0x8c
185#define AR7240_STATS_TXABORTCOL 0x90
186#define AR7240_STATS_TXMULTICOL 0x94
187#define AR7240_STATS_TXSINGLECOL 0x98
188#define AR7240_STATS_TXEXCDEFER 0x9c
189#define AR7240_STATS_TXDEFER 0xa0
190#define AR7240_STATS_TXLATECOL 0xa4
191
192#define AR7240_PORT_CPU 0
193#define AR7240_NUM_PORTS 6
194#define AR7240_NUM_PHYS 5
195
196#define AR7240_PHY_ID1 0x004d
197#define AR7240_PHY_ID2 0xd041
198
199#define AR934X_PHY_ID1 0x004d
200#define AR934X_PHY_ID2 0xd042
201
202#define AR7240_MAX_VLANS 16
203
204#define AR934X_REG_OPER_MODE0 0x04
205#define AR934X_OPER_MODE0_MAC_GMII_EN BIT(6)
206#define AR934X_OPER_MODE0_PHY_MII_EN BIT(10)
207
208#define AR934X_REG_OPER_MODE1 0x08
209#define AR934X_REG_OPER_MODE1_PHY4_MII_EN BIT(28)
210
211#define AR934X_REG_FLOOD_MASK 0x2c
212#define AR934X_FLOOD_MASK_BC_DP(_p) BIT(25 + (_p))
213
214#define AR934X_REG_QM_CTRL 0x3c
215#define AR934X_QM_CTRL_ARP_EN BIT(15)
216
217#define AR934X_REG_AT_CTRL 0x5c
218#define AR934X_AT_CTRL_AGE_TIME BITS(0, 15)
219#define AR934X_AT_CTRL_AGE_EN BIT(17)
220#define AR934X_AT_CTRL_LEARN_CHANGE BIT(18)
221
222#define AR934X_MIB_ENABLE BIT(30)
223
224#define AR934X_REG_PORT_BASE(_port) (0x100 + (_port) * 0x100)
225
226#define AR934X_REG_PORT_VLAN1(_port) (AR934X_REG_PORT_BASE((_port)) + 0x08)
227#define AR934X_PORT_VLAN1_DEFAULT_SVID_S 0
228#define AR934X_PORT_VLAN1_FORCE_DEFAULT_VID_EN BIT(12)
229#define AR934X_PORT_VLAN1_PORT_TLS_MODE BIT(13)
230#define AR934X_PORT_VLAN1_PORT_VLAN_PROP_EN BIT(14)
231#define AR934X_PORT_VLAN1_PORT_CLONE_EN BIT(15)
232#define AR934X_PORT_VLAN1_DEFAULT_CVID_S 16
233#define AR934X_PORT_VLAN1_FORCE_PORT_VLAN_EN BIT(28)
234#define AR934X_PORT_VLAN1_ING_PORT_PRI_S 29
235
236#define AR934X_REG_PORT_VLAN2(_port) (AR934X_REG_PORT_BASE((_port)) + 0x0c)
237#define AR934X_PORT_VLAN2_PORT_VID_MEM_S 16
238#define AR934X_PORT_VLAN2_8021Q_MODE_S 30
239#define AR934X_PORT_VLAN2_8021Q_MODE_PORT_ONLY 0
240#define AR934X_PORT_VLAN2_8021Q_MODE_PORT_FALLBACK 1
241#define AR934X_PORT_VLAN2_8021Q_MODE_VLAN_ONLY 2
242#define AR934X_PORT_VLAN2_8021Q_MODE_SECURE 3
243
244#define sw_to_ar7240(_dev) container_of(_dev, struct ar7240sw, swdev)
245
246struct ar7240sw_port_stat {
247    unsigned long rx_broadcast;
248    unsigned long rx_pause;
249    unsigned long rx_multicast;
250    unsigned long rx_fcs_error;
251    unsigned long rx_align_error;
252    unsigned long rx_runt;
253    unsigned long rx_fragments;
254    unsigned long rx_64byte;
255    unsigned long rx_128byte;
256    unsigned long rx_256byte;
257    unsigned long rx_512byte;
258    unsigned long rx_1024byte;
259    unsigned long rx_1518byte;
260    unsigned long rx_maxbyte;
261    unsigned long rx_toolong;
262    unsigned long rx_good_byte;
263    unsigned long rx_bad_byte;
264    unsigned long rx_overflow;
265    unsigned long filtered;
266
267    unsigned long tx_broadcast;
268    unsigned long tx_pause;
269    unsigned long tx_multicast;
270    unsigned long tx_underrun;
271    unsigned long tx_64byte;
272    unsigned long tx_128byte;
273    unsigned long tx_256byte;
274    unsigned long tx_512byte;
275    unsigned long tx_1024byte;
276    unsigned long tx_1518byte;
277    unsigned long tx_maxbyte;
278    unsigned long tx_oversize;
279    unsigned long tx_byte;
280    unsigned long tx_collision;
281    unsigned long tx_abortcol;
282    unsigned long tx_multicol;
283    unsigned long tx_singlecol;
284    unsigned long tx_excdefer;
285    unsigned long tx_defer;
286    unsigned long tx_xlatecol;
287};
288
289struct ar7240sw {
290    struct mii_bus *mii_bus;
291    struct ag71xx_switch_platform_data *swdata;
292    struct switch_dev swdev;
293    int num_ports;
294    u8 ver;
295    bool vlan;
296    u16 vlan_id[AR7240_MAX_VLANS];
297    u8 vlan_table[AR7240_MAX_VLANS];
298    u8 vlan_tagged;
299    u16 pvid[AR7240_NUM_PORTS];
300    char buf[80];
301
302    rwlock_t stats_lock;
303    struct ar7240sw_port_stat port_stats[AR7240_NUM_PORTS];
304};
305
306struct ar7240sw_hw_stat {
307    char string[ETH_GSTRING_LEN];
308    int sizeof_stat;
309    int reg;
310};
311
312static DEFINE_MUTEX(reg_mutex);
313
314static inline int sw_is_ar7240(struct ar7240sw *as)
315{
316    return as->ver == AR7240_MASK_CTRL_VERSION_AR7240;
317}
318
319static inline int sw_is_ar934x(struct ar7240sw *as)
320{
321    return as->ver == AR7240_MASK_CTRL_VERSION_AR934X;
322}
323
324static inline u32 ar7240sw_port_mask(struct ar7240sw *as, int port)
325{
326    return BIT(port);
327}
328
329static inline u32 ar7240sw_port_mask_all(struct ar7240sw *as)
330{
331    return BIT(as->swdev.ports) - 1;
332}
333
334static inline u32 ar7240sw_port_mask_but(struct ar7240sw *as, int port)
335{
336    return ar7240sw_port_mask_all(as) & ~BIT(port);
337}
338
339static inline u16 mk_phy_addr(u32 reg)
340{
341    return 0x17 & ((reg >> 4) | 0x10);
342}
343
344static inline u16 mk_phy_reg(u32 reg)
345{
346    return (reg << 1) & 0x1e;
347}
348
349static inline u16 mk_high_addr(u32 reg)
350{
351    return (reg >> 7) & 0x1ff;
352}
353
354static u32 __ar7240sw_reg_read(struct mii_bus *mii, u32 reg)
355{
356    unsigned long flags;
357    u16 phy_addr;
358    u16 phy_reg;
359    u32 hi, lo;
360
361    reg = (reg & 0xfffffffc) >> 2;
362    phy_addr = mk_phy_addr(reg);
363    phy_reg = mk_phy_reg(reg);
364
365    local_irq_save(flags);
366    ag71xx_mdio_mii_write(mii->priv, 0x1f, 0x10, mk_high_addr(reg));
367    lo = (u32) ag71xx_mdio_mii_read(mii->priv, phy_addr, phy_reg);
368    hi = (u32) ag71xx_mdio_mii_read(mii->priv, phy_addr, phy_reg + 1);
369    local_irq_restore(flags);
370
371    return (hi << 16) | lo;
372}
373
374static void __ar7240sw_reg_write(struct mii_bus *mii, u32 reg, u32 val)
375{
376    unsigned long flags;
377    u16 phy_addr;
378    u16 phy_reg;
379
380    reg = (reg & 0xfffffffc) >> 2;
381    phy_addr = mk_phy_addr(reg);
382    phy_reg = mk_phy_reg(reg);
383
384    local_irq_save(flags);
385    ag71xx_mdio_mii_write(mii->priv, 0x1f, 0x10, mk_high_addr(reg));
386    ag71xx_mdio_mii_write(mii->priv, phy_addr, phy_reg + 1, (val >> 16));
387    ag71xx_mdio_mii_write(mii->priv, phy_addr, phy_reg, (val & 0xffff));
388    local_irq_restore(flags);
389}
390
391static u32 ar7240sw_reg_read(struct mii_bus *mii, u32 reg_addr)
392{
393    u32 ret;
394
395    mutex_lock(&reg_mutex);
396    ret = __ar7240sw_reg_read(mii, reg_addr);
397    mutex_unlock(&reg_mutex);
398
399    return ret;
400}
401
402static void ar7240sw_reg_write(struct mii_bus *mii, u32 reg_addr, u32 reg_val)
403{
404    mutex_lock(&reg_mutex);
405    __ar7240sw_reg_write(mii, reg_addr, reg_val);
406    mutex_unlock(&reg_mutex);
407}
408
409static u32 ar7240sw_reg_rmw(struct mii_bus *mii, u32 reg, u32 mask, u32 val)
410{
411    u32 t;
412
413    mutex_lock(&reg_mutex);
414    t = __ar7240sw_reg_read(mii, reg);
415    t &= ~mask;
416    t |= val;
417    __ar7240sw_reg_write(mii, reg, t);
418    mutex_unlock(&reg_mutex);
419
420    return t;
421}
422
423static void ar7240sw_reg_set(struct mii_bus *mii, u32 reg, u32 val)
424{
425    u32 t;
426
427    mutex_lock(&reg_mutex);
428    t = __ar7240sw_reg_read(mii, reg);
429    t |= val;
430    __ar7240sw_reg_write(mii, reg, t);
431    mutex_unlock(&reg_mutex);
432}
433
434static int __ar7240sw_reg_wait(struct mii_bus *mii, u32 reg, u32 mask, u32 val,
435                   unsigned timeout)
436{
437    int i;
438
439    for (i = 0; i < timeout; i++) {
440        u32 t;
441
442        t = __ar7240sw_reg_read(mii, reg);
443        if ((t & mask) == val)
444            return 0;
445
446        msleep(1);
447    }
448
449    return -ETIMEDOUT;
450}
451
452static int ar7240sw_reg_wait(struct mii_bus *mii, u32 reg, u32 mask, u32 val,
453                 unsigned timeout)
454{
455    int ret;
456
457    mutex_lock(&reg_mutex);
458    ret = __ar7240sw_reg_wait(mii, reg, mask, val, timeout);
459    mutex_unlock(&reg_mutex);
460    return ret;
461}
462
463u16 ar7240sw_phy_read(struct mii_bus *mii, unsigned phy_addr,
464              unsigned reg_addr)
465{
466    u32 t, val = 0xffff;
467    int err;
468
469    if (phy_addr >= AR7240_NUM_PHYS)
470        return 0xffff;
471
472    mutex_lock(&reg_mutex);
473    t = (reg_addr << AR7240_MDIO_CTRL_REG_ADDR_S) |
474        (phy_addr << AR7240_MDIO_CTRL_PHY_ADDR_S) |
475        AR7240_MDIO_CTRL_MASTER_EN |
476        AR7240_MDIO_CTRL_BUSY |
477        AR7240_MDIO_CTRL_CMD_READ;
478
479    __ar7240sw_reg_write(mii, AR7240_REG_MDIO_CTRL, t);
480    err = __ar7240sw_reg_wait(mii, AR7240_REG_MDIO_CTRL,
481                  AR7240_MDIO_CTRL_BUSY, 0, 5);
482    if (!err)
483        val = __ar7240sw_reg_read(mii, AR7240_REG_MDIO_CTRL);
484    mutex_unlock(&reg_mutex);
485
486    return val & AR7240_MDIO_CTRL_DATA_M;
487}
488
489int ar7240sw_phy_write(struct mii_bus *mii, unsigned phy_addr,
490               unsigned reg_addr, u16 reg_val)
491{
492    u32 t;
493    int ret;
494
495    if (phy_addr >= AR7240_NUM_PHYS)
496        return -EINVAL;
497
498    mutex_lock(&reg_mutex);
499    t = (phy_addr << AR7240_MDIO_CTRL_PHY_ADDR_S) |
500        (reg_addr << AR7240_MDIO_CTRL_REG_ADDR_S) |
501        AR7240_MDIO_CTRL_MASTER_EN |
502        AR7240_MDIO_CTRL_BUSY |
503        AR7240_MDIO_CTRL_CMD_WRITE |
504        reg_val;
505
506    __ar7240sw_reg_write(mii, AR7240_REG_MDIO_CTRL, t);
507    ret = __ar7240sw_reg_wait(mii, AR7240_REG_MDIO_CTRL,
508                  AR7240_MDIO_CTRL_BUSY, 0, 5);
509    mutex_unlock(&reg_mutex);
510
511    return ret;
512}
513
514static int ar7240sw_capture_stats(struct ar7240sw *as)
515{
516    struct mii_bus *mii = as->mii_bus;
517    int port;
518    int ret;
519
520    write_lock(&as->stats_lock);
521
522    /* Capture the hardware statistics for all ports */
523    ar7240sw_reg_rmw(mii, AR7240_REG_MIB_FUNCTION0,
524             (AR7240_MIB_FUNC_M << AR7240_MIB_FUNC_S),
525             (AR7240_MIB_FUNC_CAPTURE << AR7240_MIB_FUNC_S));
526
527    /* Wait for the capturing to complete. */
528    ret = ar7240sw_reg_wait(mii, AR7240_REG_MIB_FUNCTION0,
529                AR7240_MIB_BUSY, 0, 10);
530
531    if (ret)
532        goto unlock;
533
534    for (port = 0; port < AR7240_NUM_PORTS; port++) {
535        unsigned int base;
536        struct ar7240sw_port_stat *stats;
537
538        base = AR7240_REG_STATS_BASE(port);
539        stats = &as->port_stats[port];
540
541#define READ_STAT(_r) ar7240sw_reg_read(mii, base + AR7240_STATS_ ## _r)
542
543        stats->rx_good_byte += READ_STAT(RXGOODBYTE);
544        stats->tx_byte += READ_STAT(TXBYTE);
545
546#undef READ_STAT
547    }
548
549    ret = 0;
550
551unlock:
552    write_unlock(&as->stats_lock);
553    return ret;
554}
555
556static void ar7240sw_disable_port(struct ar7240sw *as, unsigned port)
557{
558    ar7240sw_reg_write(as->mii_bus, AR7240_REG_PORT_CTRL(port),
559               AR7240_PORT_CTRL_STATE_DISABLED);
560}
561
562static void ar7240sw_setup(struct ar7240sw *as)
563{
564    struct mii_bus *mii = as->mii_bus;
565
566    /* Enable CPU port, and disable mirror port */
567    ar7240sw_reg_write(mii, AR7240_REG_CPU_PORT,
568               AR7240_CPU_PORT_EN |
569               (15 << AR7240_MIRROR_PORT_S));
570
571    /* Setup TAG priority mapping */
572    ar7240sw_reg_write(mii, AR7240_REG_TAG_PRIORITY, 0xfa50);
573
574    if (sw_is_ar934x(as)) {
575        /* Enable aging, MAC replacing */
576        ar7240sw_reg_write(mii, AR934X_REG_AT_CTRL,
577            0x2b /* 5 min age time */ |
578            AR934X_AT_CTRL_AGE_EN |
579            AR934X_AT_CTRL_LEARN_CHANGE);
580        /* Enable ARP frame acknowledge */
581        ar7240sw_reg_set(mii, AR934X_REG_QM_CTRL,
582                 AR934X_QM_CTRL_ARP_EN);
583        /* Enable Broadcast frames transmitted to the CPU */
584        ar7240sw_reg_set(mii, AR934X_REG_FLOOD_MASK,
585                 AR934X_FLOOD_MASK_BC_DP(0));
586
587        /* Enable MIB counters */
588        ar7240sw_reg_set(mii, AR7240_REG_MIB_FUNCTION0,
589                 AR934X_MIB_ENABLE);
590
591    } else {
592        /* Enable ARP frame acknowledge, aging, MAC replacing */
593        ar7240sw_reg_write(mii, AR7240_REG_AT_CTRL,
594            AR7240_AT_CTRL_RESERVED |
595            0x2b /* 5 min age time */ |
596            AR7240_AT_CTRL_AGE_EN |
597            AR7240_AT_CTRL_ARP_EN |
598            AR7240_AT_CTRL_LEARN_CHANGE);
599        /* Enable Broadcast frames transmitted to the CPU */
600        ar7240sw_reg_set(mii, AR7240_REG_FLOOD_MASK,
601                 AR7240_FLOOD_MASK_BROAD_TO_CPU);
602    }
603
604    /* setup MTU */
605    ar7240sw_reg_rmw(mii, AR7240_REG_GLOBAL_CTRL, AR7240_GLOBAL_CTRL_MTU_M,
606             1536);
607
608    /* setup Service TAG */
609    ar7240sw_reg_rmw(mii, AR7240_REG_SERVICE_TAG, AR7240_SERVICE_TAG_M, 0);
610}
611
612static int ar7240sw_reset(struct ar7240sw *as)
613{
614    struct mii_bus *mii = as->mii_bus;
615    int ret;
616    int i;
617
618    /* Set all ports to disabled state. */
619    for (i = 0; i < AR7240_NUM_PORTS; i++)
620        ar7240sw_disable_port(as, i);
621
622    /* Wait for transmit queues to drain. */
623    msleep(2);
624
625    /* Reset the switch. */
626    ar7240sw_reg_write(mii, AR7240_REG_MASK_CTRL,
627               AR7240_MASK_CTRL_SOFT_RESET);
628
629    ret = ar7240sw_reg_wait(mii, AR7240_REG_MASK_CTRL,
630                AR7240_MASK_CTRL_SOFT_RESET, 0, 1000);
631
632    /* setup PHYs */
633    for (i = 0; i < AR7240_NUM_PHYS; i++) {
634        ar7240sw_phy_write(mii, i, MII_ADVERTISE,
635                   ADVERTISE_ALL | ADVERTISE_PAUSE_CAP |
636                   ADVERTISE_PAUSE_ASYM);
637        ar7240sw_phy_write(mii, i, MII_BMCR,
638                   BMCR_RESET | BMCR_ANENABLE);
639    }
640    msleep(1000);
641
642    ar7240sw_setup(as);
643    return ret;
644}
645
646static void ar7240sw_setup_port(struct ar7240sw *as, unsigned port, u8 portmask)
647{
648    struct mii_bus *mii = as->mii_bus;
649    u32 ctrl;
650    u32 vid, mode;
651
652    ctrl = AR7240_PORT_CTRL_STATE_FORWARD | AR7240_PORT_CTRL_LEARN |
653        AR7240_PORT_CTRL_SINGLE_VLAN;
654
655    if (port == AR7240_PORT_CPU) {
656        ar7240sw_reg_write(mii, AR7240_REG_PORT_STATUS(port),
657                   AR7240_PORT_STATUS_SPEED_1000 |
658                   AR7240_PORT_STATUS_TXFLOW |
659                   AR7240_PORT_STATUS_RXFLOW |
660                   AR7240_PORT_STATUS_TXMAC |
661                   AR7240_PORT_STATUS_RXMAC |
662                   AR7240_PORT_STATUS_DUPLEX);
663    } else {
664        ar7240sw_reg_write(mii, AR7240_REG_PORT_STATUS(port),
665                   AR7240_PORT_STATUS_LINK_AUTO);
666    }
667
668    /* Set the default VID for this port */
669    if (as->vlan) {
670        vid = as->vlan_id[as->pvid[port]];
671        mode = AR7240_PORT_VLAN_MODE_SECURE;
672    } else {
673        vid = port;
674        mode = AR7240_PORT_VLAN_MODE_PORT_ONLY;
675    }
676
677    if (as->vlan) {
678        if (as->vlan_tagged & BIT(port))
679            ctrl |= AR7240_PORT_CTRL_VLAN_MODE_ADD <<
680                AR7240_PORT_CTRL_VLAN_MODE_S;
681        else
682            ctrl |= AR7240_PORT_CTRL_VLAN_MODE_STRIP <<
683                AR7240_PORT_CTRL_VLAN_MODE_S;
684    } else {
685        ctrl |= AR7240_PORT_CTRL_VLAN_MODE_KEEP <<
686            AR7240_PORT_CTRL_VLAN_MODE_S;
687    }
688
689    if (!portmask) {
690        if (port == AR7240_PORT_CPU)
691            portmask = ar7240sw_port_mask_but(as, AR7240_PORT_CPU);
692        else
693            portmask = ar7240sw_port_mask(as, AR7240_PORT_CPU);
694    }
695
696    /* allow the port to talk to all other ports, but exclude its
697     * own ID to prevent frames from being reflected back to the
698     * port that they came from */
699    portmask &= ar7240sw_port_mask_but(as, port);
700
701    ar7240sw_reg_write(mii, AR7240_REG_PORT_CTRL(port), ctrl);
702    if (sw_is_ar934x(as)) {
703        u32 vlan1, vlan2;
704
705        vlan1 = (vid << AR934X_PORT_VLAN1_DEFAULT_CVID_S);
706        vlan2 = (portmask << AR934X_PORT_VLAN2_PORT_VID_MEM_S) |
707            (mode << AR934X_PORT_VLAN2_8021Q_MODE_S);
708        ar7240sw_reg_write(mii, AR934X_REG_PORT_VLAN1(port), vlan1);
709        ar7240sw_reg_write(mii, AR934X_REG_PORT_VLAN2(port), vlan2);
710    } else {
711        u32 vlan;
712
713        vlan = vid | (mode << AR7240_PORT_VLAN_MODE_S) |
714               (portmask << AR7240_PORT_VLAN_DEST_PORTS_S);
715
716        ar7240sw_reg_write(mii, AR7240_REG_PORT_VLAN(port), vlan);
717    }
718}
719
720static int ar7240_set_addr(struct ar7240sw *as, u8 *addr)
721{
722    struct mii_bus *mii = as->mii_bus;
723    u32 t;
724
725    t = (addr[4] << 8) | addr[5];
726    ar7240sw_reg_write(mii, AR7240_REG_MAC_ADDR0, t);
727
728    t = (addr[0] << 24) | (addr[1] << 16) | (addr[2] << 8) | addr[3];
729    ar7240sw_reg_write(mii, AR7240_REG_MAC_ADDR1, t);
730
731    return 0;
732}
733
734static int
735ar7240_set_vid(struct switch_dev *dev, const struct switch_attr *attr,
736        struct switch_val *val)
737{
738    struct ar7240sw *as = sw_to_ar7240(dev);
739    as->vlan_id[val->port_vlan] = val->value.i;
740    return 0;
741}
742
743static int
744ar7240_get_vid(struct switch_dev *dev, const struct switch_attr *attr,
745        struct switch_val *val)
746{
747    struct ar7240sw *as = sw_to_ar7240(dev);
748    val->value.i = as->vlan_id[val->port_vlan];
749    return 0;
750}
751
752static int
753ar7240_set_pvid(struct switch_dev *dev, int port, int vlan)
754{
755    struct ar7240sw *as = sw_to_ar7240(dev);
756
757    /* make sure no invalid PVIDs get set */
758
759    if (vlan >= dev->vlans)
760        return -EINVAL;
761
762    as->pvid[port] = vlan;
763    return 0;
764}
765
766static int
767ar7240_get_pvid(struct switch_dev *dev, int port, int *vlan)
768{
769    struct ar7240sw *as = sw_to_ar7240(dev);
770    *vlan = as->pvid[port];
771    return 0;
772}
773
774static int
775ar7240_get_ports(struct switch_dev *dev, struct switch_val *val)
776{
777    struct ar7240sw *as = sw_to_ar7240(dev);
778    u8 ports = as->vlan_table[val->port_vlan];
779    int i;
780
781    val->len = 0;
782    for (i = 0; i < as->swdev.ports; i++) {
783        struct switch_port *p;
784
785        if (!(ports & (1 << i)))
786            continue;
787
788        p = &val->value.ports[val->len++];
789        p->id = i;
790        if (as->vlan_tagged & (1 << i))
791            p->flags = (1 << SWITCH_PORT_FLAG_TAGGED);
792        else
793            p->flags = 0;
794    }
795    return 0;
796}
797
798static int
799ar7240_set_ports(struct switch_dev *dev, struct switch_val *val)
800{
801    struct ar7240sw *as = sw_to_ar7240(dev);
802    u8 *vt = &as->vlan_table[val->port_vlan];
803    int i, j;
804
805    *vt = 0;
806    for (i = 0; i < val->len; i++) {
807        struct switch_port *p = &val->value.ports[i];
808
809        if (p->flags & (1 << SWITCH_PORT_FLAG_TAGGED))
810            as->vlan_tagged |= (1 << p->id);
811        else {
812            as->vlan_tagged &= ~(1 << p->id);
813            as->pvid[p->id] = val->port_vlan;
814
815            /* make sure that an untagged port does not
816             * appear in other vlans */
817            for (j = 0; j < AR7240_MAX_VLANS; j++) {
818                if (j == val->port_vlan)
819                    continue;
820                as->vlan_table[j] &= ~(1 << p->id);
821            }
822        }
823
824        *vt |= 1 << p->id;
825    }
826    return 0;
827}
828
829static int
830ar7240_set_vlan(struct switch_dev *dev, const struct switch_attr *attr,
831        struct switch_val *val)
832{
833    struct ar7240sw *as = sw_to_ar7240(dev);
834    as->vlan = !!val->value.i;
835    return 0;
836}
837
838static int
839ar7240_get_vlan(struct switch_dev *dev, const struct switch_attr *attr,
840        struct switch_val *val)
841{
842    struct ar7240sw *as = sw_to_ar7240(dev);
843    val->value.i = as->vlan;
844    return 0;
845}
846
847static void
848ar7240_vtu_op(struct ar7240sw *as, u32 op, u32 val)
849{
850    struct mii_bus *mii = as->mii_bus;
851
852    if (ar7240sw_reg_wait(mii, AR7240_REG_VTU, AR7240_VTU_ACTIVE, 0, 5))
853        return;
854
855    if ((op & AR7240_VTU_OP) == AR7240_VTU_OP_LOAD) {
856        val &= AR7240_VTUDATA_MEMBER;
857        val |= AR7240_VTUDATA_VALID;
858        ar7240sw_reg_write(mii, AR7240_REG_VTU_DATA, val);
859    }
860    op |= AR7240_VTU_ACTIVE;
861    ar7240sw_reg_write(mii, AR7240_REG_VTU, op);
862}
863
864static int
865ar7240_hw_apply(struct switch_dev *dev)
866{
867    struct ar7240sw *as = sw_to_ar7240(dev);
868    u8 portmask[AR7240_NUM_PORTS];
869    int i, j;
870
871    /* flush all vlan translation unit entries */
872    ar7240_vtu_op(as, AR7240_VTU_OP_FLUSH, 0);
873
874    memset(portmask, 0, sizeof(portmask));
875    if (as->vlan) {
876        /* calculate the port destination masks and load vlans
877         * into the vlan translation unit */
878        for (j = 0; j < AR7240_MAX_VLANS; j++) {
879            u8 vp = as->vlan_table[j];
880
881            if (!vp)
882                continue;
883
884            for (i = 0; i < as->swdev.ports; i++) {
885                u8 mask = (1 << i);
886                if (vp & mask)
887                    portmask[i] |= vp & ~mask;
888            }
889
890            ar7240_vtu_op(as,
891                AR7240_VTU_OP_LOAD |
892                (as->vlan_id[j] << AR7240_VTU_VID_S),
893                as->vlan_table[j]);
894        }
895    } else {
896        /* vlan disabled:
897         * isolate all ports, but connect them to the cpu port */
898        for (i = 0; i < as->swdev.ports; i++) {
899            if (i == AR7240_PORT_CPU)
900                continue;
901
902            portmask[i] = 1 << AR7240_PORT_CPU;
903            portmask[AR7240_PORT_CPU] |= (1 << i);
904        }
905    }
906
907    /* update the port destination mask registers and tag settings */
908    for (i = 0; i < as->swdev.ports; i++)
909        ar7240sw_setup_port(as, i, portmask[i]);
910
911    return 0;
912}
913
914static int
915ar7240_reset_switch(struct switch_dev *dev)
916{
917    struct ar7240sw *as = sw_to_ar7240(dev);
918    ar7240sw_reset(as);
919    return 0;
920}
921
922static int
923ar7240_get_port_link(struct switch_dev *dev, int port,
924             struct switch_port_link *link)
925{
926    struct ar7240sw *as = sw_to_ar7240(dev);
927    struct mii_bus *mii = as->mii_bus;
928    u32 status;
929
930    if (port > AR7240_NUM_PORTS)
931        return -EINVAL;
932
933    status = ar7240sw_reg_read(mii, AR7240_REG_PORT_STATUS(port));
934    link->aneg = !!(status & AR7240_PORT_STATUS_LINK_AUTO);
935    if (link->aneg) {
936        link->link = !!(status & AR7240_PORT_STATUS_LINK_UP);
937        if (!link->link)
938            return 0;
939    } else {
940        link->link = true;
941    }
942
943    link->duplex = !!(status & AR7240_PORT_STATUS_DUPLEX);
944    link->tx_flow = !!(status & AR7240_PORT_STATUS_TXFLOW);
945    link->rx_flow = !!(status & AR7240_PORT_STATUS_RXFLOW);
946    switch (status & AR7240_PORT_STATUS_SPEED_M) {
947    case AR7240_PORT_STATUS_SPEED_10:
948        link->speed = SWITCH_PORT_SPEED_10;
949        break;
950    case AR7240_PORT_STATUS_SPEED_100:
951        link->speed = SWITCH_PORT_SPEED_100;
952        break;
953    case AR7240_PORT_STATUS_SPEED_1000:
954        link->speed = SWITCH_PORT_SPEED_1000;
955        break;
956    }
957
958    return 0;
959}
960
961static int
962ar7240_get_port_stats(struct switch_dev *dev, int port,
963              struct switch_port_stats *stats)
964{
965    struct ar7240sw *as = sw_to_ar7240(dev);
966
967    if (port > AR7240_NUM_PORTS)
968        return -EINVAL;
969
970    ar7240sw_capture_stats(as);
971
972    read_lock(&as->stats_lock);
973    stats->rx_bytes = as->port_stats[port].rx_good_byte;
974    stats->tx_bytes = as->port_stats[port].tx_byte;
975    read_unlock(&as->stats_lock);
976
977    return 0;
978}
979
980static struct switch_attr ar7240_globals[] = {
981    {
982        .type = SWITCH_TYPE_INT,
983        .name = "enable_vlan",
984        .description = "Enable VLAN mode",
985        .set = ar7240_set_vlan,
986        .get = ar7240_get_vlan,
987        .max = 1
988    },
989};
990
991static struct switch_attr ar7240_port[] = {
992};
993
994static struct switch_attr ar7240_vlan[] = {
995    {
996        .type = SWITCH_TYPE_INT,
997        .name = "vid",
998        .description = "VLAN ID",
999        .set = ar7240_set_vid,
1000        .get = ar7240_get_vid,
1001        .max = 4094,
1002    },
1003};
1004
1005static const struct switch_dev_ops ar7240_ops = {
1006    .attr_global = {
1007        .attr = ar7240_globals,
1008        .n_attr = ARRAY_SIZE(ar7240_globals),
1009    },
1010    .attr_port = {
1011        .attr = ar7240_port,
1012        .n_attr = ARRAY_SIZE(ar7240_port),
1013    },
1014    .attr_vlan = {
1015        .attr = ar7240_vlan,
1016        .n_attr = ARRAY_SIZE(ar7240_vlan),
1017    },
1018    .get_port_pvid = ar7240_get_pvid,
1019    .set_port_pvid = ar7240_set_pvid,
1020    .get_vlan_ports = ar7240_get_ports,
1021    .set_vlan_ports = ar7240_set_ports,
1022    .apply_config = ar7240_hw_apply,
1023    .reset_switch = ar7240_reset_switch,
1024    .get_port_link = ar7240_get_port_link,
1025    .get_port_stats = ar7240_get_port_stats,
1026};
1027
1028static struct ar7240sw *ar7240_probe(struct ag71xx *ag)
1029{
1030    struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
1031    struct mii_bus *mii = ag->mii_bus;
1032    struct ar7240sw *as;
1033    struct switch_dev *swdev;
1034    u32 ctrl;
1035    u16 phy_id1;
1036    u16 phy_id2;
1037    int i;
1038
1039    phy_id1 = ar7240sw_phy_read(mii, 0, MII_PHYSID1);
1040    phy_id2 = ar7240sw_phy_read(mii, 0, MII_PHYSID2);
1041    if ((phy_id1 != AR7240_PHY_ID1 || phy_id2 != AR7240_PHY_ID2) &&
1042        (phy_id1 != AR934X_PHY_ID1 || phy_id2 != AR934X_PHY_ID2)) {
1043        pr_err("%s: unknown phy id '%04x:%04x'\n",
1044               ag->dev->name, phy_id1, phy_id2);
1045        return NULL;
1046    }
1047
1048    as = kzalloc(sizeof(*as), GFP_KERNEL);
1049    if (!as)
1050        return NULL;
1051
1052    as->mii_bus = mii;
1053    as->swdata = pdata->switch_data;
1054
1055    swdev = &as->swdev;
1056
1057    ctrl = ar7240sw_reg_read(mii, AR7240_REG_MASK_CTRL);
1058    as->ver = (ctrl >> AR7240_MASK_CTRL_VERSION_S) &
1059          AR7240_MASK_CTRL_VERSION_M;
1060
1061    if (sw_is_ar7240(as)) {
1062        swdev->name = "AR7240/AR9330 built-in switch";
1063        swdev->ports = AR7240_NUM_PORTS - 1;
1064    } else if (sw_is_ar934x(as)) {
1065        swdev->name = "AR934X built-in switch";
1066
1067        if (pdata->phy_if_mode == PHY_INTERFACE_MODE_GMII) {
1068            ar7240sw_reg_set(mii, AR934X_REG_OPER_MODE0,
1069                     AR934X_OPER_MODE0_MAC_GMII_EN);
1070        } else if (pdata->phy_if_mode == PHY_INTERFACE_MODE_MII) {
1071            ar7240sw_reg_set(mii, AR934X_REG_OPER_MODE0,
1072                     AR934X_OPER_MODE0_PHY_MII_EN);
1073        } else {
1074            pr_err("%s: invalid PHY interface mode\n",
1075                   ag->dev->name);
1076            goto err_free;
1077        }
1078
1079        if (as->swdata->phy4_mii_en) {
1080            ar7240sw_reg_set(mii, AR934X_REG_OPER_MODE1,
1081                     AR934X_REG_OPER_MODE1_PHY4_MII_EN);
1082            swdev->ports = AR7240_NUM_PORTS - 1;
1083        } else {
1084            swdev->ports = AR7240_NUM_PORTS;
1085        }
1086    } else {
1087        pr_err("%s: unsupported chip, ctrl=%08x\n",
1088            ag->dev->name, ctrl);
1089        goto err_free;
1090    }
1091
1092    swdev->cpu_port = AR7240_PORT_CPU;
1093    swdev->vlans = AR7240_MAX_VLANS;
1094    swdev->ops = &ar7240_ops;
1095
1096    if (register_switch(&as->swdev, ag->dev) < 0)
1097        goto err_free;
1098
1099    pr_info("%s: Found an %s\n", ag->dev->name, swdev->name);
1100
1101    /* initialize defaults */
1102    for (i = 0; i < AR7240_MAX_VLANS; i++)
1103        as->vlan_id[i] = i;
1104
1105    as->vlan_table[0] = ar7240sw_port_mask_all(as);
1106
1107    return as;
1108
1109err_free:
1110    kfree(as);
1111    return NULL;
1112}
1113
1114static void link_function(struct work_struct *work) {
1115    struct ag71xx *ag = container_of(work, struct ag71xx, link_work.work);
1116    struct ar7240sw *as = ag->phy_priv;
1117    unsigned long flags;
1118    u8 mask;
1119    int i;
1120    int status = 0;
1121
1122    mask = ~as->swdata->phy_poll_mask;
1123    for (i = 0; i < AR7240_NUM_PHYS; i++) {
1124        int link;
1125
1126        if (!(mask & BIT(i)))
1127            continue;
1128
1129        link = ar7240sw_phy_read(ag->mii_bus, i, MII_BMSR);
1130        if (link & BMSR_LSTATUS) {
1131            status = 1;
1132            break;
1133        }
1134    }
1135
1136    spin_lock_irqsave(&ag->lock, flags);
1137    if (status != ag->link) {
1138        ag->link = status;
1139        ag71xx_link_adjust(ag);
1140    }
1141    spin_unlock_irqrestore(&ag->lock, flags);
1142
1143    schedule_delayed_work(&ag->link_work, HZ / 2);
1144}
1145
1146void ag71xx_ar7240_start(struct ag71xx *ag)
1147{
1148    struct ar7240sw *as = ag->phy_priv;
1149
1150    ar7240sw_reset(as);
1151
1152    ag->speed = SPEED_1000;
1153    ag->duplex = 1;
1154
1155    ar7240_set_addr(as, ag->dev->dev_addr);
1156    ar7240_hw_apply(&as->swdev);
1157
1158    schedule_delayed_work(&ag->link_work, HZ / 10);
1159}
1160
1161void ag71xx_ar7240_stop(struct ag71xx *ag)
1162{
1163    cancel_delayed_work_sync(&ag->link_work);
1164}
1165
1166int __devinit ag71xx_ar7240_init(struct ag71xx *ag)
1167{
1168    struct ar7240sw *as;
1169
1170    as = ar7240_probe(ag);
1171    if (!as)
1172        return -ENODEV;
1173
1174    ag->phy_priv = as;
1175    ar7240sw_reset(as);
1176
1177    rwlock_init(&as->stats_lock);
1178    INIT_DELAYED_WORK(&ag->link_work, link_function);
1179
1180    return 0;
1181}
1182
1183void ag71xx_ar7240_cleanup(struct ag71xx *ag)
1184{
1185    struct ar7240sw *as = ag->phy_priv;
1186
1187    if (!as)
1188        return;
1189
1190    unregister_switch(&as->swdev);
1191    kfree(as);
1192    ag->phy_priv = NULL;
1193}
1194

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