Root/target/linux/ar71xx/files/drivers/spi/spi-rb4xx.c

1/*
2 * SPI controller driver for the Mikrotik RB4xx boards
3 *
4 * Copyright (C) 2010 Gabor Juhos <juhosg@openwrt.org>
5 *
6 * This file was based on the patches for Linux 2.6.27.39 published by
7 * MikroTik for their RouterBoard 4xx series devices.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 *
13 */
14
15#include <linux/clk.h>
16#include <linux/err.h>
17#include <linux/kernel.h>
18#include <linux/module.h>
19#include <linux/init.h>
20#include <linux/delay.h>
21#include <linux/spinlock.h>
22#include <linux/workqueue.h>
23#include <linux/platform_device.h>
24#include <linux/spi/spi.h>
25
26#include <asm/mach-ath79/ar71xx_regs.h>
27#include <asm/mach-ath79/ath79.h>
28
29#define DRV_NAME "rb4xx-spi"
30#define DRV_DESC "Mikrotik RB4xx SPI controller driver"
31#define DRV_VERSION "0.1.0"
32
33#define SPI_CTRL_FASTEST 0x40
34#define SPI_FLASH_HZ 33333334
35#define SPI_CPLD_HZ 33333334
36
37#define CPLD_CMD_READ_FAST 0x0b
38
39#undef RB4XX_SPI_DEBUG
40
41struct rb4xx_spi {
42    void __iomem *base;
43    struct spi_master *master;
44
45    unsigned spi_ctrl_flash;
46    unsigned spi_ctrl_fread;
47
48    struct clk *ahb_clk;
49    unsigned long ahb_freq;
50
51    spinlock_t lock;
52    struct list_head queue;
53    int busy:1;
54    int cs_wait;
55};
56
57static unsigned spi_clk_low = AR71XX_SPI_IOC_CS1;
58
59#ifdef RB4XX_SPI_DEBUG
60static inline void do_spi_delay(void)
61{
62    ndelay(20000);
63}
64#else
65static inline void do_spi_delay(void) { }
66#endif
67
68static inline void do_spi_init(struct spi_device *spi)
69{
70    unsigned cs = AR71XX_SPI_IOC_CS0 | AR71XX_SPI_IOC_CS1;
71
72    if (!(spi->mode & SPI_CS_HIGH))
73        cs ^= (spi->chip_select == 2) ? AR71XX_SPI_IOC_CS1 :
74                        AR71XX_SPI_IOC_CS0;
75
76    spi_clk_low = cs;
77}
78
79static inline void do_spi_finish(void __iomem *base)
80{
81    do_spi_delay();
82    __raw_writel(AR71XX_SPI_IOC_CS0 | AR71XX_SPI_IOC_CS1,
83             base + AR71XX_SPI_REG_IOC);
84}
85
86static inline void do_spi_clk(void __iomem *base, int bit)
87{
88    unsigned bval = spi_clk_low | ((bit & 1) ? AR71XX_SPI_IOC_DO : 0);
89
90    do_spi_delay();
91    __raw_writel(bval, base + AR71XX_SPI_REG_IOC);
92    do_spi_delay();
93    __raw_writel(bval | AR71XX_SPI_IOC_CLK, base + AR71XX_SPI_REG_IOC);
94}
95
96static void do_spi_byte(void __iomem *base, unsigned char byte)
97{
98    do_spi_clk(base, byte >> 7);
99    do_spi_clk(base, byte >> 6);
100    do_spi_clk(base, byte >> 5);
101    do_spi_clk(base, byte >> 4);
102    do_spi_clk(base, byte >> 3);
103    do_spi_clk(base, byte >> 2);
104    do_spi_clk(base, byte >> 1);
105    do_spi_clk(base, byte);
106
107    pr_debug("spi_byte sent 0x%02x got 0x%02x\n",
108           (unsigned)byte,
109           (unsigned char)__raw_readl(base + AR71XX_SPI_REG_RDS));
110}
111
112static inline void do_spi_clk_fast(void __iomem *base, unsigned bit1,
113                   unsigned bit2)
114{
115    unsigned bval = (spi_clk_low |
116             ((bit1 & 1) ? AR71XX_SPI_IOC_DO : 0) |
117             ((bit2 & 1) ? AR71XX_SPI_IOC_CS2 : 0));
118    do_spi_delay();
119    __raw_writel(bval, base + AR71XX_SPI_REG_IOC);
120    do_spi_delay();
121    __raw_writel(bval | AR71XX_SPI_IOC_CLK, base + AR71XX_SPI_REG_IOC);
122}
123
124static void do_spi_byte_fast(void __iomem *base, unsigned char byte)
125{
126    do_spi_clk_fast(base, byte >> 7, byte >> 6);
127    do_spi_clk_fast(base, byte >> 5, byte >> 4);
128    do_spi_clk_fast(base, byte >> 3, byte >> 2);
129    do_spi_clk_fast(base, byte >> 1, byte >> 0);
130
131    pr_debug("spi_byte_fast sent 0x%02x got 0x%02x\n",
132           (unsigned)byte,
133           (unsigned char) __raw_readl(base + AR71XX_SPI_REG_RDS));
134}
135
136static int rb4xx_spi_txrx(void __iomem *base, struct spi_transfer *t)
137{
138    const unsigned char *rxv_ptr = NULL;
139    const unsigned char *tx_ptr = t->tx_buf;
140    unsigned char *rx_ptr = t->rx_buf;
141    unsigned i;
142
143    pr_debug("spi_txrx len %u tx %u rx %u\n",
144           t->len,
145           (t->tx_buf ? 1 : 0),
146           (t->rx_buf ? 1 : 0));
147
148    if (t->verify) {
149        rxv_ptr = tx_ptr;
150        tx_ptr = NULL;
151    }
152
153    for (i = 0; i < t->len; ++i) {
154        unsigned char sdata = tx_ptr ? tx_ptr[i] : 0;
155
156        if (t->fast_write)
157            do_spi_byte_fast(base, sdata);
158        else
159            do_spi_byte(base, sdata);
160
161        if (rx_ptr) {
162            rx_ptr[i] = __raw_readl(base + AR71XX_SPI_REG_RDS) & 0xff;
163        } else if (rxv_ptr) {
164            unsigned char c = __raw_readl(base + AR71XX_SPI_REG_RDS);
165            if (rxv_ptr[i] != c)
166                return i;
167        }
168    }
169
170    return i;
171}
172
173static int rb4xx_spi_read_fast(struct rb4xx_spi *rbspi,
174                   struct spi_message *m)
175{
176    struct spi_transfer *t;
177    const unsigned char *tx_ptr;
178    unsigned addr;
179    void __iomem *base = rbspi->base;
180
181    /* check for exactly two transfers */
182    if (list_empty(&m->transfers) ||
183        list_is_last(m->transfers.next, &m->transfers) ||
184        !list_is_last(m->transfers.next->next, &m->transfers)) {
185        return -1;
186    }
187
188    /* first transfer contains command and address */
189    t = list_entry(m->transfers.next,
190               struct spi_transfer, transfer_list);
191
192    if (t->len != 5 || t->tx_buf == NULL)
193        return -1;
194
195    tx_ptr = t->tx_buf;
196    if (tx_ptr[0] != CPLD_CMD_READ_FAST)
197        return -1;
198
199    addr = tx_ptr[1];
200    addr = tx_ptr[2] | (addr << 8);
201    addr = tx_ptr[3] | (addr << 8);
202    addr += (unsigned) base;
203
204    m->actual_length += t->len;
205
206    /* second transfer contains data itself */
207    t = list_entry(m->transfers.next->next,
208               struct spi_transfer, transfer_list);
209
210    if (t->tx_buf && !t->verify)
211        return -1;
212
213    __raw_writel(AR71XX_SPI_FS_GPIO, base + AR71XX_SPI_REG_FS);
214    __raw_writel(rbspi->spi_ctrl_fread, base + AR71XX_SPI_REG_CTRL);
215    __raw_writel(0, base + AR71XX_SPI_REG_FS);
216
217    if (t->rx_buf) {
218        memcpy(t->rx_buf, (const void *)addr, t->len);
219    } else if (t->tx_buf) {
220        unsigned char buf[t->len];
221        memcpy(buf, (const void *)addr, t->len);
222        if (memcmp(t->tx_buf, buf, t->len) != 0)
223            m->status = -EMSGSIZE;
224    }
225    m->actual_length += t->len;
226
227    if (rbspi->spi_ctrl_flash != rbspi->spi_ctrl_fread) {
228        __raw_writel(AR71XX_SPI_FS_GPIO, base + AR71XX_SPI_REG_FS);
229        __raw_writel(rbspi->spi_ctrl_flash, base + AR71XX_SPI_REG_CTRL);
230        __raw_writel(0, base + AR71XX_SPI_REG_FS);
231    }
232
233    return 0;
234}
235
236static int rb4xx_spi_msg(struct rb4xx_spi *rbspi, struct spi_message *m)
237{
238    struct spi_transfer *t = NULL;
239    void __iomem *base = rbspi->base;
240
241    m->status = 0;
242    if (list_empty(&m->transfers))
243        return -1;
244
245    if (m->fast_read)
246        if (rb4xx_spi_read_fast(rbspi, m) == 0)
247            return -1;
248
249    __raw_writel(AR71XX_SPI_FS_GPIO, base + AR71XX_SPI_REG_FS);
250    __raw_writel(SPI_CTRL_FASTEST, base + AR71XX_SPI_REG_CTRL);
251    do_spi_init(m->spi);
252
253    list_for_each_entry(t, &m->transfers, transfer_list) {
254        int len;
255
256        len = rb4xx_spi_txrx(base, t);
257        if (len != t->len) {
258            m->status = -EMSGSIZE;
259            break;
260        }
261        m->actual_length += len;
262
263        if (t->cs_change) {
264            if (list_is_last(&t->transfer_list, &m->transfers)) {
265                /* wait for continuation */
266                return m->spi->chip_select;
267            }
268            do_spi_finish(base);
269            ndelay(100);
270        }
271    }
272
273    do_spi_finish(base);
274    __raw_writel(rbspi->spi_ctrl_flash, base + AR71XX_SPI_REG_CTRL);
275    __raw_writel(0, base + AR71XX_SPI_REG_FS);
276    return -1;
277}
278
279static void rb4xx_spi_process_queue_locked(struct rb4xx_spi *rbspi,
280                       unsigned long *flags)
281{
282    int cs = rbspi->cs_wait;
283
284    rbspi->busy = 1;
285    while (!list_empty(&rbspi->queue)) {
286        struct spi_message *m;
287
288        list_for_each_entry(m, &rbspi->queue, queue)
289            if (cs < 0 || cs == m->spi->chip_select)
290                break;
291
292        if (&m->queue == &rbspi->queue)
293            break;
294
295        list_del_init(&m->queue);
296        spin_unlock_irqrestore(&rbspi->lock, *flags);
297
298        cs = rb4xx_spi_msg(rbspi, m);
299        m->complete(m->context);
300
301        spin_lock_irqsave(&rbspi->lock, *flags);
302    }
303
304    rbspi->cs_wait = cs;
305    rbspi->busy = 0;
306
307    if (cs >= 0) {
308        /* TODO: add timer to unlock cs after 1s inactivity */
309    }
310}
311
312static int rb4xx_spi_transfer(struct spi_device *spi,
313                  struct spi_message *m)
314{
315    struct rb4xx_spi *rbspi = spi_master_get_devdata(spi->master);
316    unsigned long flags;
317
318    m->actual_length = 0;
319    m->status = -EINPROGRESS;
320
321    spin_lock_irqsave(&rbspi->lock, flags);
322    list_add_tail(&m->queue, &rbspi->queue);
323    if (rbspi->busy ||
324        (rbspi->cs_wait >= 0 && rbspi->cs_wait != m->spi->chip_select)) {
325        /* job will be done later */
326        spin_unlock_irqrestore(&rbspi->lock, flags);
327        return 0;
328    }
329
330    /* process job in current context */
331    rb4xx_spi_process_queue_locked(rbspi, &flags);
332    spin_unlock_irqrestore(&rbspi->lock, flags);
333
334    return 0;
335}
336
337static int rb4xx_spi_setup(struct spi_device *spi)
338{
339    struct rb4xx_spi *rbspi = spi_master_get_devdata(spi->master);
340    unsigned long flags;
341
342    if (spi->mode & ~(SPI_CS_HIGH)) {
343        dev_err(&spi->dev, "mode %x not supported\n",
344            (unsigned) spi->mode);
345        return -EINVAL;
346    }
347
348    if (spi->bits_per_word != 8 && spi->bits_per_word != 0) {
349        dev_err(&spi->dev, "bits_per_word %u not supported\n",
350            (unsigned) spi->bits_per_word);
351        return -EINVAL;
352    }
353
354    spin_lock_irqsave(&rbspi->lock, flags);
355    if (rbspi->cs_wait == spi->chip_select && !rbspi->busy) {
356        rbspi->cs_wait = -1;
357        rb4xx_spi_process_queue_locked(rbspi, &flags);
358    }
359    spin_unlock_irqrestore(&rbspi->lock, flags);
360
361    return 0;
362}
363
364static unsigned get_spi_ctrl(struct rb4xx_spi *rbspi, unsigned hz_max,
365                 const char *name)
366{
367    unsigned div;
368
369    div = (rbspi->ahb_freq - 1) / (2 * hz_max);
370
371    /*
372     * CPU has a bug at (div == 0) - first bit read is random
373     */
374    if (div == 0)
375        ++div;
376
377    if (name) {
378        unsigned ahb_khz = (rbspi->ahb_freq + 500) / 1000;
379        unsigned div_real = 2 * (div + 1);
380        pr_debug("rb4xx: %s SPI clock %u kHz (AHB %u kHz / %u)\n",
381               name,
382               ahb_khz / div_real,
383               ahb_khz, div_real);
384    }
385
386    return SPI_CTRL_FASTEST + div;
387}
388
389static int rb4xx_spi_probe(struct platform_device *pdev)
390{
391    struct spi_master *master;
392    struct rb4xx_spi *rbspi;
393    struct resource *r;
394    int err = 0;
395
396    master = spi_alloc_master(&pdev->dev, sizeof(*rbspi));
397    if (master == NULL) {
398        dev_err(&pdev->dev, "no memory for spi_master\n");
399        err = -ENOMEM;
400        goto err_out;
401    }
402
403    master->bus_num = 0;
404    master->num_chipselect = 3;
405    master->setup = rb4xx_spi_setup;
406    master->transfer = rb4xx_spi_transfer;
407
408    rbspi = spi_master_get_devdata(master);
409
410    rbspi->ahb_clk = clk_get(&pdev->dev, "ahb");
411    if (IS_ERR(rbspi->ahb_clk)) {
412        err = PTR_ERR(rbspi->ahb_clk);
413        goto err_put_master;
414    }
415
416    err = clk_enable(rbspi->ahb_clk);
417    if (err)
418        goto err_clk_put;
419
420    rbspi->ahb_freq = clk_get_rate(rbspi->ahb_clk);
421    if (!rbspi->ahb_freq) {
422        err = -EINVAL;
423        goto err_clk_disable;
424    }
425
426    platform_set_drvdata(pdev, rbspi);
427
428    r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
429    if (r == NULL) {
430        err = -ENOENT;
431        goto err_clk_disable;
432    }
433
434    rbspi->base = ioremap(r->start, r->end - r->start + 1);
435    if (!rbspi->base) {
436        err = -ENXIO;
437        goto err_clk_disable;
438    }
439
440    rbspi->master = master;
441    rbspi->spi_ctrl_flash = get_spi_ctrl(rbspi, SPI_FLASH_HZ, "FLASH");
442    rbspi->spi_ctrl_fread = get_spi_ctrl(rbspi, SPI_CPLD_HZ, "CPLD");
443    rbspi->cs_wait = -1;
444
445    spin_lock_init(&rbspi->lock);
446    INIT_LIST_HEAD(&rbspi->queue);
447
448    err = spi_register_master(master);
449    if (err) {
450        dev_err(&pdev->dev, "failed to register SPI master\n");
451        goto err_iounmap;
452    }
453
454    return 0;
455
456err_iounmap:
457    iounmap(rbspi->base);
458err_clk_disable:
459    clk_disable(rbspi->ahb_clk);
460err_clk_put:
461    clk_put(rbspi->ahb_clk);
462err_put_master:
463    platform_set_drvdata(pdev, NULL);
464    spi_master_put(master);
465err_out:
466    return err;
467}
468
469static int rb4xx_spi_remove(struct platform_device *pdev)
470{
471    struct rb4xx_spi *rbspi = platform_get_drvdata(pdev);
472
473    iounmap(rbspi->base);
474    clk_disable(rbspi->ahb_clk);
475    clk_put(rbspi->ahb_clk);
476    platform_set_drvdata(pdev, NULL);
477    spi_master_put(rbspi->master);
478
479    return 0;
480}
481
482static struct platform_driver rb4xx_spi_drv = {
483    .probe = rb4xx_spi_probe,
484    .remove = rb4xx_spi_remove,
485    .driver = {
486        .name = DRV_NAME,
487        .owner = THIS_MODULE,
488    },
489};
490
491static int __init rb4xx_spi_init(void)
492{
493    return platform_driver_register(&rb4xx_spi_drv);
494}
495subsys_initcall(rb4xx_spi_init);
496
497static void __exit rb4xx_spi_exit(void)
498{
499    platform_driver_unregister(&rb4xx_spi_drv);
500}
501
502module_exit(rb4xx_spi_exit);
503
504MODULE_DESCRIPTION(DRV_DESC);
505MODULE_VERSION(DRV_VERSION);
506MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
507MODULE_LICENSE("GPL v2");
508

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