| 1 | From d258929cd4c8c495f619f0e66d9d1c23f3f9246f Mon Sep 17 00:00:00 2001 |
| 2 | From: Gabor Juhos <juhosg@openwrt.org> |
| 3 | Date: Tue, 26 Jun 2012 11:59:45 +0200 |
| 4 | Subject: [PATCH 12/34] MIPS: pci-ar724x: use per-controller IRQ base |
| 5 | |
| 6 | Signed-off-by: Gabor Juhos <juhosg@openwrt.org> |
| 7 | --- |
| 8 | arch/mips/pci/pci-ar724x.c | 31 +++++++++++++++++++++---------- |
| 9 | 1 files changed, 21 insertions(+), 10 deletions(-) |
| 10 | |
| 11 | --- a/arch/mips/pci/pci-ar724x.c |
| 12 | +++ b/arch/mips/pci/pci-ar724x.c |
| 13 | @@ -34,6 +34,7 @@ struct ar724x_pci_controller { |
| 14 | void __iomem *ctrl_base; |
| 15 | |
| 16 | int irq; |
| 17 | + int irq_base; |
| 18 | |
| 19 | bool link_up; |
| 20 | bool bar0_is_cached; |
| 21 | @@ -205,7 +206,7 @@ static void ar724x_pci_irq_handler(unsig |
| 22 | __raw_readl(base + AR724X_PCI_REG_INT_MASK); |
| 23 | |
| 24 | if (pending & AR724X_PCI_INT_DEV0) |
| 25 | - generic_handle_irq(ATH79_PCI_IRQ(0)); |
| 26 | + generic_handle_irq(apc->irq_base + 0); |
| 27 | |
| 28 | else |
| 29 | spurious_interrupt(); |
| 30 | @@ -215,13 +216,15 @@ static void ar724x_pci_irq_unmask(struct |
| 31 | { |
| 32 | struct ar724x_pci_controller *apc; |
| 33 | void __iomem *base; |
| 34 | + int offset; |
| 35 | u32 t; |
| 36 | |
| 37 | apc = irq_data_get_irq_chip_data(d); |
| 38 | base = apc->ctrl_base; |
| 39 | + offset = apc->irq_base - d->irq; |
| 40 | |
| 41 | - switch (d->irq) { |
| 42 | - case ATH79_PCI_IRQ(0): |
| 43 | + switch (offset) { |
| 44 | + case 0: |
| 45 | t = __raw_readl(base + AR724X_PCI_REG_INT_MASK); |
| 46 | __raw_writel(t | AR724X_PCI_INT_DEV0, |
| 47 | base + AR724X_PCI_REG_INT_MASK); |
| 48 | @@ -234,13 +237,15 @@ static void ar724x_pci_irq_mask(struct i |
| 49 | { |
| 50 | struct ar724x_pci_controller *apc; |
| 51 | void __iomem *base; |
| 52 | + int offset; |
| 53 | u32 t; |
| 54 | |
| 55 | apc = irq_data_get_irq_chip_data(d); |
| 56 | base = apc->ctrl_base; |
| 57 | + offset = apc->irq_base - d->irq; |
| 58 | |
| 59 | - switch (d->irq) { |
| 60 | - case ATH79_PCI_IRQ(0): |
| 61 | + switch (offset) { |
| 62 | + case 0: |
| 63 | t = __raw_readl(base + AR724X_PCI_REG_INT_MASK); |
| 64 | __raw_writel(t & ~AR724X_PCI_INT_DEV0, |
| 65 | base + AR724X_PCI_REG_INT_MASK); |
| 66 | @@ -264,7 +269,8 @@ static struct irq_chip ar724x_pci_irq_ch |
| 67 | .irq_mask_ack = ar724x_pci_irq_mask, |
| 68 | }; |
| 69 | |
| 70 | -static void __devinit ar724x_pci_irq_init(struct ar724x_pci_controller *apc) |
| 71 | +static void __devinit ar724x_pci_irq_init(struct ar724x_pci_controller *apc, |
| 72 | + int id) |
| 73 | { |
| 74 | void __iomem *base; |
| 75 | int i; |
| 76 | @@ -274,10 +280,10 @@ static void __devinit ar724x_pci_irq_ini |
| 77 | __raw_writel(0, base + AR724X_PCI_REG_INT_MASK); |
| 78 | __raw_writel(0, base + AR724X_PCI_REG_INT_STATUS); |
| 79 | |
| 80 | - BUILD_BUG_ON(ATH79_PCI_IRQ_COUNT < AR724X_PCI_IRQ_COUNT); |
| 81 | + apc->irq_base = ATH79_PCI_IRQ_BASE + (id * AR724X_PCI_IRQ_COUNT); |
| 82 | |
| 83 | - for (i = ATH79_PCI_IRQ_BASE; |
| 84 | - i < ATH79_PCI_IRQ_BASE + AR724X_PCI_IRQ_COUNT; i++) { |
| 85 | + for (i = apc->irq_base; |
| 86 | + i < apc->irq_base + AR724X_PCI_IRQ_COUNT; i++) { |
| 87 | irq_set_chip_and_handler(i, &ar724x_pci_irq_chip, |
| 88 | handle_level_irq); |
| 89 | irq_set_chip_data(i, apc); |
| 90 | @@ -291,6 +297,11 @@ static int __devinit ar724x_pci_probe(st |
| 91 | { |
| 92 | struct ar724x_pci_controller *apc; |
| 93 | struct resource *res; |
| 94 | + int id; |
| 95 | + |
| 96 | + id = pdev->id; |
| 97 | + if (id == -1) |
| 98 | + id = 0; |
| 99 | |
| 100 | apc = devm_kzalloc(&pdev->dev, sizeof(struct ar724x_pci_controller), |
| 101 | GFP_KERNEL); |
| 102 | @@ -347,7 +358,7 @@ static int __devinit ar724x_pci_probe(st |
| 103 | if (!apc->link_up) |
| 104 | dev_warn(&pdev->dev, "PCIe link is down\n"); |
| 105 | |
| 106 | - ar724x_pci_irq_init(apc); |
| 107 | + ar724x_pci_irq_init(apc, id); |
| 108 | |
| 109 | register_pci_controller(&apc->pci_controller); |
| 110 | |
| 111 | |
