| 1 | From c9a552f3007f0621b2440ae17bad816578299e52 Mon Sep 17 00:00:00 2001 |
| 2 | From: Gabor Juhos <juhosg@openwrt.org> |
| 3 | Date: Sun, 24 Jun 2012 13:45:27 +0200 |
| 4 | Subject: [PATCH 20/34] MIPS: ath79: add GPIO setup code for the QCA955X SoCs |
| 5 | |
| 6 | Signed-off-by: Gabor Juhos <juhosg@openwrt.org> |
| 7 | --- |
| 8 | arch/mips/ath79/gpio.c | 4 +++- |
| 9 | arch/mips/include/asm/mach-ath79/ar71xx_regs.h | 1 + |
| 10 | 2 files changed, 4 insertions(+), 1 deletions(-) |
| 11 | |
| 12 | --- a/arch/mips/ath79/gpio.c |
| 13 | +++ b/arch/mips/ath79/gpio.c |
| 14 | @@ -198,12 +198,14 @@ void __init ath79_gpio_init(void) |
| 15 | ath79_gpio_count = AR933X_GPIO_COUNT; |
| 16 | else if (soc_is_ar934x()) |
| 17 | ath79_gpio_count = AR934X_GPIO_COUNT; |
| 18 | + else if (soc_is_qca955x()) |
| 19 | + ath79_gpio_count = QCA955X_GPIO_COUNT; |
| 20 | else |
| 21 | BUG(); |
| 22 | |
| 23 | ath79_gpio_base = ioremap_nocache(AR71XX_GPIO_BASE, AR71XX_GPIO_SIZE); |
| 24 | ath79_gpio_chip.ngpio = ath79_gpio_count; |
| 25 | - if (soc_is_ar934x()) { |
| 26 | + if (soc_is_ar934x() || soc_is_qca955x()) { |
| 27 | ath79_gpio_chip.direction_input = ar934x_gpio_direction_input; |
| 28 | ath79_gpio_chip.direction_output = ar934x_gpio_direction_output; |
| 29 | } |
| 30 | --- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h |
| 31 | +++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h |
| 32 | @@ -507,6 +507,7 @@ |
| 33 | #define AR913X_GPIO_COUNT 22 |
| 34 | #define AR933X_GPIO_COUNT 30 |
| 35 | #define AR934X_GPIO_COUNT 23 |
| 36 | +#define QCA955X_GPIO_COUNT 24 |
| 37 | |
| 38 | /* |
| 39 | * SRIF block |
| 40 | |
