| 1 | From 177dc53a07e2c660d1c1a6cec4576c802325e330 Mon Sep 17 00:00:00 2001 |
| 2 | From: Gabor Juhos <juhosg@openwrt.org> |
| 3 | Date: Wed, 14 Nov 2012 09:02:01 +0100 |
| 4 | Subject: [PATCH] MIPS: ath79: fix GPIO function selection for AR934x SoCs |
| 5 | |
| 6 | GPIO function selection is not working on the AR934x |
| 7 | SoCs because the offset of the function selection |
| 8 | register is different on those. |
| 9 | |
| 10 | Add a helper routine which returns the correct |
| 11 | register address based on the SoC type, and use |
| 12 | that in the 'ath79_gpio_function_*' routines. |
| 13 | |
| 14 | Signed-off-by: Gabor Juhos <juhosg@openwrt.org> |
| 15 | --- |
| 16 | arch/mips/ath79/gpio.c | 38 ++++++++++++++++-------- |
| 17 | arch/mips/include/asm/mach-ath79/ar71xx_regs.h | 2 ++ |
| 18 | 2 files changed, 28 insertions(+), 12 deletions(-) |
| 19 | |
| 20 | --- a/arch/mips/ath79/gpio.c |
| 21 | +++ b/arch/mips/ath79/gpio.c |
| 22 | @@ -137,47 +137,61 @@ static struct gpio_chip ath79_gpio_chip |
| 23 | .base = 0, |
| 24 | }; |
| 25 | |
| 26 | +static void __iomem *ath79_gpio_get_function_reg(void) |
| 27 | +{ |
| 28 | + u32 reg = 0; |
| 29 | + |
| 30 | + if (soc_is_ar71xx() || |
| 31 | + soc_is_ar724x() || |
| 32 | + soc_is_ar913x() || |
| 33 | + soc_is_ar933x()) |
| 34 | + reg = AR71XX_GPIO_REG_FUNC; |
| 35 | + else if (soc_is_ar934x()) |
| 36 | + reg = AR934X_GPIO_REG_FUNC; |
| 37 | + else |
| 38 | + BUG(); |
| 39 | + |
| 40 | + return ath79_gpio_base + reg; |
| 41 | +} |
| 42 | + |
| 43 | void ath79_gpio_function_enable(u32 mask) |
| 44 | { |
| 45 | - void __iomem *base = ath79_gpio_base; |
| 46 | + void __iomem *reg = ath79_gpio_get_function_reg(); |
| 47 | unsigned long flags; |
| 48 | |
| 49 | spin_lock_irqsave(&ath79_gpio_lock, flags); |
| 50 | |
| 51 | - __raw_writel(__raw_readl(base + AR71XX_GPIO_REG_FUNC) | mask, |
| 52 | - base + AR71XX_GPIO_REG_FUNC); |
| 53 | + __raw_writel(__raw_readl(reg) | mask, reg); |
| 54 | /* flush write */ |
| 55 | - __raw_readl(base + AR71XX_GPIO_REG_FUNC); |
| 56 | + __raw_readl(reg); |
| 57 | |
| 58 | spin_unlock_irqrestore(&ath79_gpio_lock, flags); |
| 59 | } |
| 60 | |
| 61 | void ath79_gpio_function_disable(u32 mask) |
| 62 | { |
| 63 | - void __iomem *base = ath79_gpio_base; |
| 64 | + void __iomem *reg = ath79_gpio_get_function_reg(); |
| 65 | unsigned long flags; |
| 66 | |
| 67 | spin_lock_irqsave(&ath79_gpio_lock, flags); |
| 68 | |
| 69 | - __raw_writel(__raw_readl(base + AR71XX_GPIO_REG_FUNC) & ~mask, |
| 70 | - base + AR71XX_GPIO_REG_FUNC); |
| 71 | + __raw_writel(__raw_readl(reg) & ~mask, reg); |
| 72 | /* flush write */ |
| 73 | - __raw_readl(base + AR71XX_GPIO_REG_FUNC); |
| 74 | + __raw_readl(reg); |
| 75 | |
| 76 | spin_unlock_irqrestore(&ath79_gpio_lock, flags); |
| 77 | } |
| 78 | |
| 79 | void ath79_gpio_function_setup(u32 set, u32 clear) |
| 80 | { |
| 81 | - void __iomem *base = ath79_gpio_base; |
| 82 | + void __iomem *reg = ath79_gpio_get_function_reg(); |
| 83 | unsigned long flags; |
| 84 | |
| 85 | spin_lock_irqsave(&ath79_gpio_lock, flags); |
| 86 | |
| 87 | - __raw_writel((__raw_readl(base + AR71XX_GPIO_REG_FUNC) & ~clear) | set, |
| 88 | - base + AR71XX_GPIO_REG_FUNC); |
| 89 | + __raw_writel((__raw_readl(reg) & ~clear) | set, reg); |
| 90 | /* flush write */ |
| 91 | - __raw_readl(base + AR71XX_GPIO_REG_FUNC); |
| 92 | + __raw_readl(reg); |
| 93 | |
| 94 | spin_unlock_irqrestore(&ath79_gpio_lock, flags); |
| 95 | } |
| 96 | --- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h |
| 97 | +++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h |
| 98 | @@ -520,6 +520,8 @@ |
| 99 | #define AR71XX_GPIO_REG_INT_ENABLE 0x24 |
| 100 | #define AR71XX_GPIO_REG_FUNC 0x28 |
| 101 | |
| 102 | +#define AR934X_GPIO_REG_FUNC 0x6c |
| 103 | + |
| 104 | #define AR71XX_GPIO_COUNT 16 |
| 105 | #define AR7240_GPIO_COUNT 18 |
| 106 | #define AR7241_GPIO_COUNT 20 |
| 107 | |
