Root/target/linux/ar71xx/patches-3.6/601-MIPS-ath79-add-more-register-defines.patch

1--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
2+++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
3@@ -21,6 +21,10 @@
4 #include <linux/bitops.h>
5 
6 #define AR71XX_APB_BASE 0x18000000
7+#define AR71XX_GE0_BASE 0x19000000
8+#define AR71XX_GE0_SIZE 0x10000
9+#define AR71XX_GE1_BASE 0x1a000000
10+#define AR71XX_GE1_SIZE 0x10000
11 #define AR71XX_EHCI_BASE 0x1b000000
12 #define AR71XX_EHCI_SIZE 0x1000
13 #define AR71XX_OHCI_BASE 0x1c000000
14@@ -40,6 +44,8 @@
15 #define AR71XX_PLL_SIZE 0x100
16 #define AR71XX_RESET_BASE (AR71XX_APB_BASE + 0x00060000)
17 #define AR71XX_RESET_SIZE 0x100
18+#define AR71XX_MII_BASE (AR71XX_APB_BASE + 0x00070000)
19+#define AR71XX_MII_SIZE 0x100
20 
21 #define AR71XX_PCI_MEM_BASE 0x10000000
22 #define AR71XX_PCI_MEM_SIZE 0x07000000
23@@ -82,17 +88,23 @@
24 
25 #define AR933X_UART_BASE (AR71XX_APB_BASE + 0x00020000)
26 #define AR933X_UART_SIZE 0x14
27+#define AR933X_GMAC_BASE (AR71XX_APB_BASE + 0x00070000)
28+#define AR933X_GMAC_SIZE 0x04
29 #define AR933X_WMAC_BASE (AR71XX_APB_BASE + 0x00100000)
30 #define AR933X_WMAC_SIZE 0x20000
31 #define AR933X_EHCI_BASE 0x1b000000
32 #define AR933X_EHCI_SIZE 0x1000
33 
34+#define AR934X_GMAC_BASE (AR71XX_APB_BASE + 0x00070000)
35+#define AR934X_GMAC_SIZE 0x14
36 #define AR934X_WMAC_BASE (AR71XX_APB_BASE + 0x00100000)
37 #define AR934X_WMAC_SIZE 0x20000
38 #define AR934X_SRIF_BASE (AR71XX_APB_BASE + 0x00116000)
39 #define AR934X_SRIF_SIZE 0x1000
40 #define AR934X_EHCI_BASE 0x1b000000
41 #define AR934X_EHCI_SIZE 0x200
42+#define AR934X_NFC_BASE 0x1b000200
43+#define AR934X_NFC_SIZE 0xb8
44 
45 #define QCA955X_PCI_MEM_BASE0 0x10000000
46 #define QCA955X_PCI_MEM_BASE1 0x12000000
47@@ -112,6 +124,10 @@
48 #define QCA955X_EHCI0_BASE 0x1b000000
49 #define QCA955X_EHCI1_BASE 0x1b400000
50 #define QCA955X_EHCI_SIZE 0x200
51+#define QCA955X_GMAC_BASE (AR71XX_APB_BASE + 0x00070000)
52+#define QCA955X_GMAC_SIZE 0x40
53+#define QCA955X_NFC_BASE 0x1b000200
54+#define QCA955X_NFC_SIZE 0xb8
55 
56 #define AR9300_OTP_BASE 0x14000
57 #define AR9300_OTP_STATUS 0x15f18
58@@ -175,6 +191,9 @@
59 #define AR71XX_AHB_DIV_SHIFT 20
60 #define AR71XX_AHB_DIV_MASK 0x7
61 
62+#define AR71XX_ETH0_PLL_SHIFT 17
63+#define AR71XX_ETH1_PLL_SHIFT 19
64+
65 #define AR724X_PLL_REG_CPU_CONFIG 0x00
66 #define AR724X_PLL_REG_PCIE_CONFIG 0x18
67 
68@@ -187,6 +206,8 @@
69 #define AR724X_DDR_DIV_SHIFT 22
70 #define AR724X_DDR_DIV_MASK 0x3
71 
72+#define AR7242_PLL_REG_ETH0_INT_CLOCK 0x2c
73+
74 #define AR913X_PLL_REG_CPU_CONFIG 0x00
75 #define AR913X_PLL_REG_ETH_CONFIG 0x04
76 #define AR913X_PLL_REG_ETH0_INT_CLOCK 0x14
77@@ -199,6 +220,9 @@
78 #define AR913X_AHB_DIV_SHIFT 19
79 #define AR913X_AHB_DIV_MASK 0x1
80 
81+#define AR913X_ETH0_PLL_SHIFT 20
82+#define AR913X_ETH1_PLL_SHIFT 22
83+
84 #define AR933X_PLL_CPU_CONFIG_REG 0x00
85 #define AR933X_PLL_CLOCK_CTRL_REG 0x08
86 
87@@ -220,6 +244,8 @@
88 #define AR934X_PLL_CPU_CONFIG_REG 0x00
89 #define AR934X_PLL_DDR_CONFIG_REG 0x04
90 #define AR934X_PLL_CPU_DDR_CLK_CTRL_REG 0x08
91+#define AR934X_PLL_SWITCH_CLOCK_CONTROL_REG 0x24
92+#define AR934X_PLL_ETH_XMII_CONTROL_REG 0x2c
93 
94 #define AR934X_PLL_CPU_CONFIG_NFRAC_SHIFT 0
95 #define AR934X_PLL_CPU_CONFIG_NFRAC_MASK 0x3f
96@@ -252,9 +278,13 @@
97 #define AR934X_PLL_CPU_DDR_CLK_CTRL_DDRCLK_FROM_DDRPLL BIT(21)
98 #define AR934X_PLL_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL BIT(24)
99 
100+#define AR934X_PLL_SWITCH_CLOCK_CONTROL_MDIO_CLK_SEL BIT(6)
101+
102 #define QCA955X_PLL_CPU_CONFIG_REG 0x00
103 #define QCA955X_PLL_DDR_CONFIG_REG 0x04
104 #define QCA955X_PLL_CLK_CTRL_REG 0x08
105+#define QCA955X_PLL_ETH_XMII_CONTROL_REG 0x28
106+#define QCA955X_PLL_ETH_SGMII_CONTROL_REG 0x48
107 
108 #define QCA955X_PLL_CPU_CONFIG_NFRAC_SHIFT 0
109 #define QCA955X_PLL_CPU_CONFIG_NFRAC_MASK 0x3f
110@@ -378,16 +408,83 @@
111 #define AR913X_RESET_USB_HOST BIT(5)
112 #define AR913X_RESET_USB_PHY BIT(4)
113 
114+#define AR933X_RESET_GE1_MDIO BIT(23)
115+#define AR933X_RESET_GE0_MDIO BIT(22)
116+#define AR933X_RESET_GE1_MAC BIT(13)
117 #define AR933X_RESET_WMAC BIT(11)
118+#define AR933X_RESET_GE0_MAC BIT(9)
119 #define AR933X_RESET_USB_HOST BIT(5)
120 #define AR933X_RESET_USB_PHY BIT(4)
121 #define AR933X_RESET_USBSUS_OVERRIDE BIT(3)
122 
123+#define AR934X_RESET_HOST BIT(31)
124+#define AR934X_RESET_SLIC BIT(30)
125+#define AR934X_RESET_HDMA BIT(29)
126+#define AR934X_RESET_EXTERNAL BIT(28)
127+#define AR934X_RESET_RTC BIT(27)
128+#define AR934X_RESET_PCIE_EP_INT BIT(26)
129+#define AR934X_RESET_CHKSUM_ACC BIT(25)
130+#define AR934X_RESET_FULL_CHIP BIT(24)
131+#define AR934X_RESET_GE1_MDIO BIT(23)
132+#define AR934X_RESET_GE0_MDIO BIT(22)
133+#define AR934X_RESET_CPU_NMI BIT(21)
134+#define AR934X_RESET_CPU_COLD BIT(20)
135+#define AR934X_RESET_HOST_RESET_INT BIT(19)
136+#define AR934X_RESET_PCIE_EP BIT(18)
137+#define AR934X_RESET_UART1 BIT(17)
138+#define AR934X_RESET_DDR BIT(16)
139+#define AR934X_RESET_USB_PHY_PLL_PWD_EXT BIT(15)
140+#define AR934X_RESET_NANDF BIT(14)
141+#define AR934X_RESET_GE1_MAC BIT(13)
142+#define AR934X_RESET_ETH_SWITCH_ANALOG BIT(12)
143 #define AR934X_RESET_USB_PHY_ANALOG BIT(11)
144+#define AR934X_RESET_HOST_DMA_INT BIT(10)
145+#define AR934X_RESET_GE0_MAC BIT(9)
146+#define AR934X_RESET_ETH_SWITCH BIT(8)
147+#define AR934X_RESET_PCIE_PHY BIT(7)
148+#define AR934X_RESET_PCIE BIT(6)
149 #define AR934X_RESET_USB_HOST BIT(5)
150 #define AR934X_RESET_USB_PHY BIT(4)
151 #define AR934X_RESET_USBSUS_OVERRIDE BIT(3)
152+#define AR934X_RESET_LUT BIT(2)
153+#define AR934X_RESET_MBOX BIT(1)
154+#define AR934X_RESET_I2S BIT(0)
155+
156+#define QCA955X_RESET_HOST BIT(31)
157+#define QCA955X_RESET_SLIC BIT(30)
158+#define QCA955X_RESET_HDMA BIT(29)
159+#define QCA955X_RESET_EXTERNAL BIT(28)
160+#define QCA955X_RESET_RTC BIT(27)
161+#define QCA955X_RESET_PCIE_EP_INT BIT(26)
162+#define QCA955X_RESET_CHKSUM_ACC BIT(25)
163+#define QCA955X_RESET_FULL_CHIP BIT(24)
164+#define QCA955X_RESET_GE1_MDIO BIT(23)
165+#define QCA955X_RESET_GE0_MDIO BIT(22)
166+#define QCA955X_RESET_CPU_NMI BIT(21)
167+#define QCA955X_RESET_CPU_COLD BIT(20)
168+#define QCA955X_RESET_HOST_RESET_INT BIT(19)
169+#define QCA955X_RESET_PCIE_EP BIT(18)
170+#define QCA955X_RESET_UART1 BIT(17)
171+#define QCA955X_RESET_DDR BIT(16)
172+#define QCA955X_RESET_USB_PHY_PLL_PWD_EXT BIT(15)
173+#define QCA955X_RESET_NANDF BIT(14)
174+#define QCA955X_RESET_GE1_MAC BIT(13)
175+#define QCA955X_RESET_SGMII_ANALOG BIT(12)
176+#define QCA955X_RESET_USB_PHY_ANALOG BIT(11)
177+#define QCA955X_RESET_HOST_DMA_INT BIT(10)
178+#define QCA955X_RESET_GE0_MAC BIT(9)
179+#define QCA955X_RESET_SGMII BIT(8)
180+#define QCA955X_RESET_PCIE_PHY BIT(7)
181+#define QCA955X_RESET_PCIE BIT(6)
182+#define QCA955X_RESET_USB_HOST BIT(5)
183+#define QCA955X_RESET_USB_PHY BIT(4)
184+#define QCA955X_RESET_USBSUS_OVERRIDE BIT(3)
185+#define QCA955X_RESET_LUT BIT(2)
186+#define QCA955X_RESET_MBOX BIT(1)
187+#define QCA955X_RESET_I2S BIT(0)
188 
189+#define AR933X_BOOTSTRAP_MDIO_GPIO_EN BIT(18)
190+#define AR933X_BOOTSTRAP_EEPBUSY BIT(4)
191 #define AR933X_BOOTSTRAP_REF_CLK_40 BIT(0)
192 
193 #define AR934X_BOOTSTRAP_SW_OPTION8 BIT(23)
194@@ -528,6 +625,12 @@
195 #define AR71XX_GPIO_REG_INT_ENABLE 0x24
196 #define AR71XX_GPIO_REG_FUNC 0x28
197 
198+#define AR934X_GPIO_REG_OUT_FUNC0 0x2c
199+#define AR934X_GPIO_REG_OUT_FUNC1 0x30
200+#define AR934X_GPIO_REG_OUT_FUNC2 0x34
201+#define AR934X_GPIO_REG_OUT_FUNC3 0x38
202+#define AR934X_GPIO_REG_OUT_FUNC4 0x3c
203+#define AR934X_GPIO_REG_OUT_FUNC5 0x40
204 #define AR934X_GPIO_REG_FUNC 0x6c
205 
206 #define AR71XX_GPIO_COUNT 16
207@@ -559,4 +662,133 @@
208 #define AR934X_SRIF_DPLL2_OUTDIV_SHIFT 13
209 #define AR934X_SRIF_DPLL2_OUTDIV_MASK 0x7
210 
211+#define AR71XX_GPIO_FUNC_STEREO_EN BIT(17)
212+#define AR71XX_GPIO_FUNC_SLIC_EN BIT(16)
213+#define AR71XX_GPIO_FUNC_SPI_CS2_EN BIT(13)
214+#define AR71XX_GPIO_FUNC_SPI_CS1_EN BIT(12)
215+#define AR71XX_GPIO_FUNC_UART_EN BIT(8)
216+#define AR71XX_GPIO_FUNC_USB_OC_EN BIT(4)
217+#define AR71XX_GPIO_FUNC_USB_CLK_EN BIT(0)
218+
219+#define AR724X_GPIO_FUNC_GE0_MII_CLK_EN BIT(19)
220+#define AR724X_GPIO_FUNC_SPI_EN BIT(18)
221+#define AR724X_GPIO_FUNC_SPI_CS_EN2 BIT(14)
222+#define AR724X_GPIO_FUNC_SPI_CS_EN1 BIT(13)
223+#define AR724X_GPIO_FUNC_CLK_OBS5_EN BIT(12)
224+#define AR724X_GPIO_FUNC_CLK_OBS4_EN BIT(11)
225+#define AR724X_GPIO_FUNC_CLK_OBS3_EN BIT(10)
226+#define AR724X_GPIO_FUNC_CLK_OBS2_EN BIT(9)
227+#define AR724X_GPIO_FUNC_CLK_OBS1_EN BIT(8)
228+#define AR724X_GPIO_FUNC_ETH_SWITCH_LED4_EN BIT(7)
229+#define AR724X_GPIO_FUNC_ETH_SWITCH_LED3_EN BIT(6)
230+#define AR724X_GPIO_FUNC_ETH_SWITCH_LED2_EN BIT(5)
231+#define AR724X_GPIO_FUNC_ETH_SWITCH_LED1_EN BIT(4)
232+#define AR724X_GPIO_FUNC_ETH_SWITCH_LED0_EN BIT(3)
233+#define AR724X_GPIO_FUNC_UART_RTS_CTS_EN BIT(2)
234+#define AR724X_GPIO_FUNC_UART_EN BIT(1)
235+#define AR724X_GPIO_FUNC_JTAG_DISABLE BIT(0)
236+
237+#define AR913X_GPIO_FUNC_WMAC_LED_EN BIT(22)
238+#define AR913X_GPIO_FUNC_EXP_PORT_CS_EN BIT(21)
239+#define AR913X_GPIO_FUNC_I2S_REFCLKEN BIT(20)
240+#define AR913X_GPIO_FUNC_I2S_MCKEN BIT(19)
241+#define AR913X_GPIO_FUNC_I2S1_EN BIT(18)
242+#define AR913X_GPIO_FUNC_I2S0_EN BIT(17)
243+#define AR913X_GPIO_FUNC_SLIC_EN BIT(16)
244+#define AR913X_GPIO_FUNC_UART_RTSCTS_EN BIT(9)
245+#define AR913X_GPIO_FUNC_UART_EN BIT(8)
246+#define AR913X_GPIO_FUNC_USB_CLK_EN BIT(4)
247+
248+#define AR933X_GPIO_FUNC_SPDIF2TCK BIT(31)
249+#define AR933X_GPIO_FUNC_SPDIF_EN BIT(30)
250+#define AR933X_GPIO_FUNC_I2SO_22_18_EN BIT(29)
251+#define AR933X_GPIO_FUNC_I2S_MCK_EN BIT(27)
252+#define AR933X_GPIO_FUNC_I2SO_EN BIT(26)
253+#define AR933X_GPIO_FUNC_ETH_SWITCH_LED_DUPL BIT(25)
254+#define AR933X_GPIO_FUNC_ETH_SWITCH_LED_COLL BIT(24)
255+#define AR933X_GPIO_FUNC_ETH_SWITCH_LED_ACT BIT(23)
256+#define AR933X_GPIO_FUNC_SPI_EN BIT(18)
257+#define AR933X_GPIO_FUNC_SPI_CS_EN2 BIT(14)
258+#define AR933X_GPIO_FUNC_SPI_CS_EN1 BIT(13)
259+#define AR933X_GPIO_FUNC_ETH_SWITCH_LED4_EN BIT(7)
260+#define AR933X_GPIO_FUNC_ETH_SWITCH_LED3_EN BIT(6)
261+#define AR933X_GPIO_FUNC_ETH_SWITCH_LED2_EN BIT(5)
262+#define AR933X_GPIO_FUNC_ETH_SWITCH_LED1_EN BIT(4)
263+#define AR933X_GPIO_FUNC_ETH_SWITCH_LED0_EN BIT(3)
264+#define AR933X_GPIO_FUNC_UART_RTS_CTS_EN BIT(2)
265+#define AR933X_GPIO_FUNC_UART_EN BIT(1)
266+#define AR933X_GPIO_FUNC_JTAG_DISABLE BIT(0)
267+
268+#define AR934X_GPIO_FUNC_DDR_DQOE_EN BIT(17)
269+#define AR934X_GPIO_FUNC_SPI_CS_1_EN BIT(14)
270+#define AR934X_GPIO_FUNC_SPI_CS_0_EN BIT(13)
271+
272+#define AR934X_GPIO_OUT_GPIO 0x00
273+
274+/*
275+ * MII_CTRL block
276+ */
277+#define AR71XX_MII_REG_MII0_CTRL 0x00
278+#define AR71XX_MII_REG_MII1_CTRL 0x04
279+
280+#define AR71XX_MII_CTRL_IF_MASK 3
281+#define AR71XX_MII_CTRL_SPEED_SHIFT 4
282+#define AR71XX_MII_CTRL_SPEED_MASK 3
283+#define AR71XX_MII_CTRL_SPEED_10 0
284+#define AR71XX_MII_CTRL_SPEED_100 1
285+#define AR71XX_MII_CTRL_SPEED_1000 2
286+
287+#define AR71XX_MII0_CTRL_IF_GMII 0
288+#define AR71XX_MII0_CTRL_IF_MII 1
289+#define AR71XX_MII0_CTRL_IF_RGMII 2
290+#define AR71XX_MII0_CTRL_IF_RMII 3
291+
292+#define AR71XX_MII1_CTRL_IF_RGMII 0
293+#define AR71XX_MII1_CTRL_IF_RMII 1
294+
295+/*
296+ * AR933X GMAC interface
297+ */
298+#define AR933X_GMAC_REG_ETH_CFG 0x00
299+
300+#define AR933X_ETH_CFG_RGMII_GE0 BIT(0)
301+#define AR933X_ETH_CFG_MII_GE0 BIT(1)
302+#define AR933X_ETH_CFG_GMII_GE0 BIT(2)
303+#define AR933X_ETH_CFG_MII_GE0_MASTER BIT(3)
304+#define AR933X_ETH_CFG_MII_GE0_SLAVE BIT(4)
305+#define AR933X_ETH_CFG_MII_GE0_ERR_EN BIT(5)
306+#define AR933X_ETH_CFG_SW_PHY_SWAP BIT(7)
307+#define AR933X_ETH_CFG_SW_PHY_ADDR_SWAP BIT(8)
308+#define AR933X_ETH_CFG_RMII_GE0 BIT(9)
309+#define AR933X_ETH_CFG_RMII_GE0_SPD_10 0
310+#define AR933X_ETH_CFG_RMII_GE0_SPD_100 BIT(10)
311+
312+/*
313+ * AR934X GMAC Interface
314+ */
315+#define AR934X_GMAC_REG_ETH_CFG 0x00
316+
317+#define AR934X_ETH_CFG_RGMII_GMAC0 BIT(0)
318+#define AR934X_ETH_CFG_MII_GMAC0 BIT(1)
319+#define AR934X_ETH_CFG_GMII_GMAC0 BIT(2)
320+#define AR934X_ETH_CFG_MII_GMAC0_MASTER BIT(3)
321+#define AR934X_ETH_CFG_MII_GMAC0_SLAVE BIT(4)
322+#define AR934X_ETH_CFG_MII_GMAC0_ERR_EN BIT(5)
323+#define AR934X_ETH_CFG_SW_ONLY_MODE BIT(6)
324+#define AR934X_ETH_CFG_SW_PHY_SWAP BIT(7)
325+#define AR934X_ETH_CFG_SW_APB_ACCESS BIT(9)
326+#define AR934X_ETH_CFG_RMII_GMAC0 BIT(10)
327+#define AR933X_ETH_CFG_MII_CNTL_SPEED BIT(11)
328+#define AR934X_ETH_CFG_RMII_GMAC0_MASTER BIT(12)
329+#define AR933X_ETH_CFG_SW_ACC_MSB_FIRST BIT(13)
330+
331+/*
332+ * QCA955X GMAC Interface
333+ */
334+
335+#define QCA955X_GMAC_REG_ETH_CFG 0x00
336+
337+#define QCA955X_ETH_CFG_RGMII_EN BIT(0)
338+#define QCA955X_ETH_CFG_GE0_SGMII BIT(6)
339+
340 #endif /* __ASM_MACH_AR71XX_REGS_H */
341

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