| 1 | --- a/arch/mips/ath79/mach-ap136.c |
| 2 | +++ b/arch/mips/ath79/mach-ap136.c |
| 3 | @@ -1,5 +1,5 @@ |
| 4 | /* |
| 5 | - * Qualcomm Atheros AP136 reference board support |
| 6 | + * Atheros AP136 reference board support |
| 7 | * |
| 8 | * Copyright (c) 2012 Qualcomm Atheros |
| 9 | * Copyright (c) 2012 Gabor Juhos <juhosg@openwrt.org> |
| 10 | @@ -18,23 +18,27 @@ |
| 11 | * |
| 12 | */ |
| 13 | |
| 14 | -#include <linux/pci.h> |
| 15 | -#include <linux/ath9k_platform.h> |
| 16 | +#include <linux/platform_device.h> |
| 17 | +#include <linux/ar8216_platform.h> |
| 18 | |
| 19 | -#include "machtypes.h" |
| 20 | +#include <asm/mach-ath79/ar71xx_regs.h> |
| 21 | + |
| 22 | +#include "common.h" |
| 23 | +#include "dev-ap9x-pci.h" |
| 24 | #include "dev-gpio-buttons.h" |
| 25 | +#include "dev-eth.h" |
| 26 | #include "dev-leds-gpio.h" |
| 27 | -#include "dev-spi.h" |
| 28 | +#include "dev-m25p80.h" |
| 29 | #include "dev-usb.h" |
| 30 | #include "dev-wmac.h" |
| 31 | -#include "pci.h" |
| 32 | +#include "machtypes.h" |
| 33 | |
| 34 | -#define AP136_GPIO_LED_STATUS_RED 14 |
| 35 | -#define AP136_GPIO_LED_STATUS_GREEN 19 |
| 36 | #define AP136_GPIO_LED_USB 4 |
| 37 | -#define AP136_GPIO_LED_WLAN_2G 13 |
| 38 | #define AP136_GPIO_LED_WLAN_5G 12 |
| 39 | +#define AP136_GPIO_LED_WLAN_2G 13 |
| 40 | +#define AP136_GPIO_LED_STATUS_RED 14 |
| 41 | #define AP136_GPIO_LED_WPS_RED 15 |
| 42 | +#define AP136_GPIO_LED_STATUS_GREEN 19 |
| 43 | #define AP136_GPIO_LED_WPS_GREEN 20 |
| 44 | |
| 45 | #define AP136_GPIO_BTN_WPS 16 |
| 46 | @@ -43,8 +47,10 @@ |
| 47 | #define AP136_KEYS_POLL_INTERVAL 20 /* msecs */ |
| 48 | #define AP136_KEYS_DEBOUNCE_INTERVAL (3 * AP136_KEYS_POLL_INTERVAL) |
| 49 | |
| 50 | -#define AP136_WMAC_CALDATA_OFFSET 0x1000 |
| 51 | -#define AP136_PCIE_CALDATA_OFFSET 0x5000 |
| 52 | +#define AP136_MAC0_OFFSET 0 |
| 53 | +#define AP136_MAC1_OFFSET 6 |
| 54 | +#define AP136_WMAC_CALDATA_OFFSET 0x1000 |
| 55 | +#define AP136_PCIE_CALDATA_OFFSET 0x5000 |
| 56 | |
| 57 | static struct gpio_led ap136_leds_gpio[] __initdata = { |
| 58 | { |
| 59 | @@ -98,64 +104,136 @@ static struct gpio_keys_button ap136_gpi |
| 60 | }, |
| 61 | }; |
| 62 | |
| 63 | -static struct ath79_spi_controller_data ap136_spi0_data = { |
| 64 | - .cs_type = ATH79_SPI_CS_TYPE_INTERNAL, |
| 65 | - .cs_line = 0, |
| 66 | +static struct ar8327_pad_cfg ap136_ar8327_pad0_cfg; |
| 67 | +static struct ar8327_pad_cfg ap136_ar8327_pad6_cfg; |
| 68 | + |
| 69 | +static struct ar8327_platform_data ap136_ar8327_data = { |
| 70 | + .pad0_cfg = &ap136_ar8327_pad0_cfg, |
| 71 | + .pad6_cfg = &ap136_ar8327_pad6_cfg, |
| 72 | + .port0_cfg = { |
| 73 | + .force_link = 1, |
| 74 | + .speed = AR8327_PORT_SPEED_1000, |
| 75 | + .duplex = 1, |
| 76 | + .txpause = 1, |
| 77 | + .rxpause = 1, |
| 78 | + }, |
| 79 | + .port6_cfg = { |
| 80 | + .force_link = 1, |
| 81 | + .speed = AR8327_PORT_SPEED_1000, |
| 82 | + .duplex = 1, |
| 83 | + .txpause = 1, |
| 84 | + .rxpause = 1, |
| 85 | + }, |
| 86 | }; |
| 87 | |
| 88 | -static struct spi_board_info ap136_spi_info[] = { |
| 89 | +static struct mdio_board_info ap136_mdio0_info[] = { |
| 90 | { |
| 91 | - .bus_num = 0, |
| 92 | - .chip_select = 0, |
| 93 | - .max_speed_hz = 25000000, |
| 94 | - .modalias = "mx25l6405d", |
| 95 | - .controller_data = &ap136_spi0_data, |
| 96 | - } |
| 97 | + .bus_id = "ag71xx-mdio.0", |
| 98 | + .phy_addr = 0, |
| 99 | + .platform_data = &ap136_ar8327_data, |
| 100 | + }, |
| 101 | }; |
| 102 | |
| 103 | -static struct ath79_spi_platform_data ap136_spi_data = { |
| 104 | - .bus_num = 0, |
| 105 | - .num_chipselect = 1, |
| 106 | -}; |
| 107 | +static void __init ap136_gmac_setup(void) |
| 108 | +{ |
| 109 | + void __iomem *base; |
| 110 | + u32 t; |
| 111 | |
| 112 | -#ifdef CONFIG_PCI |
| 113 | -static struct ath9k_platform_data ap136_ath9k_data; |
| 114 | + base = ioremap(QCA955X_GMAC_BASE, QCA955X_GMAC_SIZE); |
| 115 | |
| 116 | -static int ap136_pci_plat_dev_init(struct pci_dev *dev) |
| 117 | -{ |
| 118 | - if (dev->bus->number == 1 && (PCI_SLOT(dev->devfn)) == 0) |
| 119 | - dev->dev.platform_data = &ap136_ath9k_data; |
| 120 | + t = __raw_readl(base + QCA955X_GMAC_REG_ETH_CFG); |
| 121 | |
| 122 | - return 0; |
| 123 | -} |
| 124 | + t &= ~(QCA955X_ETH_CFG_RGMII_EN | QCA955X_ETH_CFG_GE0_SGMII); |
| 125 | + t |= QCA955X_ETH_CFG_RGMII_EN; |
| 126 | |
| 127 | -static void __init ap136_pci_init(u8 *eeprom) |
| 128 | -{ |
| 129 | - memcpy(ap136_ath9k_data.eeprom_data, eeprom, |
| 130 | - sizeof(ap136_ath9k_data.eeprom_data)); |
| 131 | + __raw_writel(t, base + QCA955X_GMAC_REG_ETH_CFG); |
| 132 | |
| 133 | - ath79_pci_set_plat_dev_init(ap136_pci_plat_dev_init); |
| 134 | - ath79_register_pci(); |
| 135 | + iounmap(base); |
| 136 | } |
| 137 | -#else |
| 138 | -static inline void ap136_pci_init(void) {} |
| 139 | -#endif /* CONFIG_PCI */ |
| 140 | |
| 141 | -static void __init ap136_setup(void) |
| 142 | +static void __init ap136_common_setup(void) |
| 143 | { |
| 144 | u8 *art = (u8 *) KSEG1ADDR(0x1fff0000); |
| 145 | |
| 146 | + ath79_register_m25p80(NULL); |
| 147 | + |
| 148 | ath79_register_leds_gpio(-1, ARRAY_SIZE(ap136_leds_gpio), |
| 149 | ap136_leds_gpio); |
| 150 | ath79_register_gpio_keys_polled(-1, AP136_KEYS_POLL_INTERVAL, |
| 151 | ARRAY_SIZE(ap136_gpio_keys), |
| 152 | ap136_gpio_keys); |
| 153 | - ath79_register_spi(&ap136_spi_data, ap136_spi_info, |
| 154 | - ARRAY_SIZE(ap136_spi_info)); |
| 155 | + |
| 156 | ath79_register_usb(); |
| 157 | - ath79_register_wmac(art + AP136_WMAC_CALDATA_OFFSET); |
| 158 | - ap136_pci_init(art + AP136_PCIE_CALDATA_OFFSET); |
| 159 | + ath79_register_wmac(art + AP136_WMAC_CALDATA_OFFSET, NULL); |
| 160 | + ap91_pci_init(art + AP136_PCIE_CALDATA_OFFSET, NULL); |
| 161 | + |
| 162 | + ap136_gmac_setup(); |
| 163 | + |
| 164 | + ath79_register_mdio(0, 0x0); |
| 165 | + |
| 166 | + ath79_init_mac(ath79_eth0_data.mac_addr, art + AP136_MAC0_OFFSET, 0); |
| 167 | + |
| 168 | + mdiobus_register_board_info(ap136_mdio0_info, |
| 169 | + ARRAY_SIZE(ap136_mdio0_info)); |
| 170 | + |
| 171 | + /* GMAC0 is connected to the RMGII interface */ |
| 172 | + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; |
| 173 | + ath79_eth0_data.phy_mask = BIT(0); |
| 174 | + ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev; |
| 175 | + |
| 176 | + ath79_register_eth(0); |
| 177 | + |
| 178 | + /* GMAC1 is connected tot eh SGMII interface */ |
| 179 | + ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_SGMII; |
| 180 | + ath79_eth1_data.speed = SPEED_1000; |
| 181 | + ath79_eth1_data.duplex = DUPLEX_FULL; |
| 182 | + |
| 183 | + ath79_register_eth(1); |
| 184 | +} |
| 185 | + |
| 186 | +static void __init ap136_010_setup(void) |
| 187 | +{ |
| 188 | + /* GMAC0 of the AR8327 switch is connected to GMAC0 via RGMII */ |
| 189 | + ap136_ar8327_pad0_cfg.mode = AR8327_PAD_MAC_RGMII; |
| 190 | + ap136_ar8327_pad0_cfg.txclk_delay_en = true; |
| 191 | + ap136_ar8327_pad0_cfg.rxclk_delay_en = true; |
| 192 | + ap136_ar8327_pad0_cfg.txclk_delay_sel = AR8327_CLK_DELAY_SEL1; |
| 193 | + ap136_ar8327_pad0_cfg.rxclk_delay_sel = AR8327_CLK_DELAY_SEL2; |
| 194 | + |
| 195 | + /* GMAC6 of the AR8327 switch is connected to GMAC1 via SGMII */ |
| 196 | + ap136_ar8327_pad6_cfg.mode = AR8327_PAD_MAC_SGMII; |
| 197 | + ap136_ar8327_pad6_cfg.rxclk_delay_en = true; |
| 198 | + ap136_ar8327_pad6_cfg.rxclk_delay_sel = AR8327_CLK_DELAY_SEL0; |
| 199 | + |
| 200 | + ath79_eth0_pll_data.pll_1000 = 0xa6000000; |
| 201 | + ath79_eth1_pll_data.pll_1000 = 0x03000101; |
| 202 | + |
| 203 | + ap136_common_setup(); |
| 204 | +} |
| 205 | + |
| 206 | +MIPS_MACHINE(ATH79_MACH_AP136_010, "AP136-010", |
| 207 | + "Atheros AP136-010 reference board", |
| 208 | + ap136_010_setup); |
| 209 | + |
| 210 | +static void __init ap136_020_setup(void) |
| 211 | +{ |
| 212 | + /* GMAC0 of the AR8327 switch is connected to GMAC1 via SGMII */ |
| 213 | + ap136_ar8327_pad0_cfg.mode = AR8327_PAD_MAC_SGMII; |
| 214 | + ap136_ar8327_pad0_cfg.sgmii_delay_en = true; |
| 215 | + |
| 216 | + /* GMAC6 of the AR8327 switch is connected to GMAC0 via RGMII */ |
| 217 | + ap136_ar8327_pad6_cfg.mode = AR8327_PAD_MAC_RGMII; |
| 218 | + ap136_ar8327_pad6_cfg.txclk_delay_en = true; |
| 219 | + ap136_ar8327_pad6_cfg.rxclk_delay_en = true; |
| 220 | + ap136_ar8327_pad6_cfg.txclk_delay_sel = AR8327_CLK_DELAY_SEL1; |
| 221 | + ap136_ar8327_pad6_cfg.rxclk_delay_sel = AR8327_CLK_DELAY_SEL2; |
| 222 | + |
| 223 | + ath79_eth0_pll_data.pll_1000 = 0x56000000; |
| 224 | + ath79_eth1_pll_data.pll_1000 = 0x03000101; |
| 225 | + |
| 226 | + ap136_common_setup(); |
| 227 | } |
| 228 | |
| 229 | -MIPS_MACHINE(ATH79_MACH_AP136, "AP136", "Atheros AP136 reference board", |
| 230 | - ap136_setup); |
| 231 | +MIPS_MACHINE(ATH79_MACH_AP136_020, "AP136-020", |
| 232 | + "Atheros AP136-020 reference board", |
| 233 | + ap136_020_setup); |
| 234 | --- a/arch/mips/ath79/machtypes.h |
| 235 | +++ b/arch/mips/ath79/machtypes.h |
| 236 | @@ -18,7 +18,8 @@ enum ath79_mach_type { |
| 237 | ATH79_MACH_GENERIC = 0, |
| 238 | ATH79_MACH_AP121, /* Atheros AP121 reference board */ |
| 239 | ATH79_MACH_AP121_MINI, /* Atheros AP121-MINI reference board */ |
| 240 | - ATH79_MACH_AP136, /* Atheros AP136 reference board */ |
| 241 | + ATH79_MACH_AP136_010, /* Atheros AP136-010 reference board */ |
| 242 | + ATH79_MACH_AP136_020, /* Atheros AP136-020 reference board */ |
| 243 | ATH79_MACH_AP81, /* Atheros AP81 reference board */ |
| 244 | ATH79_MACH_DB120, /* Atheros DB120 reference board */ |
| 245 | ATH79_MACH_PB44, /* Atheros PB44 reference board */ |
| 246 | |
