Root/target/linux/at91/image/dfboot/src/cstartup_ram.S

1#include "AT91RM9200_inc.h"
2        
3/*---------------------------
4ARM Core Mode and Status Bits
5---------------------------*/
6.section start
7    .text
8            
9#define ARM_MODE_USER 0x10
10#define ARM_MODE_FIQ 0x11
11#define ARM_MODE_IRQ 0x12
12#define ARM_MODE_SVC 0x13
13#define ARM_MODE_ABORT 0x17
14#define ARM_MODE_UNDEF 0x1B
15#define ARM_MODE_SYS 0x1F
16
17#define I_BIT 0x80
18#define F_BIT 0x40
19#define T_BIT 0x20
20
21/*----------------------------------------------------------------------------
22 Area Definition
23----------------
24 Must be defined as function to put first in the code as it must be mapped
25 at offset 0 of the flash EBI_CSR0, ie. at address 0 before remap.
26_---------------------------------------------------------------------------*/
27
28  .align 4
29    .globl _start
30_start:
31
32/*----------------------------------------------------------------------------
33 Exception vectors ( before Remap )
34------------------------------------
35 These vectors are read at address 0.
36 They absolutely requires to be in relative addresssing mode in order to
37 guarantee a valid jump. For the moment, all are just looping (what may be
38 dangerous in a final system). If an exception occurs before remap, this
39 would result in an infinite loop.
40----------------------------------------------------------------------------*/
41                b reset /* reset */
42                b undefvec /* Undefined Instruction */
43                b swivec /* Software Interrupt */
44                b pabtvec /* Prefetch Abort */
45                b dabtvec /* Data Abort */
46                b rsvdvec /* reserved */
47                b aicvec /* IRQ : read the AIC */
48                b fiqvec /* FIQ */
49
50undefvec:
51swivec:
52pabtvec:
53dabtvec:
54rsvdvec:
55aicvec:
56fiqvec:
57    b undefvec
58
59reset:
60
61#define MEMEND 0x00004000
62
63/* ----------------------------
64 Setup the stack for each mode
65---------------------------- */
66
67#define IRQ_STACK_SIZE 0x10
68#define FIQ_STACK_SIZE 0x04
69#define ABT_STACK_SIZE 0x04
70#define UND_STACK_SIZE 0x04
71#define SVC_STACK_SIZE 0x10
72#define USER_STACK_SIZE 0x400
73    
74                ldr r0,= MEMEND
75
76/*- Set up Supervisor Mode and set Supervisor Mode Stack*/
77                msr CPSR_c, #ARM_MODE_SVC | I_BIT | F_BIT
78                mov r13, r0 /* Init stack Undef*/
79                sub r0, r0, #SVC_STACK_SIZE
80
81/*- Set up Interrupt Mode and set IRQ Mode Stack*/
82                msr CPSR_c, #ARM_MODE_IRQ | I_BIT | F_BIT
83                mov r13, r0 /* Init stack IRQ*/
84                sub r0, r0, #IRQ_STACK_SIZE
85
86/*- Set up Fast Interrupt Mode and set FIQ Mode Stack*/
87                msr CPSR_c, #ARM_MODE_FIQ | I_BIT | F_BIT
88                mov r13, r0 /* Init stack FIQ*/
89                sub r0, r0, #FIQ_STACK_SIZE
90
91/*- Set up Abort Mode and set Abort Mode Stack*/
92                msr CPSR_c, #ARM_MODE_ABORT | I_BIT | F_BIT
93                mov r13, r0 /* Init stack Abort*/
94                sub r0, r0, #ABT_STACK_SIZE
95
96/*- Set up Undefined Instruction Mode and set Undef Mode Stack*/
97                msr CPSR_c, #ARM_MODE_UNDEF | I_BIT | F_BIT
98                mov r13, r0 /* Init stack Undef*/
99                sub r0, r0, #UND_STACK_SIZE
100
101/*- Set up user Mode and set System Mode Stack*/
102                msr CPSR_c, #ARM_MODE_SYS | I_BIT | F_BIT
103                bic r0, r0, #3 /* Insure word alignement */
104                   mov sp, r0 /* Init stack System */
105
106
107        ldr r0, = AT91F_LowLevelInit
108        mov lr, pc
109        bx r0
110
111/*----------------------------------------
112 Read/modify/write CP15 control register
113----------------------------------------*/
114        mrc p15, 0, r0, c1, c0,0 /* read cp15 control registre (cp15 r1) in r0 */
115        ldr r3,= 0xC0000080 /* Reset bit :Little Endian end fast bus mode */
116        ldr r4,= 0xC0001000 /* Set bit :Asynchronous clock mode, Not Fast Bus, I-Cache enable */
117        bic r0, r0, r3
118        orr r0, r0, r4
119        mcr p15, 0, r0, c1, c0,0 /* write r0 in cp15 control registre (cp15 r1) */
120
121/* Enable interrupts */
122        msr CPSR_c, #ARM_MODE_SYS | F_BIT
123
124/*------------------------------------------------------------------------------
125- Branch on C code Main function (with interworking)
126----------------------------------------------------
127- Branch must be performed by an interworking call as either an ARM or Thumb
128- _start function must be supported. This makes the code not position-
129- independent. A Branch with link would generate errors
130----------------------------------------------------------------------------*/
131    
132/*- Branch to _start by interworking*/
133        ldr r4, = main
134            mov lr, pc
135            bx r4
136    
137/*-----------------------------------------------------------------------------
138- Loop for ever
139---------------
140- End of application. Normally, never occur.
141- Could jump on Software Reset ( B 0x0 ).
142------------------------------------------------------------------------------*/
143End:
144            b End
145

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