Root/target/linux/at91/image/dfboot/src/include/AT91RM9200.h

1// ----------------------------------------------------------------------------
2// ATMEL Microcontroller Software Support - ROUSSET -
3// ----------------------------------------------------------------------------
4// The software is delivered "AS IS" without warranty or condition of any
5// kind, either express, implied or statutory. This includes without
6// limitation any warranty or condition with respect to merchantability or
7// fitness for any particular purpose, or against the infringements of
8// intellectual property rights of others.
9// ----------------------------------------------------------------------------
10// File Name : AT91RM9200.h
11// Object : AT91RM9200 definitions
12// Generated : AT91 SW Application Group 11/19/2003 (17:20:50)
13//
14// CVS Reference : /AT91RM9200.pl/1.16/Fri Feb 07 10:29:51 2003//
15// CVS Reference : /SYS_AT91RM9200.pl/1.2/Fri Jan 17 12:44:37 2003//
16// CVS Reference : /MC_1760A.pl/1.1/Fri Aug 23 14:38:22 2002//
17// CVS Reference : /AIC_1796B.pl/1.1.1.1/Fri Jun 28 09:36:47 2002//
18// CVS Reference : /PMC_2636A.pl/1.1.1.1/Fri Jun 28 09:36:48 2002//
19// CVS Reference : /ST_1763B.pl/1.1/Fri Aug 23 14:41:42 2002//
20// CVS Reference : /RTC_1245D.pl/1.2/Fri Jan 31 12:19:06 2003//
21// CVS Reference : /PIO_1725D.pl/1.1.1.1/Fri Jun 28 09:36:47 2002//
22// CVS Reference : /DBGU_1754A.pl/1.4/Fri Jan 31 12:18:24 2003//
23// CVS Reference : /UDP_1765B.pl/1.3/Fri Aug 02 14:45:38 2002//
24// CVS Reference : /MCI_1764A.pl/1.2/Thu Nov 14 17:48:24 2002//
25// CVS Reference : /US_1739C.pl/1.2/Fri Jul 12 07:49:25 2002//
26// CVS Reference : /SPI_AT91RMxxxx.pl/1.3/Tue Nov 26 10:20:29 2002//
27// CVS Reference : /SSC_1762A.pl/1.2/Fri Nov 08 13:26:39 2002//
28// CVS Reference : /TC_1753B.pl/1.2/Fri Jan 31 12:19:55 2003//
29// CVS Reference : /TWI_1761B.pl/1.4/Fri Feb 07 10:30:07 2003//
30// CVS Reference : /PDC_1734B.pl/1.2/Thu Nov 21 16:38:23 2002//
31// CVS Reference : /UHP_xxxxA.pl/1.1/Mon Jul 22 12:21:58 2002//
32// CVS Reference : /EMAC_1794A.pl/1.4/Fri Jan 17 12:11:54 2003//
33// CVS Reference : /EBI_1759B.pl/1.10/Fri Jan 17 12:44:29 2003//
34// CVS Reference : /SMC_1783A.pl/1.3/Thu Oct 31 14:38:17 2002//
35// CVS Reference : /SDRC_1758B.pl/1.2/Thu Oct 03 13:04:41 2002//
36// CVS Reference : /BFC_1757B.pl/1.3/Thu Oct 31 14:38:00 2002//
37// ----------------------------------------------------------------------------
38
39#ifndef AT91RM9200_H
40#define AT91RM9200_H
41
42typedef volatile unsigned int AT91_REG;// Hardware register definition
43
44// *****************************************************************************
45// SOFTWARE API DEFINITION FOR System Peripherals
46// *****************************************************************************
47typedef struct _AT91S_SYS {
48    AT91_REG AIC_SMR[32]; // Source Mode Register
49    AT91_REG AIC_SVR[32]; // Source Vector Register
50    AT91_REG AIC_IVR; // IRQ Vector Register
51    AT91_REG AIC_FVR; // FIQ Vector Register
52    AT91_REG AIC_ISR; // Interrupt Status Register
53    AT91_REG AIC_IPR; // Interrupt Pending Register
54    AT91_REG AIC_IMR; // Interrupt Mask Register
55    AT91_REG AIC_CISR; // Core Interrupt Status Register
56    AT91_REG Reserved0[2]; //
57    AT91_REG AIC_IECR; // Interrupt Enable Command Register
58    AT91_REG AIC_IDCR; // Interrupt Disable Command Register
59    AT91_REG AIC_ICCR; // Interrupt Clear Command Register
60    AT91_REG AIC_ISCR; // Interrupt Set Command Register
61    AT91_REG AIC_EOICR; // End of Interrupt Command Register
62    AT91_REG AIC_SPU; // Spurious Vector Register
63    AT91_REG AIC_DCR; // Debug Control Register (Protect)
64    AT91_REG Reserved1[1]; //
65    AT91_REG AIC_FFER; // Fast Forcing Enable Register
66    AT91_REG AIC_FFDR; // Fast Forcing Disable Register
67    AT91_REG AIC_FFSR; // Fast Forcing Status Register
68    AT91_REG Reserved2[45]; //
69    AT91_REG DBGU_CR; // Control Register
70    AT91_REG DBGU_MR; // Mode Register
71    AT91_REG DBGU_IER; // Interrupt Enable Register
72    AT91_REG DBGU_IDR; // Interrupt Disable Register
73    AT91_REG DBGU_IMR; // Interrupt Mask Register
74    AT91_REG DBGU_CSR; // Channel Status Register
75    AT91_REG DBGU_RHR; // Receiver Holding Register
76    AT91_REG DBGU_THR; // Transmitter Holding Register
77    AT91_REG DBGU_BRGR; // Baud Rate Generator Register
78    AT91_REG Reserved3[7]; //
79    AT91_REG DBGU_C1R; // Chip ID1 Register
80    AT91_REG DBGU_C2R; // Chip ID2 Register
81    AT91_REG DBGU_FNTR; // Force NTRST Register
82    AT91_REG Reserved4[45]; //
83    AT91_REG DBGU_RPR; // Receive Pointer Register
84    AT91_REG DBGU_RCR; // Receive Counter Register
85    AT91_REG DBGU_TPR; // Transmit Pointer Register
86    AT91_REG DBGU_TCR; // Transmit Counter Register
87    AT91_REG DBGU_RNPR; // Receive Next Pointer Register
88    AT91_REG DBGU_RNCR; // Receive Next Counter Register
89    AT91_REG DBGU_TNPR; // Transmit Next Pointer Register
90    AT91_REG DBGU_TNCR; // Transmit Next Counter Register
91    AT91_REG DBGU_PTCR; // PDC Transfer Control Register
92    AT91_REG DBGU_PTSR; // PDC Transfer Status Register
93    AT91_REG Reserved5[54]; //
94    AT91_REG PIOA_PER; // PIO Enable Register
95    AT91_REG PIOA_PDR; // PIO Disable Register
96    AT91_REG PIOA_PSR; // PIO Status Register
97    AT91_REG Reserved6[1]; //
98    AT91_REG PIOA_OER; // Output Enable Register
99    AT91_REG PIOA_ODR; // Output Disable Registerr
100    AT91_REG PIOA_OSR; // Output Status Register
101    AT91_REG Reserved7[1]; //
102    AT91_REG PIOA_IFER; // Input Filter Enable Register
103    AT91_REG PIOA_IFDR; // Input Filter Disable Register
104    AT91_REG PIOA_IFSR; // Input Filter Status Register
105    AT91_REG Reserved8[1]; //
106    AT91_REG PIOA_SODR; // Set Output Data Register
107    AT91_REG PIOA_CODR; // Clear Output Data Register
108    AT91_REG PIOA_ODSR; // Output Data Status Register
109    AT91_REG PIOA_PDSR; // Pin Data Status Register
110    AT91_REG PIOA_IER; // Interrupt Enable Register
111    AT91_REG PIOA_IDR; // Interrupt Disable Register
112    AT91_REG PIOA_IMR; // Interrupt Mask Register
113    AT91_REG PIOA_ISR; // Interrupt Status Register
114    AT91_REG PIOA_MDER; // Multi-driver Enable Register
115    AT91_REG PIOA_MDDR; // Multi-driver Disable Register
116    AT91_REG PIOA_MDSR; // Multi-driver Status Register
117    AT91_REG Reserved9[1]; //
118    AT91_REG PIOA_PPUDR; // Pull-up Disable Register
119    AT91_REG PIOA_PPUER; // Pull-up Enable Register
120    AT91_REG PIOA_PPUSR; // Pad Pull-up Status Register
121    AT91_REG Reserved10[1]; //
122    AT91_REG PIOA_ASR; // Select A Register
123    AT91_REG PIOA_BSR; // Select B Register
124    AT91_REG PIOA_ABSR; // AB Select Status Register
125    AT91_REG Reserved11[9]; //
126    AT91_REG PIOA_OWER; // Output Write Enable Register
127    AT91_REG PIOA_OWDR; // Output Write Disable Register
128    AT91_REG PIOA_OWSR; // Output Write Status Register
129    AT91_REG Reserved12[85]; //
130    AT91_REG PIOB_PER; // PIO Enable Register
131    AT91_REG PIOB_PDR; // PIO Disable Register
132    AT91_REG PIOB_PSR; // PIO Status Register
133    AT91_REG Reserved13[1]; //
134    AT91_REG PIOB_OER; // Output Enable Register
135    AT91_REG PIOB_ODR; // Output Disable Registerr
136    AT91_REG PIOB_OSR; // Output Status Register
137    AT91_REG Reserved14[1]; //
138    AT91_REG PIOB_IFER; // Input Filter Enable Register
139    AT91_REG PIOB_IFDR; // Input Filter Disable Register
140    AT91_REG PIOB_IFSR; // Input Filter Status Register
141    AT91_REG Reserved15[1]; //
142    AT91_REG PIOB_SODR; // Set Output Data Register
143    AT91_REG PIOB_CODR; // Clear Output Data Register
144    AT91_REG PIOB_ODSR; // Output Data Status Register
145    AT91_REG PIOB_PDSR; // Pin Data Status Register
146    AT91_REG PIOB_IER; // Interrupt Enable Register
147    AT91_REG PIOB_IDR; // Interrupt Disable Register
148    AT91_REG PIOB_IMR; // Interrupt Mask Register
149    AT91_REG PIOB_ISR; // Interrupt Status Register
150    AT91_REG PIOB_MDER; // Multi-driver Enable Register
151    AT91_REG PIOB_MDDR; // Multi-driver Disable Register
152    AT91_REG PIOB_MDSR; // Multi-driver Status Register
153    AT91_REG Reserved16[1]; //
154    AT91_REG PIOB_PPUDR; // Pull-up Disable Register
155    AT91_REG PIOB_PPUER; // Pull-up Enable Register
156    AT91_REG PIOB_PPUSR; // Pad Pull-up Status Register
157    AT91_REG Reserved17[1]; //
158    AT91_REG PIOB_ASR; // Select A Register
159    AT91_REG PIOB_BSR; // Select B Register
160    AT91_REG PIOB_ABSR; // AB Select Status Register
161    AT91_REG Reserved18[9]; //
162    AT91_REG PIOB_OWER; // Output Write Enable Register
163    AT91_REG PIOB_OWDR; // Output Write Disable Register
164    AT91_REG PIOB_OWSR; // Output Write Status Register
165    AT91_REG Reserved19[85]; //
166    AT91_REG PIOC_PER; // PIO Enable Register
167    AT91_REG PIOC_PDR; // PIO Disable Register
168    AT91_REG PIOC_PSR; // PIO Status Register
169    AT91_REG Reserved20[1]; //
170    AT91_REG PIOC_OER; // Output Enable Register
171    AT91_REG PIOC_ODR; // Output Disable Registerr
172    AT91_REG PIOC_OSR; // Output Status Register
173    AT91_REG Reserved21[1]; //
174    AT91_REG PIOC_IFER; // Input Filter Enable Register
175    AT91_REG PIOC_IFDR; // Input Filter Disable Register
176    AT91_REG PIOC_IFSR; // Input Filter Status Register
177    AT91_REG Reserved22[1]; //
178    AT91_REG PIOC_SODR; // Set Output Data Register
179    AT91_REG PIOC_CODR; // Clear Output Data Register
180    AT91_REG PIOC_ODSR; // Output Data Status Register
181    AT91_REG PIOC_PDSR; // Pin Data Status Register
182    AT91_REG PIOC_IER; // Interrupt Enable Register
183    AT91_REG PIOC_IDR; // Interrupt Disable Register
184    AT91_REG PIOC_IMR; // Interrupt Mask Register
185    AT91_REG PIOC_ISR; // Interrupt Status Register
186    AT91_REG PIOC_MDER; // Multi-driver Enable Register
187    AT91_REG PIOC_MDDR; // Multi-driver Disable Register
188    AT91_REG PIOC_MDSR; // Multi-driver Status Register
189    AT91_REG Reserved23[1]; //
190    AT91_REG PIOC_PPUDR; // Pull-up Disable Register
191    AT91_REG PIOC_PPUER; // Pull-up Enable Register
192    AT91_REG PIOC_PPUSR; // Pad Pull-up Status Register
193    AT91_REG Reserved24[1]; //
194    AT91_REG PIOC_ASR; // Select A Register
195    AT91_REG PIOC_BSR; // Select B Register
196    AT91_REG PIOC_ABSR; // AB Select Status Register
197    AT91_REG Reserved25[9]; //
198    AT91_REG PIOC_OWER; // Output Write Enable Register
199    AT91_REG PIOC_OWDR; // Output Write Disable Register
200    AT91_REG PIOC_OWSR; // Output Write Status Register
201    AT91_REG Reserved26[85]; //
202    AT91_REG PIOD_PER; // PIO Enable Register
203    AT91_REG PIOD_PDR; // PIO Disable Register
204    AT91_REG PIOD_PSR; // PIO Status Register
205    AT91_REG Reserved27[1]; //
206    AT91_REG PIOD_OER; // Output Enable Register
207    AT91_REG PIOD_ODR; // Output Disable Registerr
208    AT91_REG PIOD_OSR; // Output Status Register
209    AT91_REG Reserved28[1]; //
210    AT91_REG PIOD_IFER; // Input Filter Enable Register
211    AT91_REG PIOD_IFDR; // Input Filter Disable Register
212    AT91_REG PIOD_IFSR; // Input Filter Status Register
213    AT91_REG Reserved29[1]; //
214    AT91_REG PIOD_SODR; // Set Output Data Register
215    AT91_REG PIOD_CODR; // Clear Output Data Register
216    AT91_REG PIOD_ODSR; // Output Data Status Register
217    AT91_REG PIOD_PDSR; // Pin Data Status Register
218    AT91_REG PIOD_IER; // Interrupt Enable Register
219    AT91_REG PIOD_IDR; // Interrupt Disable Register
220    AT91_REG PIOD_IMR; // Interrupt Mask Register
221    AT91_REG PIOD_ISR; // Interrupt Status Register
222    AT91_REG PIOD_MDER; // Multi-driver Enable Register
223    AT91_REG PIOD_MDDR; // Multi-driver Disable Register
224    AT91_REG PIOD_MDSR; // Multi-driver Status Register
225    AT91_REG Reserved30[1]; //
226    AT91_REG PIOD_PPUDR; // Pull-up Disable Register
227    AT91_REG PIOD_PPUER; // Pull-up Enable Register
228    AT91_REG PIOD_PPUSR; // Pad Pull-up Status Register
229    AT91_REG Reserved31[1]; //
230    AT91_REG PIOD_ASR; // Select A Register
231    AT91_REG PIOD_BSR; // Select B Register
232    AT91_REG PIOD_ABSR; // AB Select Status Register
233    AT91_REG Reserved32[9]; //
234    AT91_REG PIOD_OWER; // Output Write Enable Register
235    AT91_REG PIOD_OWDR; // Output Write Disable Register
236    AT91_REG PIOD_OWSR; // Output Write Status Register
237    AT91_REG Reserved33[85]; //
238    AT91_REG PMC_SCER; // System Clock Enable Register
239    AT91_REG PMC_SCDR; // System Clock Disable Register
240    AT91_REG PMC_SCSR; // System Clock Status Register
241    AT91_REG Reserved34[1]; //
242    AT91_REG PMC_PCER; // Peripheral Clock Enable Register
243    AT91_REG PMC_PCDR; // Peripheral Clock Disable Register
244    AT91_REG PMC_PCSR; // Peripheral Clock Status Register
245    AT91_REG Reserved35[1]; //
246    AT91_REG CKGR_MOR; // Main Oscillator Register
247    AT91_REG CKGR_MCFR; // Main Clock Frequency Register
248    AT91_REG CKGR_PLLAR; // PLL A Register
249    AT91_REG CKGR_PLLBR; // PLL B Register
250    AT91_REG PMC_MCKR; // Master Clock Register
251    AT91_REG Reserved36[3]; //
252    AT91_REG PMC_PCKR[8]; // Programmable Clock Register
253    AT91_REG PMC_IER; // Interrupt Enable Register
254    AT91_REG PMC_IDR; // Interrupt Disable Register
255    AT91_REG PMC_SR; // Status Register
256    AT91_REG PMC_IMR; // Interrupt Mask Register
257    AT91_REG Reserved37[36]; //
258    AT91_REG ST_CR; // Control Register
259    AT91_REG ST_PIMR; // Period Interval Mode Register
260    AT91_REG ST_WDMR; // Watchdog Mode Register
261    AT91_REG ST_RTMR; // Real-time Mode Register
262    AT91_REG ST_SR; // Status Register
263    AT91_REG ST_IER; // Interrupt Enable Register
264    AT91_REG ST_IDR; // Interrupt Disable Register
265    AT91_REG ST_IMR; // Interrupt Mask Register
266    AT91_REG ST_RTAR; // Real-time Alarm Register
267    AT91_REG ST_CRTR; // Current Real-time Register
268    AT91_REG Reserved38[54]; //
269    AT91_REG RTC_CR; // Control Register
270    AT91_REG RTC_MR; // Mode Register
271    AT91_REG RTC_TIMR; // Time Register
272    AT91_REG RTC_CALR; // Calendar Register
273    AT91_REG RTC_TIMALR; // Time Alarm Register
274    AT91_REG RTC_CALALR; // Calendar Alarm Register
275    AT91_REG RTC_SR; // Status Register
276    AT91_REG RTC_SCCR; // Status Clear Command Register
277    AT91_REG RTC_IER; // Interrupt Enable Register
278    AT91_REG RTC_IDR; // Interrupt Disable Register
279    AT91_REG RTC_IMR; // Interrupt Mask Register
280    AT91_REG RTC_VER; // Valid Entry Register
281    AT91_REG Reserved39[52]; //
282    AT91_REG MC_RCR; // MC Remap Control Register
283    AT91_REG MC_ASR; // MC Abort Status Register
284    AT91_REG MC_AASR; // MC Abort Address Status Register
285    AT91_REG Reserved40[1]; //
286    AT91_REG MC_PUIA[16]; // MC Protection Unit Area
287    AT91_REG MC_PUP; // MC Protection Unit Peripherals
288    AT91_REG MC_PUER; // MC Protection Unit Enable Register
289    AT91_REG Reserved41[2]; //
290    AT91_REG EBI_CSA; // Chip Select Assignment Register
291    AT91_REG EBI_CFGR; // Configuration Register
292    AT91_REG Reserved42[2]; //
293    AT91_REG EBI_SMC2_CSR[8]; // SMC2 Chip Select Register
294    AT91_REG EBI_SDRC_MR; // SDRAM Controller Mode Register
295    AT91_REG EBI_SDRC_TR; // SDRAM Controller Refresh Timer Register
296    AT91_REG EBI_SDRC_CR; // SDRAM Controller Configuration Register
297    AT91_REG EBI_SDRC_SRR; // SDRAM Controller Self Refresh Register
298    AT91_REG EBI_SDRC_LPR; // SDRAM Controller Low Power Register
299    AT91_REG EBI_SDRC_IER; // SDRAM Controller Interrupt Enable Register
300    AT91_REG EBI_SDRC_IDR; // SDRAM Controller Interrupt Disable Register
301    AT91_REG EBI_SDRC_IMR; // SDRAM Controller Interrupt Mask Register
302    AT91_REG EBI_SDRC_ISR; // SDRAM Controller Interrupt Mask Register
303    AT91_REG Reserved43[3]; //
304    AT91_REG EBI_BFC_MR; // BFC Mode Register
305} AT91S_SYS, *AT91PS_SYS;
306
307
308// *****************************************************************************
309// SOFTWARE API DEFINITION FOR Memory Controller Interface
310// *****************************************************************************
311typedef struct _AT91S_MC {
312    AT91_REG MC_RCR; // MC Remap Control Register
313    AT91_REG MC_ASR; // MC Abort Status Register
314    AT91_REG MC_AASR; // MC Abort Address Status Register
315    AT91_REG Reserved0[1]; //
316    AT91_REG MC_PUIA[16]; // MC Protection Unit Area
317    AT91_REG MC_PUP; // MC Protection Unit Peripherals
318    AT91_REG MC_PUER; // MC Protection Unit Enable Register
319} AT91S_MC, *AT91PS_MC;
320
321// -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register --------
322#define AT91C_MC_RCB ((unsigned int) 0x1 << 0) // (MC) Remap Command Bit
323// -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register --------
324#define AT91C_MC_UNDADD ((unsigned int) 0x1 << 0) // (MC) Undefined Addess Abort Status
325#define AT91C_MC_MISADD ((unsigned int) 0x1 << 1) // (MC) Misaligned Addess Abort Status
326#define AT91C_MC_MPU ((unsigned int) 0x1 << 2) // (MC) Memory protection Unit Abort Status
327#define AT91C_MC_ABTSZ ((unsigned int) 0x3 << 8) // (MC) Abort Size Status
328#define AT91C_MC_ABTSZ_BYTE ((unsigned int) 0x0 << 8) // (MC) Byte
329#define AT91C_MC_ABTSZ_HWORD ((unsigned int) 0x1 << 8) // (MC) Half-word
330#define AT91C_MC_ABTSZ_WORD ((unsigned int) 0x2 << 8) // (MC) Word
331#define AT91C_MC_ABTTYP ((unsigned int) 0x3 << 10) // (MC) Abort Type Status
332#define AT91C_MC_ABTTYP_DATAR ((unsigned int) 0x0 << 10) // (MC) Data Read
333#define AT91C_MC_ABTTYP_DATAW ((unsigned int) 0x1 << 10) // (MC) Data Write
334#define AT91C_MC_ABTTYP_FETCH ((unsigned int) 0x2 << 10) // (MC) Code Fetch
335#define AT91C_MC_MST0 ((unsigned int) 0x1 << 16) // (MC) Master 0 Abort Source
336#define AT91C_MC_MST1 ((unsigned int) 0x1 << 17) // (MC) Master 1 Abort Source
337#define AT91C_MC_SVMST0 ((unsigned int) 0x1 << 24) // (MC) Saved Master 0 Abort Source
338#define AT91C_MC_SVMST1 ((unsigned int) 0x1 << 25) // (MC) Saved Master 1 Abort Source
339// -------- MC_PUIA : (MC Offset: 0x10) MC Protection Unit Area --------
340#define AT91C_MC_PROT ((unsigned int) 0x3 << 0) // (MC) Protection
341#define AT91C_MC_PROT_PNAUNA ((unsigned int) 0x0) // (MC) Privilege: No Access, User: No Access
342#define AT91C_MC_PROT_PRWUNA ((unsigned int) 0x1) // (MC) Privilege: Read/Write, User: No Access
343#define AT91C_MC_PROT_PRWURO ((unsigned int) 0x2) // (MC) Privilege: Read/Write, User: Read Only
344#define AT91C_MC_PROT_PRWURW ((unsigned int) 0x3) // (MC) Privilege: Read/Write, User: Read/Write
345#define AT91C_MC_SIZE ((unsigned int) 0xF << 4) // (MC) Internal Area Size
346#define AT91C_MC_SIZE_1KB ((unsigned int) 0x0 << 4) // (MC) Area size 1KByte
347#define AT91C_MC_SIZE_2KB ((unsigned int) 0x1 << 4) // (MC) Area size 2KByte
348#define AT91C_MC_SIZE_4KB ((unsigned int) 0x2 << 4) // (MC) Area size 4KByte
349#define AT91C_MC_SIZE_8KB ((unsigned int) 0x3 << 4) // (MC) Area size 8KByte
350#define AT91C_MC_SIZE_16KB ((unsigned int) 0x4 << 4) // (MC) Area size 16KByte
351#define AT91C_MC_SIZE_32KB ((unsigned int) 0x5 << 4) // (MC) Area size 32KByte
352#define AT91C_MC_SIZE_64KB ((unsigned int) 0x6 << 4) // (MC) Area size 64KByte
353#define AT91C_MC_SIZE_128KB ((unsigned int) 0x7 << 4) // (MC) Area size 128KByte
354#define AT91C_MC_SIZE_256KB ((unsigned int) 0x8 << 4) // (MC) Area size 256KByte
355#define AT91C_MC_SIZE_512KB ((unsigned int) 0x9 << 4) // (MC) Area size 512KByte
356#define AT91C_MC_SIZE_1MB ((unsigned int) 0xA << 4) // (MC) Area size 1MByte
357#define AT91C_MC_SIZE_2MB ((unsigned int) 0xB << 4) // (MC) Area size 2MByte
358#define AT91C_MC_SIZE_4MB ((unsigned int) 0xC << 4) // (MC) Area size 4MByte
359#define AT91C_MC_SIZE_8MB ((unsigned int) 0xD << 4) // (MC) Area size 8MByte
360#define AT91C_MC_SIZE_16MB ((unsigned int) 0xE << 4) // (MC) Area size 16MByte
361#define AT91C_MC_SIZE_64MB ((unsigned int) 0xF << 4) // (MC) Area size 64MByte
362#define AT91C_MC_BA ((unsigned int) 0x3FFFF << 10) // (MC) Internal Area Base Address
363// -------- MC_PUP : (MC Offset: 0x50) MC Protection Unit Peripheral --------
364// -------- MC_PUER : (MC Offset: 0x54) MC Protection Unit Area --------
365#define AT91C_MC_PUEB ((unsigned int) 0x1 << 0) // (MC) Protection Unit enable Bit
366
367// *****************************************************************************
368// SOFTWARE API DEFINITION FOR Real-time Clock Alarm and Parallel Load Interface
369// *****************************************************************************
370typedef struct _AT91S_RTC {
371    AT91_REG RTC_CR; // Control Register
372    AT91_REG RTC_MR; // Mode Register
373    AT91_REG RTC_TIMR; // Time Register
374    AT91_REG RTC_CALR; // Calendar Register
375    AT91_REG RTC_TIMALR; // Time Alarm Register
376    AT91_REG RTC_CALALR; // Calendar Alarm Register
377    AT91_REG RTC_SR; // Status Register
378    AT91_REG RTC_SCCR; // Status Clear Command Register
379    AT91_REG RTC_IER; // Interrupt Enable Register
380    AT91_REG RTC_IDR; // Interrupt Disable Register
381    AT91_REG RTC_IMR; // Interrupt Mask Register
382    AT91_REG RTC_VER; // Valid Entry Register
383} AT91S_RTC, *AT91PS_RTC;
384
385// -------- RTC_CR : (RTC Offset: 0x0) RTC Control Register --------
386#define AT91C_RTC_UPDTIM ((unsigned int) 0x1 << 0) // (RTC) Update Request Time Register
387#define AT91C_RTC_UPDCAL ((unsigned int) 0x1 << 1) // (RTC) Update Request Calendar Register
388#define AT91C_RTC_TIMEVSEL ((unsigned int) 0x3 << 8) // (RTC) Time Event Selection
389#define AT91C_RTC_TIMEVSEL_MINUTE ((unsigned int) 0x0 << 8) // (RTC) Minute change.
390#define AT91C_RTC_TIMEVSEL_HOUR ((unsigned int) 0x1 << 8) // (RTC) Hour change.
391#define AT91C_RTC_TIMEVSEL_DAY24 ((unsigned int) 0x2 << 8) // (RTC) Every day at midnight.
392#define AT91C_RTC_TIMEVSEL_DAY12 ((unsigned int) 0x3 << 8) // (RTC) Every day at noon.
393#define AT91C_RTC_CALEVSEL ((unsigned int) 0x3 << 16) // (RTC) Calendar Event Selection
394#define AT91C_RTC_CALEVSEL_WEEK ((unsigned int) 0x0 << 16) // (RTC) Week change (every Monday at time 00:00:00).
395#define AT91C_RTC_CALEVSEL_MONTH ((unsigned int) 0x1 << 16) // (RTC) Month change (every 01 of each month at time 00:00:00).
396#define AT91C_RTC_CALEVSEL_YEAR ((unsigned int) 0x2 << 16) // (RTC) Year change (every January 1 at time 00:00:00).
397// -------- RTC_MR : (RTC Offset: 0x4) RTC Mode Register --------
398#define AT91C_RTC_HRMOD ((unsigned int) 0x1 << 0) // (RTC) 12-24 hour Mode
399// -------- RTC_TIMR : (RTC Offset: 0x8) RTC Time Register --------
400#define AT91C_RTC_SEC ((unsigned int) 0x7F << 0) // (RTC) Current Second
401#define AT91C_RTC_MIN ((unsigned int) 0x7F << 8) // (RTC) Current Minute
402#define AT91C_RTC_HOUR ((unsigned int) 0x1F << 16) // (RTC) Current Hour
403#define AT91C_RTC_AMPM ((unsigned int) 0x1 << 22) // (RTC) Ante Meridiem, Post Meridiem Indicator
404// -------- RTC_CALR : (RTC Offset: 0xc) RTC Calendar Register --------
405#define AT91C_RTC_CENT ((unsigned int) 0x3F << 0) // (RTC) Current Century
406#define AT91C_RTC_YEAR ((unsigned int) 0xFF << 8) // (RTC) Current Year
407#define AT91C_RTC_MONTH ((unsigned int) 0x1F << 16) // (RTC) Current Month
408#define AT91C_RTC_DAY ((unsigned int) 0x7 << 21) // (RTC) Current Day
409#define AT91C_RTC_DATE ((unsigned int) 0x3F << 24) // (RTC) Current Date
410// -------- RTC_TIMALR : (RTC Offset: 0x10) RTC Time Alarm Register --------
411#define AT91C_RTC_SECEN ((unsigned int) 0x1 << 7) // (RTC) Second Alarm Enable
412#define AT91C_RTC_MINEN ((unsigned int) 0x1 << 15) // (RTC) Minute Alarm
413#define AT91C_RTC_HOUREN ((unsigned int) 0x1 << 23) // (RTC) Current Hour
414// -------- RTC_CALALR : (RTC Offset: 0x14) RTC Calendar Alarm Register --------
415#define AT91C_RTC_MONTHEN ((unsigned int) 0x1 << 23) // (RTC) Month Alarm Enable
416#define AT91C_RTC_DATEEN ((unsigned int) 0x1 << 31) // (RTC) Date Alarm Enable
417// -------- RTC_SR : (RTC Offset: 0x18) RTC Status Register --------
418#define AT91C_RTC_ACKUPD ((unsigned int) 0x1 << 0) // (RTC) Acknowledge for Update
419#define AT91C_RTC_ALARM ((unsigned int) 0x1 << 1) // (RTC) Alarm Flag
420#define AT91C_RTC_SECEV ((unsigned int) 0x1 << 2) // (RTC) Second Event
421#define AT91C_RTC_TIMEV ((unsigned int) 0x1 << 3) // (RTC) Time Event
422#define AT91C_RTC_CALEV ((unsigned int) 0x1 << 4) // (RTC) Calendar event
423// -------- RTC_SCCR : (RTC Offset: 0x1c) RTC Status Clear Command Register --------
424// -------- RTC_IER : (RTC Offset: 0x20) RTC Interrupt Enable Register --------
425// -------- RTC_IDR : (RTC Offset: 0x24) RTC Interrupt Disable Register --------
426// -------- RTC_IMR : (RTC Offset: 0x28) RTC Interrupt Mask Register --------
427// -------- RTC_VER : (RTC Offset: 0x2c) RTC Valid Entry Register --------
428#define AT91C_RTC_NVTIM ((unsigned int) 0x1 << 0) // (RTC) Non valid Time
429#define AT91C_RTC_NVCAL ((unsigned int) 0x1 << 1) // (RTC) Non valid Calendar
430#define AT91C_RTC_NVTIMALR ((unsigned int) 0x1 << 2) // (RTC) Non valid time Alarm
431#define AT91C_RTC_NVCALALR ((unsigned int) 0x1 << 3) // (RTC) Nonvalid Calendar Alarm
432
433// *****************************************************************************
434// SOFTWARE API DEFINITION FOR System Timer Interface
435// *****************************************************************************
436typedef struct _AT91S_ST {
437    AT91_REG ST_CR; // Control Register
438    AT91_REG ST_PIMR; // Period Interval Mode Register
439    AT91_REG ST_WDMR; // Watchdog Mode Register
440    AT91_REG ST_RTMR; // Real-time Mode Register
441    AT91_REG ST_SR; // Status Register
442    AT91_REG ST_IER; // Interrupt Enable Register
443    AT91_REG ST_IDR; // Interrupt Disable Register
444    AT91_REG ST_IMR; // Interrupt Mask Register
445    AT91_REG ST_RTAR; // Real-time Alarm Register
446    AT91_REG ST_CRTR; // Current Real-time Register
447} AT91S_ST, *AT91PS_ST;
448
449// -------- ST_CR : (ST Offset: 0x0) System Timer Control Register --------
450#define AT91C_ST_WDRST ((unsigned int) 0x1 << 0) // (ST) Watchdog Timer Restart
451// -------- ST_PIMR : (ST Offset: 0x4) System Timer Period Interval Mode Register --------
452#define AT91C_ST_PIV ((unsigned int) 0xFFFF << 0) // (ST) Watchdog Timer Restart
453// -------- ST_WDMR : (ST Offset: 0x8) System Timer Watchdog Mode Register --------
454#define AT91C_ST_WDV ((unsigned int) 0xFFFF << 0) // (ST) Watchdog Timer Restart
455#define AT91C_ST_RSTEN ((unsigned int) 0x1 << 16) // (ST) Reset Enable
456#define AT91C_ST_EXTEN ((unsigned int) 0x1 << 17) // (ST) External Signal Assertion Enable
457// -------- ST_RTMR : (ST Offset: 0xc) System Timer Real-time Mode Register --------
458#define AT91C_ST_RTPRES ((unsigned int) 0xFFFF << 0) // (ST) Real-time Timer Prescaler Value
459// -------- ST_SR : (ST Offset: 0x10) System Timer Status Register --------
460#define AT91C_ST_PITS ((unsigned int) 0x1 << 0) // (ST) Period Interval Timer Interrupt
461#define AT91C_ST_WDOVF ((unsigned int) 0x1 << 1) // (ST) Watchdog Overflow
462#define AT91C_ST_RTTINC ((unsigned int) 0x1 << 2) // (ST) Real-time Timer Increment
463#define AT91C_ST_ALMS ((unsigned int) 0x1 << 3) // (ST) Alarm Status
464// -------- ST_IER : (ST Offset: 0x14) System Timer Interrupt Enable Register --------
465// -------- ST_IDR : (ST Offset: 0x18) System Timer Interrupt Disable Register --------
466// -------- ST_IMR : (ST Offset: 0x1c) System Timer Interrupt Mask Register --------
467// -------- ST_RTAR : (ST Offset: 0x20) System Timer Real-time Alarm Register --------
468#define AT91C_ST_ALMV ((unsigned int) 0xFFFFF << 0) // (ST) Alarm Value Value
469// -------- ST_CRTR : (ST Offset: 0x24) System Timer Current Real-time Register --------
470#define AT91C_ST_CRTV ((unsigned int) 0xFFFFF << 0) // (ST) Current Real-time Value
471
472// *****************************************************************************
473// SOFTWARE API DEFINITION FOR Power Management Controler
474// *****************************************************************************
475typedef struct _AT91S_PMC {
476    AT91_REG PMC_SCER; // System Clock Enable Register
477    AT91_REG PMC_SCDR; // System Clock Disable Register
478    AT91_REG PMC_SCSR; // System Clock Status Register
479    AT91_REG Reserved0[1]; //
480    AT91_REG PMC_PCER; // Peripheral Clock Enable Register
481    AT91_REG PMC_PCDR; // Peripheral Clock Disable Register
482    AT91_REG PMC_PCSR; // Peripheral Clock Status Register
483    AT91_REG Reserved1[5]; //
484    AT91_REG PMC_MCKR; // Master Clock Register
485    AT91_REG Reserved2[3]; //
486    AT91_REG PMC_PCKR[8]; // Programmable Clock Register
487    AT91_REG PMC_IER; // Interrupt Enable Register
488    AT91_REG PMC_IDR; // Interrupt Disable Register
489    AT91_REG PMC_SR; // Status Register
490    AT91_REG PMC_IMR; // Interrupt Mask Register
491} AT91S_PMC, *AT91PS_PMC;
492
493// -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register --------
494#define AT91C_PMC_PCK ((unsigned int) 0x1 << 0) // (PMC) Processor Clock
495#define AT91C_PMC_UDP ((unsigned int) 0x1 << 1) // (PMC) USB Device Port Clock
496#define AT91C_PMC_MCKUDP ((unsigned int) 0x1 << 2) // (PMC) USB Device Port Master Clock Automatic Disable on Suspend
497#define AT91C_PMC_UHP ((unsigned int) 0x1 << 4) // (PMC) USB Host Port Clock
498#define AT91C_PMC_PCK0 ((unsigned int) 0x1 << 8) // (PMC) Programmable Clock Output
499#define AT91C_PMC_PCK1 ((unsigned int) 0x1 << 9) // (PMC) Programmable Clock Output
500#define AT91C_PMC_PCK2 ((unsigned int) 0x1 << 10) // (PMC) Programmable Clock Output
501#define AT91C_PMC_PCK3 ((unsigned int) 0x1 << 11) // (PMC) Programmable Clock Output
502#define AT91C_PMC_PCK4 ((unsigned int) 0x1 << 12) // (PMC) Programmable Clock Output
503#define AT91C_PMC_PCK5 ((unsigned int) 0x1 << 13) // (PMC) Programmable Clock Output
504#define AT91C_PMC_PCK6 ((unsigned int) 0x1 << 14) // (PMC) Programmable Clock Output
505#define AT91C_PMC_PCK7 ((unsigned int) 0x1 << 15) // (PMC) Programmable Clock Output
506// -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register --------
507// -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register --------
508// -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register --------
509#define AT91C_PMC_CSS ((unsigned int) 0x3 << 0) // (PMC) Programmable Clock Selection
510#define AT91C_PMC_CSS_SLOW_CLK ((unsigned int) 0x0) // (PMC) Slow Clock is selected
511#define AT91C_PMC_CSS_MAIN_CLK ((unsigned int) 0x1) // (PMC) Main Clock is selected
512#define AT91C_PMC_CSS_PLLA_CLK ((unsigned int) 0x2) // (PMC) Clock from PLL A is selected
513#define AT91C_PMC_CSS_PLLB_CLK ((unsigned int) 0x3) // (PMC) Clock from PLL B is selected
514#define AT91C_PMC_PRES ((unsigned int) 0x7 << 2) // (PMC) Programmable Clock Prescaler
515#define AT91C_PMC_PRES_CLK ((unsigned int) 0x0 << 2) // (PMC) Selected clock
516#define AT91C_PMC_PRES_CLK_2 ((unsigned int) 0x1 << 2) // (PMC) Selected clock divided by 2
517#define AT91C_PMC_PRES_CLK_4 ((unsigned int) 0x2 << 2) // (PMC) Selected clock divided by 4
518#define AT91C_PMC_PRES_CLK_8 ((unsigned int) 0x3 << 2) // (PMC) Selected clock divided by 8
519#define AT91C_PMC_PRES_CLK_16 ((unsigned int) 0x4 << 2) // (PMC) Selected clock divided by 16
520#define AT91C_PMC_PRES_CLK_32 ((unsigned int) 0x5 << 2) // (PMC) Selected clock divided by 32
521#define AT91C_PMC_PRES_CLK_64 ((unsigned int) 0x6 << 2) // (PMC) Selected clock divided by 64
522#define AT91C_PMC_MDIV ((unsigned int) 0x3 << 8) // (PMC) Master Clock Division
523#define AT91C_PMC_MDIV_1 ((unsigned int) 0x0 << 8) // (PMC) The master clock and the processor clock are the same
524#define AT91C_PMC_MDIV_2 ((unsigned int) 0x1 << 8) // (PMC) The processor clock is twice as fast as the master clock
525#define AT91C_PMC_MDIV_3 ((unsigned int) 0x2 << 8) // (PMC) The processor clock is three times faster than the master clock
526#define AT91C_PMC_MDIV_4 ((unsigned int) 0x3 << 8) // (PMC) The processor clock is four times faster than the master clock
527// -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register --------
528// -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register --------
529#define AT91C_PMC_MOSCS ((unsigned int) 0x1 << 0) // (PMC) MOSC Status/Enable/Disable/Mask
530#define AT91C_PMC_LOCKA ((unsigned int) 0x1 << 1) // (PMC) PLL A Status/Enable/Disable/Mask
531#define AT91C_PMC_LOCKB ((unsigned int) 0x1 << 2) // (PMC) PLL B Status/Enable/Disable/Mask
532#define AT91C_PMC_MCKRDY ((unsigned int) 0x1 << 3) // (PMC) MCK_RDY Status/Enable/Disable/Mask
533#define AT91C_PMC_PCK0RDY ((unsigned int) 0x1 << 8) // (PMC) PCK0_RDY Status/Enable/Disable/Mask
534#define AT91C_PMC_PCK1RDY ((unsigned int) 0x1 << 9) // (PMC) PCK1_RDY Status/Enable/Disable/Mask
535#define AT91C_PMC_PCK2RDY ((unsigned int) 0x1 << 10) // (PMC) PCK2_RDY Status/Enable/Disable/Mask
536#define AT91C_PMC_PCK3RDY ((unsigned int) 0x1 << 11) // (PMC) PCK3_RDY Status/Enable/Disable/Mask
537#define AT91C_PMC_PCK4RDY ((unsigned int) 0x1 << 12) // (PMC) PCK4_RDY Status/Enable/Disable/Mask
538#define AT91C_PMC_PCK5RDY ((unsigned int) 0x1 << 13) // (PMC) PCK5_RDY Status/Enable/Disable/Mask
539#define AT91C_PMC_PCK6RDY ((unsigned int) 0x1 << 14) // (PMC) PCK6_RDY Status/Enable/Disable/Mask
540#define AT91C_PMC_PCK7RDY ((unsigned int) 0x1 << 15) // (PMC) PCK7_RDY Status/Enable/Disable/Mask
541// -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register --------
542// -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register --------
543// -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register --------
544
545// *****************************************************************************
546// SOFTWARE API DEFINITION FOR Clock Generator Controler
547// *****************************************************************************
548typedef struct _AT91S_CKGR {
549    AT91_REG CKGR_MOR; // Main Oscillator Register
550    AT91_REG CKGR_MCFR; // Main Clock Frequency Register
551    AT91_REG CKGR_PLLAR; // PLL A Register
552    AT91_REG CKGR_PLLBR; // PLL B Register
553} AT91S_CKGR, *AT91PS_CKGR;
554
555// -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register --------
556#define AT91C_CKGR_MOSCEN ((unsigned int) 0x1 << 0) // (CKGR) Main Oscillator Enable
557#define AT91C_CKGR_OSCTEST ((unsigned int) 0x1 << 1) // (CKGR) Oscillator Test
558#define AT91C_CKGR_OSCOUNT ((unsigned int) 0xFF << 8) // (CKGR) Main Oscillator Start-up Time
559// -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register --------
560#define AT91C_CKGR_MAINF ((unsigned int) 0xFFFF << 0) // (CKGR) Main Clock Frequency
561#define AT91C_CKGR_MAINRDY ((unsigned int) 0x1 << 16) // (CKGR) Main Clock Ready
562// -------- CKGR_PLLAR : (CKGR Offset: 0x8) PLL A Register --------
563#define AT91C_CKGR_DIVA ((unsigned int) 0xFF << 0) // (CKGR) Divider Selected
564#define AT91C_CKGR_DIVA_0 ((unsigned int) 0x0) // (CKGR) Divider output is 0
565#define AT91C_CKGR_DIVA_BYPASS ((unsigned int) 0x1) // (CKGR) Divider is bypassed
566#define AT91C_CKGR_PLLACOUNT ((unsigned int) 0x3F << 8) // (CKGR) PLL A Counter
567#define AT91C_CKGR_OUTA ((unsigned int) 0x3 << 14) // (CKGR) PLL A Output Frequency Range
568#define AT91C_CKGR_OUTA_0 ((unsigned int) 0x0 << 14) // (CKGR) Please refer to the PLLA datasheet
569#define AT91C_CKGR_OUTA_1 ((unsigned int) 0x1 << 14) // (CKGR) Please refer to the PLLA datasheet
570#define AT91C_CKGR_OUTA_2 ((unsigned int) 0x2 << 14) // (CKGR) Please refer to the PLLA datasheet
571#define AT91C_CKGR_OUTA_3 ((unsigned int) 0x3 << 14) // (CKGR) Please refer to the PLLA datasheet
572#define AT91C_CKGR_MULA ((unsigned int) 0x7FF << 16) // (CKGR) PLL A Multiplier
573#define AT91C_CKGR_SRCA ((unsigned int) 0x1 << 29) // (CKGR) PLL A Source
574// -------- CKGR_PLLBR : (CKGR Offset: 0xc) PLL B Register --------
575#define AT91C_CKGR_DIVB ((unsigned int) 0xFF << 0) // (CKGR) Divider Selected
576#define AT91C_CKGR_DIVB_0 ((unsigned int) 0x0) // (CKGR) Divider output is 0
577#define AT91C_CKGR_DIVB_BYPASS ((unsigned int) 0x1) // (CKGR) Divider is bypassed
578#define AT91C_CKGR_PLLBCOUNT ((unsigned int) 0x3F << 8) // (CKGR) PLL B Counter
579#define AT91C_CKGR_OUTB ((unsigned int) 0x3 << 14) // (CKGR) PLL B Output Frequency Range
580#define AT91C_CKGR_OUTB_0 ((unsigned int) 0x0 << 14) // (CKGR) Please refer to the PLLB datasheet
581#define AT91C_CKGR_OUTB_1 ((unsigned int) 0x1 << 14) // (CKGR) Please refer to the PLLB datasheet
582#define AT91C_CKGR_OUTB_2 ((unsigned int) 0x2 << 14) // (CKGR) Please refer to the PLLB datasheet
583#define AT91C_CKGR_OUTB_3 ((unsigned int) 0x3 << 14) // (CKGR) Please refer to the PLLB datasheet
584#define AT91C_CKGR_MULB ((unsigned int) 0x7FF << 16) // (CKGR) PLL B Multiplier
585#define AT91C_CKGR_USB_96M ((unsigned int) 0x1 << 28) // (CKGR) Divider for USB Ports
586#define AT91C_CKGR_USB_PLL ((unsigned int) 0x1 << 29) // (CKGR) PLL Use
587
588// *****************************************************************************
589// SOFTWARE API DEFINITION FOR Parallel Input Output Controler
590// *****************************************************************************
591typedef struct _AT91S_PIO {
592    AT91_REG PIO_PER; // PIO Enable Register
593    AT91_REG PIO_PDR; // PIO Disable Register
594    AT91_REG PIO_PSR; // PIO Status Register
595    AT91_REG Reserved0[1]; //
596    AT91_REG PIO_OER; // Output Enable Register
597    AT91_REG PIO_ODR; // Output Disable Registerr
598    AT91_REG PIO_OSR; // Output Status Register
599    AT91_REG Reserved1[1]; //
600    AT91_REG PIO_IFER; // Input Filter Enable Register
601    AT91_REG PIO_IFDR; // Input Filter Disable Register
602    AT91_REG PIO_IFSR; // Input Filter Status Register
603    AT91_REG Reserved2[1]; //
604    AT91_REG PIO_SODR; // Set Output Data Register
605    AT91_REG PIO_CODR; // Clear Output Data Register
606    AT91_REG PIO_ODSR; // Output Data Status Register
607    AT91_REG PIO_PDSR; // Pin Data Status Register
608    AT91_REG PIO_IER; // Interrupt Enable Register
609    AT91_REG PIO_IDR; // Interrupt Disable Register
610    AT91_REG PIO_IMR; // Interrupt Mask Register
611    AT91_REG PIO_ISR; // Interrupt Status Register
612    AT91_REG PIO_MDER; // Multi-driver Enable Register
613    AT91_REG PIO_MDDR; // Multi-driver Disable Register
614    AT91_REG PIO_MDSR; // Multi-driver Status Register
615    AT91_REG Reserved3[1]; //
616    AT91_REG PIO_PPUDR; // Pull-up Disable Register
617    AT91_REG PIO_PPUER; // Pull-up Enable Register
618    AT91_REG PIO_PPUSR; // Pad Pull-up Status Register
619    AT91_REG Reserved4[1]; //
620    AT91_REG PIO_ASR; // Select A Register
621    AT91_REG PIO_BSR; // Select B Register
622    AT91_REG PIO_ABSR; // AB Select Status Register
623    AT91_REG Reserved5[9]; //
624    AT91_REG PIO_OWER; // Output Write Enable Register
625    AT91_REG PIO_OWDR; // Output Write Disable Register
626    AT91_REG PIO_OWSR; // Output Write Status Register
627} AT91S_PIO, *AT91PS_PIO;
628
629
630// *****************************************************************************
631// SOFTWARE API DEFINITION FOR Debug Unit
632// *****************************************************************************
633typedef struct _AT91S_DBGU {
634    AT91_REG DBGU_CR; // Control Register
635    AT91_REG DBGU_MR; // Mode Register
636    AT91_REG DBGU_IER; // Interrupt Enable Register
637    AT91_REG DBGU_IDR; // Interrupt Disable Register
638    AT91_REG DBGU_IMR; // Interrupt Mask Register
639    AT91_REG DBGU_CSR; // Channel Status Register
640    AT91_REG DBGU_RHR; // Receiver Holding Register
641    AT91_REG DBGU_THR; // Transmitter Holding Register
642    AT91_REG DBGU_BRGR; // Baud Rate Generator Register
643    AT91_REG Reserved0[7]; //
644    AT91_REG DBGU_C1R; // Chip ID1 Register
645    AT91_REG DBGU_C2R; // Chip ID2 Register
646    AT91_REG DBGU_FNTR; // Force NTRST Register
647    AT91_REG Reserved1[45]; //
648    AT91_REG DBGU_RPR; // Receive Pointer Register
649    AT91_REG DBGU_RCR; // Receive Counter Register
650    AT91_REG DBGU_TPR; // Transmit Pointer Register
651    AT91_REG DBGU_TCR; // Transmit Counter Register
652    AT91_REG DBGU_RNPR; // Receive Next Pointer Register
653    AT91_REG DBGU_RNCR; // Receive Next Counter Register
654    AT91_REG DBGU_TNPR; // Transmit Next Pointer Register
655    AT91_REG DBGU_TNCR; // Transmit Next Counter Register
656    AT91_REG DBGU_PTCR; // PDC Transfer Control Register
657    AT91_REG DBGU_PTSR; // PDC Transfer Status Register
658} AT91S_DBGU, *AT91PS_DBGU;
659
660// -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register --------
661#define AT91C_US_RSTRX ((unsigned int) 0x1 << 2) // (DBGU) Reset Receiver
662#define AT91C_US_RSTTX ((unsigned int) 0x1 << 3) // (DBGU) Reset Transmitter
663#define AT91C_US_RXEN ((unsigned int) 0x1 << 4) // (DBGU) Receiver Enable
664#define AT91C_US_RXDIS ((unsigned int) 0x1 << 5) // (DBGU) Receiver Disable
665#define AT91C_US_TXEN ((unsigned int) 0x1 << 6) // (DBGU) Transmitter Enable
666#define AT91C_US_TXDIS ((unsigned int) 0x1 << 7) // (DBGU) Transmitter Disable
667// -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register --------
668#define AT91C_US_PAR ((unsigned int) 0x7 << 9) // (DBGU) Parity type
669#define AT91C_US_PAR_EVEN ((unsigned int) 0x0 << 9) // (DBGU) Even Parity
670#define AT91C_US_PAR_ODD ((unsigned int) 0x1 << 9) // (DBGU) Odd Parity
671#define AT91C_US_PAR_SPACE ((unsigned int) 0x2 << 9) // (DBGU) Parity forced to 0 (Space)
672#define AT91C_US_PAR_MARK ((unsigned int) 0x3 << 9) // (DBGU) Parity forced to 1 (Mark)
673#define AT91C_US_PAR_NONE ((unsigned int) 0x4 << 9) // (DBGU) No Parity
674#define AT91C_US_PAR_MULTI_DROP ((unsigned int) 0x6 << 9) // (DBGU) Multi-drop mode
675#define AT91C_US_CHMODE ((unsigned int) 0x3 << 14) // (DBGU) Channel Mode
676#define AT91C_US_CHMODE_NORMAL ((unsigned int) 0x0 << 14) // (DBGU) Normal Mode: The USART channel operates as an RX/TX USART.
677#define AT91C_US_CHMODE_AUTO ((unsigned int) 0x1 << 14) // (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin.
678#define AT91C_US_CHMODE_LOCAL ((unsigned int) 0x2 << 14) // (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal.
679#define AT91C_US_CHMODE_REMOTE ((unsigned int) 0x3 << 14) // (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin.
680// -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register --------
681#define AT91C_US_RXRDY ((unsigned int) 0x1 << 0) // (DBGU) RXRDY Interrupt
682#define AT91C_US_TXRDY ((unsigned int) 0x1 << 1) // (DBGU) TXRDY Interrupt
683#define AT91C_US_ENDRX ((unsigned int) 0x1 << 3) // (DBGU) End of Receive Transfer Interrupt
684#define AT91C_US_ENDTX ((unsigned int) 0x1 << 4) // (DBGU) End of Transmit Interrupt
685#define AT91C_US_OVRE ((unsigned int) 0x1 << 5) // (DBGU) Overrun Interrupt
686#define AT91C_US_FRAME ((unsigned int) 0x1 << 6) // (DBGU) Framing Error Interrupt
687#define AT91C_US_PARE ((unsigned int) 0x1 << 7) // (DBGU) Parity Error Interrupt
688#define AT91C_US_TXEMPTY ((unsigned int) 0x1 << 9) // (DBGU) TXEMPTY Interrupt
689#define AT91C_US_TXBUFE ((unsigned int) 0x1 << 11) // (DBGU) TXBUFE Interrupt
690#define AT91C_US_RXBUFF ((unsigned int) 0x1 << 12) // (DBGU) RXBUFF Interrupt
691#define AT91C_US_COMM_TX ((unsigned int) 0x1 << 30) // (DBGU) COMM_TX Interrupt
692#define AT91C_US_COMM_RX ((unsigned int) 0x1 << 31) // (DBGU) COMM_RX Interrupt
693// -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register --------
694// -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register --------
695// -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register --------
696// -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register --------
697#define AT91C_US_FORCE_NTRST ((unsigned int) 0x1 << 0) // (DBGU) Force NTRST in JTAG
698
699// *****************************************************************************
700// SOFTWARE API DEFINITION FOR Peripheral Data Controller
701// *****************************************************************************
702typedef struct _AT91S_PDC {
703    AT91_REG PDC_RPR; // Receive Pointer Register
704    AT91_REG PDC_RCR; // Receive Counter Register
705    AT91_REG PDC_TPR; // Transmit Pointer Register
706    AT91_REG PDC_TCR; // Transmit Counter Register
707    AT91_REG PDC_RNPR; // Receive Next Pointer Register
708    AT91_REG PDC_RNCR; // Receive Next Counter Register
709    AT91_REG PDC_TNPR; // Transmit Next Pointer Register
710    AT91_REG PDC_TNCR; // Transmit Next Counter Register
711    AT91_REG PDC_PTCR; // PDC Transfer Control Register
712    AT91_REG PDC_PTSR; // PDC Transfer Status Register
713} AT91S_PDC, *AT91PS_PDC;
714
715// -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register --------
716#define AT91C_PDC_RXTEN ((unsigned int) 0x1 << 0) // (PDC) Receiver Transfer Enable
717#define AT91C_PDC_RXTDIS ((unsigned int) 0x1 << 1) // (PDC) Receiver Transfer Disable
718#define AT91C_PDC_TXTEN ((unsigned int) 0x1 << 8) // (PDC) Transmitter Transfer Enable
719#define AT91C_PDC_TXTDIS ((unsigned int) 0x1 << 9) // (PDC) Transmitter Transfer Disable
720// -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register --------
721
722// *****************************************************************************
723// SOFTWARE API DEFINITION FOR Advanced Interrupt Controller
724// *****************************************************************************
725typedef struct _AT91S_AIC {
726    AT91_REG AIC_SMR[32]; // Source Mode Register
727    AT91_REG AIC_SVR[32]; // Source Vector Register
728    AT91_REG AIC_IVR; // IRQ Vector Register
729    AT91_REG AIC_FVR; // FIQ Vector Register
730    AT91_REG AIC_ISR; // Interrupt Status Register
731    AT91_REG AIC_IPR; // Interrupt Pending Register
732    AT91_REG AIC_IMR; // Interrupt Mask Register
733    AT91_REG AIC_CISR; // Core Interrupt Status Register
734    AT91_REG Reserved0[2]; //
735    AT91_REG AIC_IECR; // Interrupt Enable Command Register
736    AT91_REG AIC_IDCR; // Interrupt Disable Command Register
737    AT91_REG AIC_ICCR; // Interrupt Clear Command Register
738    AT91_REG AIC_ISCR; // Interrupt Set Command Register
739    AT91_REG AIC_EOICR; // End of Interrupt Command Register
740    AT91_REG AIC_SPU; // Spurious Vector Register
741    AT91_REG AIC_DCR; // Debug Control Register (Protect)
742    AT91_REG Reserved1[1]; //
743    AT91_REG AIC_FFER; // Fast Forcing Enable Register
744    AT91_REG AIC_FFDR; // Fast Forcing Disable Register
745    AT91_REG AIC_FFSR; // Fast Forcing Status Register
746} AT91S_AIC, *AT91PS_AIC;
747
748// -------- AIC_SMR : (AIC Offset: 0x0) Control Register --------
749#define AT91C_AIC_PRIOR ((unsigned int) 0x7 << 0) // (AIC) Priority Level
750#define AT91C_AIC_PRIOR_LOWEST ((unsigned int) 0x0) // (AIC) Lowest priority level
751#define AT91C_AIC_PRIOR_HIGHEST ((unsigned int) 0x7) // (AIC) Highest priority level
752#define AT91C_AIC_SRCTYPE ((unsigned int) 0x3 << 5) // (AIC) Interrupt Source Type
753#define AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE ((unsigned int) 0x0 << 5) // (AIC) Internal Sources Code Label Level Sensitive
754#define AT91C_AIC_SRCTYPE_INT_EDGE_TRIGGERED ((unsigned int) 0x1 << 5) // (AIC) Internal Sources Code Label Edge triggered
755#define AT91C_AIC_SRCTYPE_EXT_HIGH_LEVEL ((unsigned int) 0x2 << 5) // (AIC) External Sources Code Label High-level Sensitive
756#define AT91C_AIC_SRCTYPE_EXT_POSITIVE_EDGE ((unsigned int) 0x3 << 5) // (AIC) External Sources Code Label Positive Edge triggered
757// -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register --------
758#define AT91C_AIC_NFIQ ((unsigned int) 0x1 << 0) // (AIC) NFIQ Status
759#define AT91C_AIC_NIRQ ((unsigned int) 0x1 << 1) // (AIC) NIRQ Status
760// -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) --------
761#define AT91C_AIC_DCR_PROT ((unsigned int) 0x1 << 0) // (AIC) Protection Mode
762#define AT91C_AIC_DCR_GMSK ((unsigned int) 0x1 << 1) // (AIC) General Mask
763
764// *****************************************************************************
765// SOFTWARE API DEFINITION FOR Serial Parallel Interface
766// *****************************************************************************
767typedef struct _AT91S_SPI {
768    AT91_REG SPI_CR; // Control Register
769    AT91_REG SPI_MR; // Mode Register
770    AT91_REG SPI_RDR; // Receive Data Register
771    AT91_REG SPI_TDR; // Transmit Data Register
772    AT91_REG SPI_SR; // Status Register
773    AT91_REG SPI_IER; // Interrupt Enable Register
774    AT91_REG SPI_IDR; // Interrupt Disable Register
775    AT91_REG SPI_IMR; // Interrupt Mask Register
776    AT91_REG Reserved0[4]; //
777    AT91_REG SPI_CSR[4]; // Chip Select Register
778    AT91_REG Reserved1[48]; //
779    AT91_REG SPI_RPR; // Receive Pointer Register
780    AT91_REG SPI_RCR; // Receive Counter Register
781    AT91_REG SPI_TPR; // Transmit Pointer Register
782    AT91_REG SPI_TCR; // Transmit Counter Register
783    AT91_REG SPI_RNPR; // Receive Next Pointer Register
784    AT91_REG SPI_RNCR; // Receive Next Counter Register
785    AT91_REG SPI_TNPR; // Transmit Next Pointer Register
786    AT91_REG SPI_TNCR; // Transmit Next Counter Register
787    AT91_REG SPI_PTCR; // PDC Transfer Control Register
788    AT91_REG SPI_PTSR; // PDC Transfer Status Register
789} AT91S_SPI, *AT91PS_SPI;
790
791// -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register --------
792#define AT91C_SPI_SPIEN ((unsigned int) 0x1 << 0) // (SPI) SPI Enable
793#define AT91C_SPI_SPIDIS ((unsigned int) 0x1 << 1) // (SPI) SPI Disable
794#define AT91C_SPI_SWRST ((unsigned int) 0x1 << 7) // (SPI) SPI Software reset
795// -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register --------
796#define AT91C_SPI_MSTR ((unsigned int) 0x1 << 0) // (SPI) Master/Slave Mode
797#define AT91C_SPI_PS ((unsigned int) 0x1 << 1) // (SPI) Peripheral Select
798#define AT91C_SPI_PS_FIXED ((unsigned int) 0x0 << 1) // (SPI) Fixed Peripheral Select
799#define AT91C_SPI_PS_VARIABLE ((unsigned int) 0x1 << 1) // (SPI) Variable Peripheral Select
800#define AT91C_SPI_PCSDEC ((unsigned int) 0x1 << 2) // (SPI) Chip Select Decode
801#define AT91C_SPI_DIV32 ((unsigned int) 0x1 << 3) // (SPI) Clock Selection
802#define AT91C_SPI_MODFDIS ((unsigned int) 0x1 << 4) // (SPI) Mode Fault Detection
803#define AT91C_SPI_LLB ((unsigned int) 0x1 << 7) // (SPI) Clock Selection
804#define AT91C_SPI_PCS ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select
805#define AT91C_SPI_DLYBCS ((unsigned int) 0xFF << 24) // (SPI) Delay Between Chip Selects
806// -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register --------
807#define AT91C_SPI_RD ((unsigned int) 0xFFFF << 0) // (SPI) Receive Data
808#define AT91C_SPI_RPCS ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select Status
809// -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register --------
810#define AT91C_SPI_TD ((unsigned int) 0xFFFF << 0) // (SPI) Transmit Data
811#define AT91C_SPI_TPCS ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select Status
812// -------- SPI_SR : (SPI Offset: 0x10) Status Register --------
813#define AT91C_SPI_RDRF ((unsigned int) 0x1 << 0) // (SPI) Receive Data Register Full
814#define AT91C_SPI_TDRE ((unsigned int) 0x1 << 1) // (SPI) Transmit Data Register Empty
815#define AT91C_SPI_MODF ((unsigned int) 0x1 << 2) // (SPI) Mode Fault Error
816#define AT91C_SPI_OVRES ((unsigned int) 0x1 << 3) // (SPI) Overrun Error Status
817#define AT91C_SPI_SPENDRX ((unsigned int) 0x1 << 4) // (SPI) End of Receiver Transfer
818#define AT91C_SPI_SPENDTX ((unsigned int) 0x1 << 5) // (SPI) End of Receiver Transfer
819#define AT91C_SPI_RXBUFF ((unsigned int) 0x1 << 6) // (SPI) RXBUFF Interrupt
820#define AT91C_SPI_TXBUFE ((unsigned int) 0x1 << 7) // (SPI) TXBUFE Interrupt
821#define AT91C_SPI_SPIENS ((unsigned int) 0x1 << 16) // (SPI) Enable Status
822// -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register --------
823// -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register --------
824// -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register --------
825// -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register --------
826#define AT91C_SPI_CPOL ((unsigned int) 0x1 << 0) // (SPI) Clock Polarity
827#define AT91C_SPI_NCPHA ((unsigned int) 0x1 << 1) // (SPI) Clock Phase
828#define AT91C_SPI_BITS ((unsigned int) 0xF << 4) // (SPI) Bits Per Transfer
829#define AT91C_SPI_BITS_8 ((unsigned int) 0x0 << 4) // (SPI) 8 Bits Per transfer
830#define AT91C_SPI_BITS_9 ((unsigned int) 0x1 << 4) // (SPI) 9 Bits Per transfer
831#define AT91C_SPI_BITS_10 ((unsigned int) 0x2 << 4) // (SPI) 10 Bits Per transfer
832#define AT91C_SPI_BITS_11 ((unsigned int) 0x3 << 4) // (SPI) 11 Bits Per transfer
833#define AT91C_SPI_BITS_12 ((unsigned int) 0x4 << 4) // (SPI) 12 Bits Per transfer
834#define AT91C_SPI_BITS_13 ((unsigned int) 0x5 << 4) // (SPI) 13 Bits Per transfer
835#define AT91C_SPI_BITS_14 ((unsigned int) 0x6 << 4) // (SPI) 14 Bits Per transfer
836#define AT91C_SPI_BITS_15 ((unsigned int) 0x7 << 4) // (SPI) 15 Bits Per transfer
837#define AT91C_SPI_BITS_16 ((unsigned int) 0x8 << 4) // (SPI) 16 Bits Per transfer
838#define AT91C_SPI_SCBR ((unsigned int) 0xFF << 8) // (SPI) Serial Clock Baud Rate
839#define AT91C_SPI_DLYBS ((unsigned int) 0xFF << 16) // (SPI) Serial Clock Baud Rate
840#define AT91C_SPI_DLYBCT ((unsigned int) 0xFF << 24) // (SPI) Delay Between Consecutive Transfers
841
842// *****************************************************************************
843// SOFTWARE API DEFINITION FOR Synchronous Serial Controller Interface
844// *****************************************************************************
845typedef struct _AT91S_SSC {
846    AT91_REG SSC_CR; // Control Register
847    AT91_REG SSC_CMR; // Clock Mode Register
848    AT91_REG Reserved0[2]; //
849    AT91_REG SSC_RCMR; // Receive Clock ModeRegister
850    AT91_REG SSC_RFMR; // Receive Frame Mode Register
851    AT91_REG SSC_TCMR; // Transmit Clock Mode Register
852    AT91_REG SSC_TFMR; // Transmit Frame Mode Register
853    AT91_REG SSC_RHR; // Receive Holding Register
854    AT91_REG SSC_THR; // Transmit Holding Register
855    AT91_REG Reserved1[2]; //
856    AT91_REG SSC_RSHR; // Receive Sync Holding Register
857    AT91_REG SSC_TSHR; // Transmit Sync Holding Register
858    AT91_REG SSC_RC0R; // Receive Compare 0 Register
859    AT91_REG SSC_RC1R; // Receive Compare 1 Register
860    AT91_REG SSC_SR; // Status Register
861    AT91_REG SSC_IER; // Interrupt Enable Register
862    AT91_REG SSC_IDR; // Interrupt Disable Register
863    AT91_REG SSC_IMR; // Interrupt Mask Register
864    AT91_REG Reserved2[44]; //
865    AT91_REG SSC_RPR; // Receive Pointer Register
866    AT91_REG SSC_RCR; // Receive Counter Register
867    AT91_REG SSC_TPR; // Transmit Pointer Register
868    AT91_REG SSC_TCR; // Transmit Counter Register
869    AT91_REG SSC_RNPR; // Receive Next Pointer Register
870    AT91_REG SSC_RNCR; // Receive Next Counter Register
871    AT91_REG SSC_TNPR; // Transmit Next Pointer Register
872    AT91_REG SSC_TNCR; // Transmit Next Counter Register
873    AT91_REG SSC_PTCR; // PDC Transfer Control Register
874    AT91_REG SSC_PTSR; // PDC Transfer Status Register
875} AT91S_SSC, *AT91PS_SSC;
876
877// -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register --------
878#define AT91C_SSC_RXEN ((unsigned int) 0x1 << 0) // (SSC) Receive Enable
879#define AT91C_SSC_RXDIS ((unsigned int) 0x1 << 1) // (SSC) Receive Disable
880#define AT91C_SSC_TXEN ((unsigned int) 0x1 << 8) // (SSC) Transmit Enable
881#define AT91C_SSC_TXDIS ((unsigned int) 0x1 << 9) // (SSC) Transmit Disable
882#define AT91C_SSC_SWRST ((unsigned int) 0x1 << 15) // (SSC) Software Reset
883// -------- SSC_RCMR : (SSC Offset: 0x10) SSC Receive Clock Mode Register --------
884#define AT91C_SSC_CKS ((unsigned int) 0x3 << 0) // (SSC) Receive/Transmit Clock Selection
885#define AT91C_SSC_CKS_DIV ((unsigned int) 0x0) // (SSC) Divided Clock
886#define AT91C_SSC_CKS_TK ((unsigned int) 0x1) // (SSC) TK Clock signal
887#define AT91C_SSC_CKS_RK ((unsigned int) 0x2) // (SSC) RK pin
888#define AT91C_SSC_CKO ((unsigned int) 0x7 << 2) // (SSC) Receive/Transmit Clock Output Mode Selection
889#define AT91C_SSC_CKO_NONE ((unsigned int) 0x0 << 2) // (SSC) Receive/Transmit Clock Output Mode: None RK pin: Input-only
890#define AT91C_SSC_CKO_CONTINOUS ((unsigned int) 0x1 << 2) // (SSC) Continuous Receive/Transmit Clock RK pin: Output
891#define AT91C_SSC_CKO_DATA_TX ((unsigned int) 0x2 << 2) // (SSC) Receive/Transmit Clock only during data transfers RK pin: Output
892#define AT91C_SSC_CKI ((unsigned int) 0x1 << 5) // (SSC) Receive/Transmit Clock Inversion
893#define AT91C_SSC_CKG ((unsigned int) 0x3 << 6) // (SSC) Receive/Transmit Clock Gating Selection
894#define AT91C_SSC_CKG_NONE ((unsigned int) 0x0 << 6) // (SSC) Receive/Transmit Clock Gating: None, continuous clock
895#define AT91C_SSC_CKG_LOW ((unsigned int) 0x1 << 6) // (SSC) Receive/Transmit Clock enabled only if RF Low
896#define AT91C_SSC_CKG_HIGH ((unsigned int) 0x2 << 6) // (SSC) Receive/Transmit Clock enabled only if RF High
897#define AT91C_SSC_START ((unsigned int) 0xF << 8) // (SSC) Receive/Transmit Start Selection
898#define AT91C_SSC_START_CONTINOUS ((unsigned int) 0x0 << 8) // (SSC) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data.
899#define AT91C_SSC_START_TX ((unsigned int) 0x1 << 8) // (SSC) Transmit/Receive start
900#define AT91C_SSC_START_LOW_RF ((unsigned int) 0x2 << 8) // (SSC) Detection of a low level on RF input
901#define AT91C_SSC_START_HIGH_RF ((unsigned int) 0x3 << 8) // (SSC) Detection of a high level on RF input
902#define AT91C_SSC_START_FALL_RF ((unsigned int) 0x4 << 8) // (SSC) Detection of a falling edge on RF input
903#define AT91C_SSC_START_RISE_RF ((unsigned int) 0x5 << 8) // (SSC) Detection of a rising edge on RF input
904#define AT91C_SSC_START_LEVEL_RF ((unsigned int) 0x6 << 8) // (SSC) Detection of any level change on RF input
905#define AT91C_SSC_START_EDGE_RF ((unsigned int) 0x7 << 8) // (SSC) Detection of any edge on RF input
906#define AT91C_SSC_START_0 ((unsigned int) 0x8 << 8) // (SSC) Compare 0
907#define AT91C_SSC_STOP ((unsigned int) 0x1 << 12) // (SSC) Receive Stop Selection
908#define AT91C_SSC_STTOUT ((unsigned int) 0x1 << 15) // (SSC) Receive/Transmit Start Output Selection
909#define AT91C_SSC_STTDLY ((unsigned int) 0xFF << 16) // (SSC) Receive/Transmit Start Delay
910#define AT91C_SSC_PERIOD ((unsigned int) 0xFF << 24) // (SSC) Receive/Transmit Period Divider Selection
911// -------- SSC_RFMR : (SSC Offset: 0x14) SSC Receive Frame Mode Register --------
912#define AT91C_SSC_DATLEN ((unsigned int) 0x1F << 0) // (SSC) Data Length
913#define AT91C_SSC_LOOP ((unsigned int) 0x1 << 5) // (SSC) Loop Mode
914#define AT91C_SSC_MSBF ((unsigned int) 0x1 << 7) // (SSC) Most Significant Bit First
915#define AT91C_SSC_DATNB ((unsigned int) 0xF << 8) // (SSC) Data Number per Frame
916#define AT91C_SSC_FSLEN ((unsigned int) 0xF << 16) // (SSC) Receive/Transmit Frame Sync length
917#define AT91C_SSC_FSOS ((unsigned int) 0x7 << 20) // (SSC) Receive/Transmit Frame Sync Output Selection
918#define AT91C_SSC_FSOS_NONE ((unsigned int) 0x0 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: None RK pin Input-only
919#define AT91C_SSC_FSOS_NEGATIVE ((unsigned int) 0x1 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Negative Pulse
920#define AT91C_SSC_FSOS_POSITIVE ((unsigned int) 0x2 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Positive Pulse
921#define AT91C_SSC_FSOS_LOW ((unsigned int) 0x3 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver Low during data transfer
922#define AT91C_SSC_FSOS_HIGH ((unsigned int) 0x4 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver High during data transfer
923#define AT91C_SSC_FSOS_TOGGLE ((unsigned int) 0x5 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Toggling at each start of data transfer
924#define AT91C_SSC_FSEDGE ((unsigned int) 0x1 << 24) // (SSC) Frame Sync Edge Detection
925// -------- SSC_TCMR : (SSC Offset: 0x18) SSC Transmit Clock Mode Register --------
926// -------- SSC_TFMR : (SSC Offset: 0x1c) SSC Transmit Frame Mode Register --------
927#define AT91C_SSC_DATDEF ((unsigned int) 0x1 << 5) // (SSC) Data Default Value
928#define AT91C_SSC_FSDEN ((unsigned int) 0x1 << 23) // (SSC) Frame Sync Data Enable
929// -------- SSC_SR : (SSC Offset: 0x40) SSC Status Register --------
930#define AT91C_SSC_TXRDY ((unsigned int) 0x1 << 0) // (SSC) Transmit Ready
931#define AT91C_SSC_TXEMPTY ((unsigned int) 0x1 << 1) // (SSC) Transmit Empty
932#define AT91C_SSC_ENDTX ((unsigned int) 0x1 << 2) // (SSC) End Of Transmission
933#define AT91C_SSC_TXBUFE ((unsigned int) 0x1 << 3) // (SSC) Transmit Buffer Empty
934#define AT91C_SSC_RXRDY ((unsigned int) 0x1 << 4) // (SSC) Receive Ready
935#define AT91C_SSC_OVRUN ((unsigned int) 0x1 << 5) // (SSC) Receive Overrun
936#define AT91C_SSC_ENDRX ((unsigned int) 0x1 << 6) // (SSC) End of Reception
937#define AT91C_SSC_RXBUFF ((unsigned int) 0x1 << 7) // (SSC) Receive Buffer Full
938#define AT91C_SSC_CP0 ((unsigned int) 0x1 << 8) // (SSC) Compare 0
939#define AT91C_SSC_CP1 ((unsigned int) 0x1 << 9) // (SSC) Compare 1
940#define AT91C_SSC_TXSYN ((unsigned int) 0x1 << 10) // (SSC) Transmit Sync
941#define AT91C_SSC_RXSYN ((unsigned int) 0x1 << 11) // (SSC) Receive Sync
942#define AT91C_SSC_TXENA ((unsigned int) 0x1 << 16) // (SSC) Transmit Enable
943#define AT91C_SSC_RXENA ((unsigned int) 0x1 << 17) // (SSC) Receive Enable
944// -------- SSC_IER : (SSC Offset: 0x44) SSC Interrupt Enable Register --------
945// -------- SSC_IDR : (SSC Offset: 0x48) SSC Interrupt Disable Register --------
946// -------- SSC_IMR : (SSC Offset: 0x4c) SSC Interrupt Mask Register --------
947
948// *****************************************************************************
949// SOFTWARE API DEFINITION FOR Usart
950// *****************************************************************************
951typedef struct _AT91S_USART {
952    AT91_REG US_CR; // Control Register
953    AT91_REG US_MR; // Mode Register
954    AT91_REG US_IER; // Interrupt Enable Register
955    AT91_REG US_IDR; // Interrupt Disable Register
956    AT91_REG US_IMR; // Interrupt Mask Register
957    AT91_REG US_CSR; // Channel Status Register
958    AT91_REG US_RHR; // Receiver Holding Register
959    AT91_REG US_THR; // Transmitter Holding Register
960    AT91_REG US_BRGR; // Baud Rate Generator Register
961    AT91_REG US_RTOR; // Receiver Time-out Register
962    AT91_REG US_TTGR; // Transmitter Time-guard Register
963    AT91_REG Reserved0[5]; //
964    AT91_REG US_FIDI; // FI_DI_Ratio Register
965    AT91_REG US_NER; // Nb Errors Register
966    AT91_REG US_XXR; // XON_XOFF Register
967    AT91_REG US_IF; // IRDA_FILTER Register
968    AT91_REG Reserved1[44]; //
969    AT91_REG US_RPR; // Receive Pointer Register
970    AT91_REG US_RCR; // Receive Counter Register
971    AT91_REG US_TPR; // Transmit Pointer Register
972    AT91_REG US_TCR; // Transmit Counter Register
973    AT91_REG US_RNPR; // Receive Next Pointer Register
974    AT91_REG US_RNCR; // Receive Next Counter Register
975    AT91_REG US_TNPR; // Transmit Next Pointer Register
976    AT91_REG US_TNCR; // Transmit Next Counter Register
977    AT91_REG US_PTCR; // PDC Transfer Control Register
978    AT91_REG US_PTSR; // PDC Transfer Status Register
979} AT91S_USART, *AT91PS_USART;
980
981// -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register --------
982#define AT91C_US_RSTSTA ((unsigned int) 0x1 << 8) // (USART) Reset Status Bits
983#define AT91C_US_STTBRK ((unsigned int) 0x1 << 9) // (USART) Start Break
984#define AT91C_US_STPBRK ((unsigned int) 0x1 << 10) // (USART) Stop Break
985#define AT91C_US_STTTO ((unsigned int) 0x1 << 11) // (USART) Start Time-out
986#define AT91C_US_SENDA ((unsigned int) 0x1 << 12) // (USART) Send Address
987#define AT91C_US_RSTIT ((unsigned int) 0x1 << 13) // (USART) Reset Iterations
988#define AT91C_US_RSTNACK ((unsigned int) 0x1 << 14) // (USART) Reset Non Acknowledge
989#define AT91C_US_RETTO ((unsigned int) 0x1 << 15) // (USART) Rearm Time-out
990#define AT91C_US_DTREN ((unsigned int) 0x1 << 16) // (USART) Data Terminal ready Enable
991#define AT91C_US_DTRDIS ((unsigned int) 0x1 << 17) // (USART) Data Terminal ready Disable
992#define AT91C_US_RTSEN ((unsigned int) 0x1 << 18) // (USART) Request to Send enable
993#define AT91C_US_RTSDIS ((unsigned int) 0x1 << 19) // (USART) Request to Send Disable
994// -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register --------
995#define AT91C_US_USMODE ((unsigned int) 0xF << 0) // (USART) Usart mode
996#define AT91C_US_USMODE_NORMAL ((unsigned int) 0x0) // (USART) Normal
997#define AT91C_US_USMODE_RS485 ((unsigned int) 0x1) // (USART) RS485
998#define AT91C_US_USMODE_HWHSH ((unsigned int) 0x2) // (USART) Hardware Handshaking
999#define AT91C_US_USMODE_MODEM ((unsigned int) 0x3) // (USART) Modem
1000#define AT91C_US_USMODE_ISO7816_0 ((unsigned int) 0x4) // (USART) ISO7816 protocol: T = 0
1001#define AT91C_US_USMODE_ISO7816_1 ((unsigned int) 0x6) // (USART) ISO7816 protocol: T = 1
1002#define AT91C_US_USMODE_IRDA ((unsigned int) 0x8) // (USART) IrDA
1003#define AT91C_US_USMODE_SWHSH ((unsigned int) 0xC) // (USART) Software Handshaking
1004#define AT91C_US_CLKS ((unsigned int) 0x3 << 4) // (USART) Clock Selection (Baud Rate generator Input Clock
1005#define AT91C_US_CLKS_CLOCK ((unsigned int) 0x0 << 4) // (USART) Clock
1006#define AT91C_US_CLKS_FDIV1 ((unsigned int) 0x1 << 4) // (USART) fdiv1
1007#define AT91C_US_CLKS_SLOW ((unsigned int) 0x2 << 4) // (USART) slow_clock (ARM)
1008#define AT91C_US_CLKS_EXT ((unsigned int) 0x3 << 4) // (USART) External (SCK)
1009#define AT91C_US_CHRL ((unsigned int) 0x3 << 6) // (USART) Clock Selection (Baud Rate generator Input Clock
1010#define AT91C_US_CHRL_5_BITS ((unsigned int) 0x0 << 6) // (USART) Character Length: 5 bits
1011#define AT91C_US_CHRL_6_BITS ((unsigned int) 0x1 << 6) // (USART) Character Length: 6 bits
1012#define AT91C_US_CHRL_7_BITS ((unsigned int) 0x2 << 6) // (USART) Character Length: 7 bits
1013#define AT91C_US_CHRL_8_BITS ((unsigned int) 0x3 << 6) // (USART) Character Length: 8 bits
1014#define AT91C_US_SYNC ((unsigned int) 0x1 << 8) // (USART) Synchronous Mode Select
1015#define AT91C_US_NBSTOP ((unsigned int) 0x3 << 12) // (USART) Number of Stop bits
1016#define AT91C_US_NBSTOP_1_BIT ((unsigned int) 0x0 << 12) // (USART) 1 stop bit
1017#define AT91C_US_NBSTOP_15_BIT ((unsigned int) 0x1 << 12) // (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits
1018#define AT91C_US_NBSTOP_2_BIT ((unsigned int) 0x2 << 12) // (USART) 2 stop bits
1019#define AT91C_US_MSBF ((unsigned int) 0x1 << 16) // (USART) Bit Order
1020#define AT91C_US_MODE9 ((unsigned int) 0x1 << 17) // (USART) 9-bit Character length
1021#define AT91C_US_CKLO ((unsigned int) 0x1 << 18) // (USART) Clock Output Select
1022#define AT91C_US_OVER ((unsigned int) 0x1 << 19) // (USART) Over Sampling Mode
1023#define AT91C_US_INACK ((unsigned int) 0x1 << 20) // (USART) Inhibit Non Acknowledge
1024#define AT91C_US_DSNACK ((unsigned int) 0x1 << 21) // (USART) Disable Successive NACK
1025#define AT91C_US_MAX_ITER ((unsigned int) 0x1 << 24) // (USART) Number of Repetitions
1026#define AT91C_US_FILTER ((unsigned int) 0x1 << 28) // (USART) Receive Line Filter
1027// -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register --------
1028#define AT91C_US_RXBRK ((unsigned int) 0x1 << 2) // (USART) Break Received/End of Break
1029#define AT91C_US_TIMEOUT ((unsigned int) 0x1 << 8) // (USART) Receiver Time-out
1030#define AT91C_US_ITERATION ((unsigned int) 0x1 << 10) // (USART) Max number of Repetitions Reached
1031#define AT91C_US_NACK ((unsigned int) 0x1 << 13) // (USART) Non Acknowledge
1032#define AT91C_US_RIIC ((unsigned int) 0x1 << 16) // (USART) Ring INdicator Input Change Flag
1033#define AT91C_US_DSRIC ((unsigned int) 0x1 << 17) // (USART) Data Set Ready Input Change Flag
1034#define AT91C_US_DCDIC ((unsigned int) 0x1 << 18) // (USART) Data Carrier Flag
1035#define AT91C_US_CTSIC ((unsigned int) 0x1 << 19) // (USART) Clear To Send Input Change Flag
1036// -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register --------
1037// -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register --------
1038// -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register --------
1039#define AT91C_US_RI ((unsigned int) 0x1 << 20) // (USART) Image of RI Input
1040#define AT91C_US_DSR ((unsigned int) 0x1 << 21) // (USART) Image of DSR Input
1041#define AT91C_US_DCD ((unsigned int) 0x1 << 22) // (USART) Image of DCD Input
1042#define AT91C_US_CTS ((unsigned int) 0x1 << 23) // (USART) Image of CTS Input
1043
1044// *****************************************************************************
1045// SOFTWARE API DEFINITION FOR Two-wire Interface
1046// *****************************************************************************
1047typedef struct _AT91S_TWI {
1048    AT91_REG TWI_CR; // Control Register
1049    AT91_REG TWI_MMR; // Master Mode Register
1050    AT91_REG TWI_SMR; // Slave Mode Register
1051    AT91_REG TWI_IADR; // Internal Address Register
1052    AT91_REG TWI_CWGR; // Clock Waveform Generator Register
1053    AT91_REG Reserved0[3]; //
1054    AT91_REG TWI_SR; // Status Register
1055    AT91_REG TWI_IER; // Interrupt Enable Register
1056    AT91_REG TWI_IDR; // Interrupt Disable Register
1057    AT91_REG TWI_IMR; // Interrupt Mask Register
1058    AT91_REG TWI_RHR; // Receive Holding Register
1059    AT91_REG TWI_THR; // Transmit Holding Register
1060} AT91S_TWI, *AT91PS_TWI;
1061
1062// -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register --------
1063#define AT91C_TWI_START ((unsigned int) 0x1 << 0) // (TWI) Send a START Condition
1064#define AT91C_TWI_STOP ((unsigned int) 0x1 << 1) // (TWI) Send a STOP Condition
1065#define AT91C_TWI_MSEN ((unsigned int) 0x1 << 2) // (TWI) TWI Master Transfer Enabled
1066#define AT91C_TWI_MSDIS ((unsigned int) 0x1 << 3) // (TWI) TWI Master Transfer Disabled
1067#define AT91C_TWI_SVEN ((unsigned int) 0x1 << 4) // (TWI) TWI Slave Transfer Enabled
1068#define AT91C_TWI_SVDIS ((unsigned int) 0x1 << 5) // (TWI) TWI Slave Transfer Disabled
1069#define AT91C_TWI_SWRST ((unsigned int) 0x1 << 7) // (TWI) Software Reset
1070// -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register --------
1071#define AT91C_TWI_IADRSZ ((unsigned int) 0x3 << 8) // (TWI) Internal Device Address Size
1072#define AT91C_TWI_IADRSZ_NO ((unsigned int) 0x0 << 8) // (TWI) No internal device address
1073#define AT91C_TWI_IADRSZ_1_BYTE ((unsigned int) 0x1 << 8) // (TWI) One-byte internal device address
1074#define AT91C_TWI_IADRSZ_2_BYTE ((unsigned int) 0x2 << 8) // (TWI) Two-byte internal device address
1075#define AT91C_TWI_IADRSZ_3_BYTE ((unsigned int) 0x3 << 8) // (TWI) Three-byte internal device address
1076#define AT91C_TWI_MREAD ((unsigned int) 0x1 << 12) // (TWI) Master Read Direction
1077#define AT91C_TWI_DADR ((unsigned int) 0x7F << 16) // (TWI) Device Address
1078// -------- TWI_SMR : (TWI Offset: 0x8) TWI Slave Mode Register --------
1079#define AT91C_TWI_SADR ((unsigned int) 0x7F << 16) // (TWI) Slave Device Address
1080// -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register --------
1081#define AT91C_TWI_CLDIV ((unsigned int) 0xFF << 0) // (TWI) Clock Low Divider
1082#define AT91C_TWI_CHDIV ((unsigned int) 0xFF << 8) // (TWI) Clock High Divider
1083#define AT91C_TWI_CKDIV ((unsigned int) 0x7 << 16) // (TWI) Clock Divider
1084// -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register --------
1085#define AT91C_TWI_TXCOMP ((unsigned int) 0x1 << 0) // (TWI) Transmission Completed
1086#define AT91C_TWI_RXRDY ((unsigned int) 0x1 << 1) // (TWI) Receive holding register ReaDY
1087#define AT91C_TWI_TXRDY ((unsigned int) 0x1 << 2) // (TWI) Transmit holding register ReaDY
1088#define AT91C_TWI_SVREAD ((unsigned int) 0x1 << 3) // (TWI) Slave Read
1089#define AT91C_TWI_SVACC ((unsigned int) 0x1 << 4) // (TWI) Slave Access
1090#define AT91C_TWI_GCACC ((unsigned int) 0x1 << 5) // (TWI) General Call Access
1091#define AT91C_TWI_OVRE ((unsigned int) 0x1 << 6) // (TWI) Overrun Error
1092#define AT91C_TWI_UNRE ((unsigned int) 0x1 << 7) // (TWI) Underrun Error
1093#define AT91C_TWI_NACK ((unsigned int) 0x1 << 8) // (TWI) Not Acknowledged
1094#define AT91C_TWI_ARBLST ((unsigned int) 0x1 << 9) // (TWI) Arbitration Lost
1095// -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register --------
1096// -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register --------
1097// -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register --------
1098
1099// *****************************************************************************
1100// SOFTWARE API DEFINITION FOR Multimedia Card Interface
1101// *****************************************************************************
1102typedef struct _AT91S_MCI {
1103    AT91_REG MCI_CR; // MCI Control Register
1104    AT91_REG MCI_MR; // MCI Mode Register
1105    AT91_REG MCI_DTOR; // MCI Data Timeout Register
1106    AT91_REG MCI_SDCR; // MCI SD Card Register
1107    AT91_REG MCI_ARGR; // MCI Argument Register
1108    AT91_REG MCI_CMDR; // MCI Command Register
1109    AT91_REG Reserved0[2]; //
1110    AT91_REG MCI_RSPR[4]; // MCI Response Register
1111    AT91_REG MCI_RDR; // MCI Receive Data Register
1112    AT91_REG MCI_TDR; // MCI Transmit Data Register
1113    AT91_REG Reserved1[2]; //
1114    AT91_REG MCI_SR; // MCI Status Register
1115    AT91_REG MCI_IER; // MCI Interrupt Enable Register
1116    AT91_REG MCI_IDR; // MCI Interrupt Disable Register
1117    AT91_REG MCI_IMR; // MCI Interrupt Mask Register
1118    AT91_REG Reserved2[44]; //
1119    AT91_REG MCI_RPR; // Receive Pointer Register
1120    AT91_REG MCI_RCR; // Receive Counter Register
1121    AT91_REG MCI_TPR; // Transmit Pointer Register
1122    AT91_REG MCI_TCR; // Transmit Counter Register
1123    AT91_REG MCI_RNPR; // Receive Next Pointer Register
1124    AT91_REG MCI_RNCR; // Receive Next Counter Register
1125    AT91_REG MCI_TNPR; // Transmit Next Pointer Register
1126    AT91_REG MCI_TNCR; // Transmit Next Counter Register
1127    AT91_REG MCI_PTCR; // PDC Transfer Control Register
1128    AT91_REG MCI_PTSR; // PDC Transfer Status Register
1129} AT91S_MCI, *AT91PS_MCI;
1130
1131// -------- MCI_CR : (MCI Offset: 0x0) MCI Control Register --------
1132#define AT91C_MCI_MCIEN ((unsigned int) 0x1 << 0) // (MCI) Multimedia Interface Enable
1133#define AT91C_MCI_MCIDIS ((unsigned int) 0x1 << 1) // (MCI) Multimedia Interface Disable
1134#define AT91C_MCI_PWSEN ((unsigned int) 0x1 << 2) // (MCI) Power Save Mode Enable
1135#define AT91C_MCI_PWSDIS ((unsigned int) 0x1 << 3) // (MCI) Power Save Mode Disable
1136// -------- MCI_MR : (MCI Offset: 0x4) MCI Mode Register --------
1137#define AT91C_MCI_CLKDIV ((unsigned int) 0x1 << 0) // (MCI) Clock Divider
1138#define AT91C_MCI_PWSDIV ((unsigned int) 0x1 << 8) // (MCI) Power Saving Divider
1139#define AT91C_MCI_PDCPADV ((unsigned int) 0x1 << 14) // (MCI) PDC Padding Value
1140#define AT91C_MCI_PDCMODE ((unsigned int) 0x1 << 15) // (MCI) PDC Oriented Mode
1141#define AT91C_MCI_BLKLEN ((unsigned int) 0x1 << 18) // (MCI) Data Block Length
1142// -------- MCI_DTOR : (MCI Offset: 0x8) MCI Data Timeout Register --------
1143#define AT91C_MCI_DTOCYC ((unsigned int) 0x1 << 0) // (MCI) Data Timeout Cycle Number
1144#define AT91C_MCI_DTOMUL ((unsigned int) 0x7 << 4) // (MCI) Data Timeout Multiplier
1145#define AT91C_MCI_DTOMUL_1 ((unsigned int) 0x0 << 4) // (MCI) DTOCYC x 1
1146#define AT91C_MCI_DTOMUL_16 ((unsigned int) 0x1 << 4) // (MCI) DTOCYC x 16
1147#define AT91C_MCI_DTOMUL_128 ((unsigned int) 0x2 << 4) // (MCI) DTOCYC x 128
1148#define AT91C_MCI_DTOMUL_256 ((unsigned int) 0x3 << 4) // (MCI) DTOCYC x 256
1149#define AT91C_MCI_DTOMUL_1024 ((unsigned int) 0x4 << 4) // (MCI) DTOCYC x 1024
1150#define AT91C_MCI_DTOMUL_4096 ((unsigned int) 0x5 << 4) // (MCI) DTOCYC x 4096
1151#define AT91C_MCI_DTOMUL_65536 ((unsigned int) 0x6 << 4) // (MCI) DTOCYC x 65536
1152#define AT91C_MCI_DTOMUL_1048576 ((unsigned int) 0x7 << 4) // (MCI) DTOCYC x 1048576
1153// -------- MCI_SDCR : (MCI Offset: 0xc) MCI SD Card Register --------
1154#define AT91C_MCI_SCDSEL ((unsigned int) 0x1 << 0) // (MCI) SD Card Selector
1155#define AT91C_MCI_SCDBUS ((unsigned int) 0x1 << 7) // (MCI) SD Card Bus Width
1156// -------- MCI_CMDR : (MCI Offset: 0x14) MCI Command Register --------
1157#define AT91C_MCI_CMDNB ((unsigned int) 0x1F << 0) // (MCI) Command Number
1158#define AT91C_MCI_RSPTYP ((unsigned int) 0x3 << 6) // (MCI) Response Type
1159#define AT91C_MCI_RSPTYP_NO ((unsigned int) 0x0 << 6) // (MCI) No response
1160#define AT91C_MCI_RSPTYP_48 ((unsigned int) 0x1 << 6) // (MCI) 48-bit response
1161#define AT91C_MCI_RSPTYP_136 ((unsigned int) 0x2 << 6) // (MCI) 136-bit response
1162#define AT91C_MCI_SPCMD ((unsigned int) 0x7 << 8) // (MCI) Special CMD
1163#define AT91C_MCI_SPCMD_NONE ((unsigned int) 0x0 << 8) // (MCI) Not a special CMD
1164#define AT91C_MCI_SPCMD_INIT ((unsigned int) 0x1 << 8) // (MCI) Initialization CMD
1165#define AT91C_MCI_SPCMD_SYNC ((unsigned int) 0x2 << 8) // (MCI) Synchronized CMD
1166#define AT91C_MCI_SPCMD_IT_CMD ((unsigned int) 0x4 << 8) // (MCI) Interrupt command
1167#define AT91C_MCI_SPCMD_IT_REP ((unsigned int) 0x5 << 8) // (MCI) Interrupt response
1168#define AT91C_MCI_OPDCMD ((unsigned int) 0x1 << 11) // (MCI) Open Drain Command
1169#define AT91C_MCI_MAXLAT ((unsigned int) 0x1 << 12) // (MCI) Maximum Latency for Command to respond
1170#define AT91C_MCI_TRCMD ((unsigned int) 0x3 << 16) // (MCI) Transfer CMD
1171#define AT91C_MCI_TRCMD_NO ((unsigned int) 0x0 << 16) // (MCI) No transfer
1172#define AT91C_MCI_TRCMD_START ((unsigned int) 0x1 << 16) // (MCI) Start transfer
1173#define AT91C_MCI_TRCMD_STOP ((unsigned int) 0x2 << 16) // (MCI) Stop transfer
1174#define AT91C_MCI_TRDIR ((unsigned int) 0x1 << 18) // (MCI) Transfer Direction
1175#define AT91C_MCI_TRTYP ((unsigned int) 0x3 << 19) // (MCI) Transfer Type
1176#define AT91C_MCI_TRTYP_BLOCK ((unsigned int) 0x0 << 19) // (MCI) Block Transfer type
1177#define AT91C_MCI_TRTYP_MULTIPLE ((unsigned int) 0x1 << 19) // (MCI) Multiple Block transfer type
1178#define AT91C_MCI_TRTYP_STREAM ((unsigned int) 0x2 << 19) // (MCI) Stream transfer type
1179// -------- MCI_SR : (MCI Offset: 0x40) MCI Status Register --------
1180#define AT91C_MCI_CMDRDY ((unsigned int) 0x1 << 0) // (MCI) Command Ready flag
1181#define AT91C_MCI_RXRDY ((unsigned int) 0x1 << 1) // (MCI) RX Ready flag
1182#define AT91C_MCI_TXRDY ((unsigned int) 0x1 << 2) // (MCI) TX Ready flag
1183#define AT91C_MCI_BLKE ((unsigned int) 0x1 << 3) // (MCI) Data Block Transfer Ended flag
1184#define AT91C_MCI_DTIP ((unsigned int) 0x1 << 4) // (MCI) Data Transfer in Progress flag
1185#define AT91C_MCI_NOTBUSY ((unsigned int) 0x1 << 5) // (MCI) Data Line Not Busy flag
1186#define AT91C_MCI_ENDRX ((unsigned int) 0x1 << 6) // (MCI) End of RX Buffer flag
1187#define AT91C_MCI_ENDTX ((unsigned int) 0x1 << 7) // (MCI) End of TX Buffer flag
1188#define AT91C_MCI_RXBUFF ((unsigned int) 0x1 << 14) // (MCI) RX Buffer Full flag
1189#define AT91C_MCI_TXBUFE ((unsigned int) 0x1 << 15) // (MCI) TX Buffer Empty flag
1190#define AT91C_MCI_RINDE ((unsigned int) 0x1 << 16) // (MCI) Response Index Error flag
1191#define AT91C_MCI_RDIRE ((unsigned int) 0x1 << 17) // (MCI) Response Direction Error flag
1192#define AT91C_MCI_RCRCE ((unsigned int) 0x1 << 18) // (MCI) Response CRC Error flag
1193#define AT91C_MCI_RENDE ((unsigned int) 0x1 << 19) // (MCI) Response End Bit Error flag
1194#define AT91C_MCI_RTOE ((unsigned int) 0x1 << 20) // (MCI) Response Time-out Error flag
1195#define AT91C_MCI_DCRCE ((unsigned int) 0x1 << 21) // (MCI) data CRC Error flag
1196#define AT91C_MCI_DTOE ((unsigned int) 0x1 << 22) // (MCI) Data timeout Error flag
1197#define AT91C_MCI_OVRE ((unsigned int) 0x1 << 30) // (MCI) Overrun flag
1198#define AT91C_MCI_UNRE ((unsigned int) 0x1 << 31) // (MCI) Underrun flag
1199// -------- MCI_IER : (MCI Offset: 0x44) MCI Interrupt Enable Register --------
1200// -------- MCI_IDR : (MCI Offset: 0x48) MCI Interrupt Disable Register --------
1201// -------- MCI_IMR : (MCI Offset: 0x4c) MCI Interrupt Mask Register --------
1202
1203// *****************************************************************************
1204// SOFTWARE API DEFINITION FOR USB Device Interface
1205// *****************************************************************************
1206typedef struct _AT91S_UDP {
1207    AT91_REG UDP_NUM; // Frame Number Register
1208    AT91_REG UDP_GLBSTATE; // Global State Register
1209    AT91_REG UDP_FADDR; // Function Address Register
1210    AT91_REG Reserved0[1]; //
1211    AT91_REG UDP_IER; // Interrupt Enable Register
1212    AT91_REG UDP_IDR; // Interrupt Disable Register
1213    AT91_REG UDP_IMR; // Interrupt Mask Register
1214    AT91_REG UDP_ISR; // Interrupt Status Register
1215    AT91_REG UDP_ICR; // Interrupt Clear Register
1216    AT91_REG Reserved1[1]; //
1217    AT91_REG UDP_RSTEP; // Reset Endpoint Register
1218    AT91_REG Reserved2[1]; //
1219    AT91_REG UDP_CSR[8]; // Endpoint Control and Status Register
1220    AT91_REG UDP_FDR[8]; // Endpoint FIFO Data Register
1221} AT91S_UDP, *AT91PS_UDP;
1222
1223// -------- UDP_FRM_NUM : (UDP Offset: 0x0) USB Frame Number Register --------
1224#define AT91C_UDP_FRM_NUM ((unsigned int) 0x7FF << 0) // (UDP) Frame Number as Defined in the Packet Field Formats
1225#define AT91C_UDP_FRM_ERR ((unsigned int) 0x1 << 16) // (UDP) Frame Error
1226#define AT91C_UDP_FRM_OK ((unsigned int) 0x1 << 17) // (UDP) Frame OK
1227// -------- UDP_GLB_STATE : (UDP Offset: 0x4) USB Global State Register --------
1228#define AT91C_UDP_FADDEN ((unsigned int) 0x1 << 0) // (UDP) Function Address Enable
1229#define AT91C_UDP_CONFG ((unsigned int) 0x1 << 1) // (UDP) Configured
1230#define AT91C_UDP_RMWUPE ((unsigned int) 0x1 << 2) // (UDP) Remote Wake Up Enable
1231#define AT91C_UDP_RSMINPR ((unsigned int) 0x1 << 3) // (UDP) A Resume Has Been Sent to the Host
1232// -------- UDP_FADDR : (UDP Offset: 0x8) USB Function Address Register --------
1233#define AT91C_UDP_FADD ((unsigned int) 0xFF << 0) // (UDP) Function Address Value
1234#define AT91C_UDP_FEN ((unsigned int) 0x1 << 8) // (UDP) Function Enable
1235// -------- UDP_IER : (UDP Offset: 0x10) USB Interrupt Enable Register --------
1236#define AT91C_UDP_EPINT0 ((unsigned int) 0x1 << 0) // (UDP) Endpoint 0 Interrupt
1237#define AT91C_UDP_EPINT1 ((unsigned int) 0x1 << 1) // (UDP) Endpoint 0 Interrupt
1238#define AT91C_UDP_EPINT2 ((unsigned int) 0x1 << 2) // (UDP) Endpoint 2 Interrupt
1239#define AT91C_UDP_EPINT3 ((unsigned int) 0x1 << 3) // (UDP) Endpoint 3 Interrupt
1240#define AT91C_UDP_EPINT4 ((unsigned int) 0x1 << 4) // (UDP) Endpoint 4 Interrupt
1241#define AT91C_UDP_EPINT5 ((unsigned int) 0x1 << 5) // (UDP) Endpoint 5 Interrupt
1242#define AT91C_UDP_EPINT6 ((unsigned int) 0x1 << 6) // (UDP) Endpoint 6 Interrupt
1243#define AT91C_UDP_EPINT7 ((unsigned int) 0x1 << 7) // (UDP) Endpoint 7 Interrupt
1244#define AT91C_UDP_RXSUSP ((unsigned int) 0x1 << 8) // (UDP) USB Suspend Interrupt
1245#define AT91C_UDP_RXRSM ((unsigned int) 0x1 << 9) // (UDP) USB Resume Interrupt
1246#define AT91C_UDP_EXTRSM ((unsigned int) 0x1 << 10) // (UDP) USB External Resume Interrupt
1247#define AT91C_UDP_SOFINT ((unsigned int) 0x1 << 11) // (UDP) USB Start Of frame Interrupt
1248#define AT91C_UDP_WAKEUP ((unsigned int) 0x1 << 13) // (UDP) USB Resume Interrupt
1249// -------- UDP_IDR : (UDP Offset: 0x14) USB Interrupt Disable Register --------
1250// -------- UDP_IMR : (UDP Offset: 0x18) USB Interrupt Mask Register --------
1251// -------- UDP_ISR : (UDP Offset: 0x1c) USB Interrupt Status Register --------
1252#define AT91C_UDP_ENDBUSRES ((unsigned int) 0x1 << 12) // (UDP) USB End Of Bus Reset Interrupt
1253// -------- UDP_ICR : (UDP Offset: 0x20) USB Interrupt Clear Register --------
1254// -------- UDP_RST_EP : (UDP Offset: 0x28) USB Reset Endpoint Register --------
1255#define AT91C_UDP_EP0 ((unsigned int) 0x1 << 0) // (UDP) Reset Endpoint 0
1256#define AT91C_UDP_EP1 ((unsigned int) 0x1 << 1) // (UDP) Reset Endpoint 1
1257#define AT91C_UDP_EP2 ((unsigned int) 0x1 << 2) // (UDP) Reset Endpoint 2
1258#define AT91C_UDP_EP3 ((unsigned int) 0x1 << 3) // (UDP) Reset Endpoint 3
1259#define AT91C_UDP_EP4 ((unsigned int) 0x1 << 4) // (UDP) Reset Endpoint 4
1260#define AT91C_UDP_EP5 ((unsigned int) 0x1 << 5) // (UDP) Reset Endpoint 5
1261#define AT91C_UDP_EP6 ((unsigned int) 0x1 << 6) // (UDP) Reset Endpoint 6
1262#define AT91C_UDP_EP7 ((unsigned int) 0x1 << 7) // (UDP) Reset Endpoint 7
1263// -------- UDP_CSR : (UDP Offset: 0x30) USB Endpoint Control and Status Register --------
1264#define AT91C_UDP_TXCOMP ((unsigned int) 0x1 << 0) // (UDP) Generates an IN packet with data previously written in the DPR
1265#define AT91C_UDP_RX_DATA_BK0 ((unsigned int) 0x1 << 1) // (UDP) Receive Data Bank 0
1266#define AT91C_UDP_RXSETUP ((unsigned int) 0x1 << 2) // (UDP) Sends STALL to the Host (Control endpoints)
1267#define AT91C_UDP_ISOERROR ((unsigned int) 0x1 << 3) // (UDP) Isochronous error (Isochronous endpoints)
1268#define AT91C_UDP_TXPKTRDY ((unsigned int) 0x1 << 4) // (UDP) Transmit Packet Ready
1269#define AT91C_UDP_FORCESTALL ((unsigned int) 0x1 << 5) // (UDP) Force Stall (used by Control, Bulk and Isochronous endpoints).
1270#define AT91C_UDP_RX_DATA_BK1 ((unsigned int) 0x1 << 6) // (UDP) Receive Data Bank 1 (only used by endpoints with ping-pong attributes).
1271#define AT91C_UDP_DIR ((unsigned int) 0x1 << 7) // (UDP) Transfer Direction
1272#define AT91C_UDP_EPTYPE ((unsigned int) 0x7 << 8) // (UDP) Endpoint type
1273#define AT91C_UDP_EPTYPE_CTRL ((unsigned int) 0x0 << 8) // (UDP) Control
1274#define AT91C_UDP_EPTYPE_ISO_OUT ((unsigned int) 0x1 << 8) // (UDP) Isochronous OUT
1275#define AT91C_UDP_EPTYPE_BULK_OUT ((unsigned int) 0x2 << 8) // (UDP) Bulk OUT
1276#define AT91C_UDP_EPTYPE_INT_OUT ((unsigned int) 0x3 << 8) // (UDP) Interrupt OUT
1277#define AT91C_UDP_EPTYPE_ISO_IN ((unsigned int) 0x5 << 8) // (UDP) Isochronous IN
1278#define AT91C_UDP_EPTYPE_BULK_IN ((unsigned int) 0x6 << 8) // (UDP) Bulk IN
1279#define AT91C_UDP_EPTYPE_INT_IN ((unsigned int) 0x7 << 8) // (UDP) Interrupt IN
1280#define AT91C_UDP_DTGLE ((unsigned int) 0x1 << 11) // (UDP) Data Toggle
1281#define AT91C_UDP_EPEDS ((unsigned int) 0x1 << 15) // (UDP) Endpoint Enable Disable
1282#define AT91C_UDP_RXBYTECNT ((unsigned int) 0x7FF << 16) // (UDP) Number Of Bytes Available in the FIFO
1283
1284// *****************************************************************************
1285// SOFTWARE API DEFINITION FOR Timer Counter Channel Interface
1286// *****************************************************************************
1287typedef struct _AT91S_TC {
1288    AT91_REG TC_CCR; // Channel Control Register
1289    AT91_REG TC_CMR; // Channel Mode Register
1290    AT91_REG Reserved0[2]; //
1291    AT91_REG TC_CV; // Counter Value
1292    AT91_REG TC_RA; // Register A
1293    AT91_REG TC_RB; // Register B
1294    AT91_REG TC_RC; // Register C
1295    AT91_REG TC_SR; // Status Register
1296    AT91_REG TC_IER; // Interrupt Enable Register
1297    AT91_REG TC_IDR; // Interrupt Disable Register
1298    AT91_REG TC_IMR; // Interrupt Mask Register
1299} AT91S_TC, *AT91PS_TC;
1300
1301// -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register --------
1302#define AT91C_TC_CLKEN ((unsigned int) 0x1 << 0) // (TC) Counter Clock Enable Command
1303#define AT91C_TC_CLKDIS ((unsigned int) 0x1 << 1) // (TC) Counter Clock Disable Command
1304#define AT91C_TC_SWTRG ((unsigned int) 0x1 << 2) // (TC) Software Trigger Command
1305// -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode --------
1306#define AT91C_TC_CPCSTOP ((unsigned int) 0x1 << 6) // (TC) Counter Clock Stopped with RC Compare
1307#define AT91C_TC_CPCDIS ((unsigned int) 0x1 << 7) // (TC) Counter Clock Disable with RC Compare
1308#define AT91C_TC_EEVTEDG ((unsigned int) 0x3 << 8) // (TC) External Event Edge Selection
1309#define AT91C_TC_EEVTEDG_NONE ((unsigned int) 0x0 << 8) // (TC) Edge: None
1310#define AT91C_TC_EEVTEDG_RISING ((unsigned int) 0x1 << 8) // (TC) Edge: rising edge
1311#define AT91C_TC_EEVTEDG_FALLING ((unsigned int) 0x2 << 8) // (TC) Edge: falling edge
1312#define AT91C_TC_EEVTEDG_BOTH ((unsigned int) 0x3 << 8) // (TC) Edge: each edge
1313#define AT91C_TC_EEVT ((unsigned int) 0x3 << 10) // (TC) External Event Selection
1314#define AT91C_TC_EEVT_NONE ((unsigned int) 0x0 << 10) // (TC) Signal selected as external event: TIOB TIOB direction: input
1315#define AT91C_TC_EEVT_RISING ((unsigned int) 0x1 << 10) // (TC) Signal selected as external event: XC0 TIOB direction: output
1316#define AT91C_TC_EEVT_FALLING ((unsigned int) 0x2 << 10) // (TC) Signal selected as external event: XC1 TIOB direction: output
1317#define AT91C_TC_EEVT_BOTH ((unsigned int) 0x3 << 10) // (TC) Signal selected as external event: XC2 TIOB direction: output
1318#define AT91C_TC_ENETRG ((unsigned int) 0x1 << 12) // (TC) External Event Trigger enable
1319#define AT91C_TC_WAVESEL ((unsigned int) 0x3 << 13) // (TC) Waveform Selection
1320#define AT91C_TC_WAVESEL_UP ((unsigned int) 0x0 << 13) // (TC) UP mode without atomatic trigger on RC Compare
1321#define AT91C_TC_WAVESEL_UPDOWN ((unsigned int) 0x1 << 13) // (TC) UPDOWN mode without automatic trigger on RC Compare
1322#define AT91C_TC_WAVESEL_UP_AUTO ((unsigned int) 0x2 << 13) // (TC) UP mode with automatic trigger on RC Compare
1323#define AT91C_TC_WAVESEL_UPDOWN_AUTO ((unsigned int) 0x3 << 13) // (TC) UPDOWN mode with automatic trigger on RC Compare
1324#define AT91C_TC_CPCTRG ((unsigned int) 0x1 << 14) // (TC) RC Compare Trigger Enable
1325#define AT91C_TC_WAVE ((unsigned int) 0x1 << 15) // (TC)
1326#define AT91C_TC_ACPA ((unsigned int) 0x3 << 16) // (TC) RA Compare Effect on TIOA
1327#define AT91C_TC_ACPA_NONE ((unsigned int) 0x0 << 16) // (TC) Effect: none
1328#define AT91C_TC_ACPA_SET ((unsigned int) 0x1 << 16) // (TC) Effect: set
1329#define AT91C_TC_ACPA_CLEAR ((unsigned int) 0x2 << 16) // (TC) Effect: clear
1330#define AT91C_TC_ACPA_TOGGLE ((unsigned int) 0x3 << 16) // (TC) Effect: toggle
1331#define AT91C_TC_ACPC ((unsigned int) 0x3 << 18) // (TC) RC Compare Effect on TIOA
1332#define AT91C_TC_ACPC_NONE ((unsigned int) 0x0 << 18) // (TC) Effect: none
1333#define AT91C_TC_ACPC_SET ((unsigned int) 0x1 << 18) // (TC) Effect: set
1334#define AT91C_TC_ACPC_CLEAR ((unsigned int) 0x2 << 18) // (TC) Effect: clear
1335#define AT91C_TC_ACPC_TOGGLE ((unsigned int) 0x3 << 18) // (TC) Effect: toggle
1336#define AT91C_TC_AEEVT ((unsigned int) 0x3 << 20) // (TC) External Event Effect on TIOA
1337#define AT91C_TC_AEEVT_NONE ((unsigned int) 0x0 << 20) // (TC) Effect: none
1338#define AT91C_TC_AEEVT_SET ((unsigned int) 0x1 << 20) // (TC) Effect: set
1339#define AT91C_TC_AEEVT_CLEAR ((unsigned int) 0x2 << 20) // (TC) Effect: clear
1340#define AT91C_TC_AEEVT_TOGGLE ((unsigned int) 0x3 << 20) // (TC) Effect: toggle
1341#define AT91C_TC_ASWTRG ((unsigned int) 0x3 << 22) // (TC) Software Trigger Effect on TIOA
1342#define AT91C_TC_ASWTRG_NONE ((unsigned int) 0x0 << 22) // (TC) Effect: none
1343#define AT91C_TC_ASWTRG_SET ((unsigned int) 0x1 << 22) // (TC) Effect: set
1344#define AT91C_TC_ASWTRG_CLEAR ((unsigned int) 0x2 << 22) // (TC) Effect: clear
1345#define AT91C_TC_ASWTRG_TOGGLE ((unsigned int) 0x3 << 22) // (TC) Effect: toggle
1346#define AT91C_TC_BCPB ((unsigned int) 0x3 << 24) // (TC) RB Compare Effect on TIOB
1347#define AT91C_TC_BCPB_NONE ((unsigned int) 0x0 << 24) // (TC) Effect: none
1348#define AT91C_TC_BCPB_SET ((unsigned int) 0x1 << 24) // (TC) Effect: set
1349#define AT91C_TC_BCPB_CLEAR ((unsigned int) 0x2 << 24) // (TC) Effect: clear
1350#define AT91C_TC_BCPB_TOGGLE ((unsigned int) 0x3 << 24) // (TC) Effect: toggle
1351#define AT91C_TC_BCPC ((unsigned int) 0x3 << 26) // (TC) RC Compare Effect on TIOB
1352#define AT91C_TC_BCPC_NONE ((unsigned int) 0x0 << 26) // (TC) Effect: none
1353#define AT91C_TC_BCPC_SET ((unsigned int) 0x1 << 26) // (TC) Effect: set
1354#define AT91C_TC_BCPC_CLEAR ((unsigned int) 0x2 << 26) // (TC) Effect: clear
1355#define AT91C_TC_BCPC_TOGGLE ((unsigned int) 0x3 << 26) // (TC) Effect: toggle
1356#define AT91C_TC_BEEVT ((unsigned int) 0x3 << 28) // (TC) External Event Effect on TIOB
1357#define AT91C_TC_BEEVT_NONE ((unsigned int) 0x0 << 28) // (TC) Effect: none
1358#define AT91C_TC_BEEVT_SET ((unsigned int) 0x1 << 28) // (TC) Effect: set
1359#define AT91C_TC_BEEVT_CLEAR ((unsigned int) 0x2 << 28) // (TC) Effect: clear
1360#define AT91C_TC_BEEVT_TOGGLE ((unsigned int) 0x3 << 28) // (TC) Effect: toggle
1361#define AT91C_TC_BSWTRG ((unsigned int) 0x3 << 30) // (TC) Software Trigger Effect on TIOB
1362#define AT91C_TC_BSWTRG_NONE ((unsigned int) 0x0 << 30) // (TC) Effect: none
1363#define AT91C_TC_BSWTRG_SET ((unsigned int) 0x1 << 30) // (TC) Effect: set
1364#define AT91C_TC_BSWTRG_CLEAR ((unsigned int) 0x2 << 30) // (TC) Effect: clear
1365#define AT91C_TC_BSWTRG_TOGGLE ((unsigned int) 0x3 << 30) // (TC) Effect: toggle
1366// -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register --------
1367#define AT91C_TC_COVFS ((unsigned int) 0x1 << 0) // (TC) Counter Overflow
1368#define AT91C_TC_LOVRS ((unsigned int) 0x1 << 1) // (TC) Load Overrun
1369#define AT91C_TC_CPAS ((unsigned int) 0x1 << 2) // (TC) RA Compare
1370#define AT91C_TC_CPBS ((unsigned int) 0x1 << 3) // (TC) RB Compare
1371#define AT91C_TC_CPCS ((unsigned int) 0x1 << 4) // (TC) RC Compare
1372#define AT91C_TC_LDRAS ((unsigned int) 0x1 << 5) // (TC) RA Loading
1373#define AT91C_TC_LDRBS ((unsigned int) 0x1 << 6) // (TC) RB Loading
1374#define AT91C_TC_ETRCS ((unsigned int) 0x1 << 7) // (TC) External Trigger
1375#define AT91C_TC_ETRGS ((unsigned int) 0x1 << 16) // (TC) Clock Enabling
1376#define AT91C_TC_MTIOA ((unsigned int) 0x1 << 17) // (TC) TIOA Mirror
1377#define AT91C_TC_MTIOB ((unsigned int) 0x1 << 18) // (TC) TIOA Mirror
1378// -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register --------
1379// -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register --------
1380// -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register --------
1381
1382// *****************************************************************************
1383// SOFTWARE API DEFINITION FOR Timer Counter Interface
1384// *****************************************************************************
1385typedef struct _AT91S_TCB {
1386    AT91S_TC TCB_TC0; // TC Channel 0
1387    AT91_REG Reserved0[4]; //
1388    AT91S_TC TCB_TC1; // TC Channel 1
1389    AT91_REG Reserved1[4]; //
1390    AT91S_TC TCB_TC2; // TC Channel 2
1391    AT91_REG Reserved2[4]; //
1392    AT91_REG TCB_BCR; // TC Block Control Register
1393    AT91_REG TCB_BMR; // TC Block Mode Register
1394} AT91S_TCB, *AT91PS_TCB;
1395
1396// -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register --------
1397#define AT91C_TCB_SYNC ((unsigned int) 0x1 << 0) // (TCB) Synchro Command
1398// -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register --------
1399#define AT91C_TCB_TC0XC0S ((unsigned int) 0x1 << 0) // (TCB) External Clock Signal 0 Selection
1400#define AT91C_TCB_TC0XC0S_TCLK0 ((unsigned int) 0x0) // (TCB) TCLK0 connected to XC0
1401#define AT91C_TCB_TC0XC0S_NONE ((unsigned int) 0x1) // (TCB) None signal connected to XC0
1402#define AT91C_TCB_TC0XC0S_TIOA1 ((unsigned int) 0x2) // (TCB) TIOA1 connected to XC0
1403#define AT91C_TCB_TC0XC0S_TIOA2 ((unsigned int) 0x3) // (TCB) TIOA2 connected to XC0
1404#define AT91C_TCB_TC1XC1S ((unsigned int) 0x1 << 2) // (TCB) External Clock Signal 1 Selection
1405#define AT91C_TCB_TC1XC1S_TCLK1 ((unsigned int) 0x0 << 2) // (TCB) TCLK1 connected to XC1
1406#define AT91C_TCB_TC1XC1S_NONE ((unsigned int) 0x1 << 2) // (TCB) None signal connected to XC1
1407#define AT91C_TCB_TC1XC1S_TIOA0 ((unsigned int) 0x2 << 2) // (TCB) TIOA0 connected to XC1
1408#define AT91C_TCB_TC1XC1S_TIOA2 ((unsigned int) 0x3 << 2) // (TCB) TIOA2 connected to XC1
1409#define AT91C_TCB_TC2XC2S ((unsigned int) 0x1 << 4) // (TCB) External Clock Signal 2 Selection
1410#define AT91C_TCB_TC2XC2S_TCLK2 ((unsigned int) 0x0 << 4) // (TCB) TCLK2 connected to XC2
1411#define AT91C_TCB_TC2XC2S_NONE ((unsigned int) 0x1 << 4) // (TCB) None signal connected to XC2
1412#define AT91C_TCB_TC2XC2S_TIOA0 ((unsigned int) 0x2 << 4) // (TCB) TIOA0 connected to XC2
1413#define AT91C_TCB_TC2XC2S_TIOA2 ((unsigned int) 0x3 << 4) // (TCB) TIOA2 connected to XC2
1414
1415// *****************************************************************************
1416// SOFTWARE API DEFINITION FOR USB Host Interface
1417// *****************************************************************************
1418typedef struct _AT91S_UHP {
1419    AT91_REG UHP_HcRevision; // Revision
1420    AT91_REG UHP_HcControl; // Operating modes for the Host Controller
1421    AT91_REG UHP_HcCommandStatus; // Command & status Register
1422    AT91_REG UHP_HcInterruptStatus; // Interrupt Status Register
1423    AT91_REG UHP_HcInterruptEnable; // Interrupt Enable Register
1424    AT91_REG UHP_HcInterruptDisable; // Interrupt Disable Register
1425    AT91_REG UHP_HcHCCA; // Pointer to the Host Controller Communication Area
1426    AT91_REG UHP_HcPeriodCurrentED; // Current Isochronous or Interrupt Endpoint Descriptor
1427    AT91_REG UHP_HcControlHeadED; // First Endpoint Descriptor of the Control list
1428    AT91_REG UHP_HcControlCurrentED; // Endpoint Control and Status Register
1429    AT91_REG UHP_HcBulkHeadED; // First endpoint register of the Bulk list
1430    AT91_REG UHP_HcBulkCurrentED; // Current endpoint of the Bulk list
1431    AT91_REG UHP_HcBulkDoneHead; // Last completed transfer descriptor
1432    AT91_REG UHP_HcFmInterval; // Bit time between 2 consecutive SOFs
1433    AT91_REG UHP_HcFmRemaining; // Bit time remaining in the current Frame
1434    AT91_REG UHP_HcFmNumber; // Frame number
1435    AT91_REG UHP_HcPeriodicStart; // Periodic Start
1436    AT91_REG UHP_HcLSThreshold; // LS Threshold
1437    AT91_REG UHP_HcRhDescriptorA; // Root Hub characteristics A
1438    AT91_REG UHP_HcRhDescriptorB; // Root Hub characteristics B
1439    AT91_REG UHP_HcRhStatus; // Root Hub Status register
1440    AT91_REG UHP_HcRhPortStatus[2]; // Root Hub Port Status Register
1441} AT91S_UHP, *AT91PS_UHP;
1442
1443
1444// *****************************************************************************
1445// SOFTWARE API DEFINITION FOR Ethernet MAC
1446// *****************************************************************************
1447typedef struct _AT91S_EMAC {
1448    AT91_REG EMAC_CTL; // Network Control Register
1449    AT91_REG EMAC_CFG; // Network Configuration Register
1450    AT91_REG EMAC_SR; // Network Status Register
1451    AT91_REG EMAC_TAR; // Transmit Address Register
1452    AT91_REG EMAC_TCR; // Transmit Control Register
1453    AT91_REG EMAC_TSR; // Transmit Status Register
1454    AT91_REG EMAC_RBQP; // Receive Buffer Queue Pointer
1455    AT91_REG Reserved0[1]; //
1456    AT91_REG EMAC_RSR; // Receive Status Register
1457    AT91_REG EMAC_ISR; // Interrupt Status Register
1458    AT91_REG EMAC_IER; // Interrupt Enable Register
1459    AT91_REG EMAC_IDR; // Interrupt Disable Register
1460    AT91_REG EMAC_IMR; // Interrupt Mask Register
1461    AT91_REG EMAC_MAN; // PHY Maintenance Register
1462    AT91_REG Reserved1[2]; //
1463    AT91_REG EMAC_FRA; // Frames Transmitted OK Register
1464    AT91_REG EMAC_SCOL; // Single Collision Frame Register
1465    AT91_REG EMAC_MCOL; // Multiple Collision Frame Register
1466    AT91_REG EMAC_OK; // Frames Received OK Register
1467    AT91_REG EMAC_SEQE; // Frame Check Sequence Error Register
1468    AT91_REG EMAC_ALE; // Alignment Error Register
1469    AT91_REG EMAC_DTE; // Deferred Transmission Frame Register
1470    AT91_REG EMAC_LCOL; // Late Collision Register
1471    AT91_REG EMAC_ECOL; // Excessive Collision Register
1472    AT91_REG EMAC_CSE; // Carrier Sense Error Register
1473    AT91_REG EMAC_TUE; // Transmit Underrun Error Register
1474    AT91_REG EMAC_CDE; // Code Error Register
1475    AT91_REG EMAC_ELR; // Excessive Length Error Register
1476    AT91_REG EMAC_RJB; // Receive Jabber Register
1477    AT91_REG EMAC_USF; // Undersize Frame Register
1478    AT91_REG EMAC_SQEE; // SQE Test Error Register
1479    AT91_REG EMAC_DRFC; // Discarded RX Frame Register
1480    AT91_REG Reserved2[3]; //
1481    AT91_REG EMAC_HSH; // Hash Address High[63:32]
1482    AT91_REG EMAC_HSL; // Hash Address Low[31:0]
1483    AT91_REG EMAC_SA1L; // Specific Address 1 Low, First 4 bytes
1484    AT91_REG EMAC_SA1H; // Specific Address 1 High, Last 2 bytes
1485    AT91_REG EMAC_SA2L; // Specific Address 2 Low, First 4 bytes
1486    AT91_REG EMAC_SA2H; // Specific Address 2 High, Last 2 bytes
1487    AT91_REG EMAC_SA3L; // Specific Address 3 Low, First 4 bytes
1488    AT91_REG EMAC_SA3H; // Specific Address 3 High, Last 2 bytes
1489    AT91_REG EMAC_SA4L; // Specific Address 4 Low, First 4 bytes
1490    AT91_REG EMAC_SA4H; // Specific Address 4 High, Last 2 bytesr
1491} AT91S_EMAC, *AT91PS_EMAC;
1492
1493// -------- EMAC_CTL : (EMAC Offset: 0x0) --------
1494#define AT91C_EMAC_LB ((unsigned int) 0x1 << 0) // (EMAC) Loopback. Optional. When set, loopback signal is at high level.
1495#define AT91C_EMAC_LBL ((unsigned int) 0x1 << 1) // (EMAC) Loopback local.
1496#define AT91C_EMAC_RE ((unsigned int) 0x1 << 2) // (EMAC) Receive enable.
1497#define AT91C_EMAC_TE ((unsigned int) 0x1 << 3) // (EMAC) Transmit enable.
1498#define AT91C_EMAC_MPE ((unsigned int) 0x1 << 4) // (EMAC) Management port enable.
1499#define AT91C_EMAC_CSR ((unsigned int) 0x1 << 5) // (EMAC) Clear statistics registers.
1500#define AT91C_EMAC_ISR ((unsigned int) 0x1 << 6) // (EMAC) Increment statistics registers.
1501#define AT91C_EMAC_WES ((unsigned int) 0x1 << 7) // (EMAC) Write enable for statistics registers.
1502#define AT91C_EMAC_BP ((unsigned int) 0x1 << 8) // (EMAC) Back pressure.
1503// -------- EMAC_CFG : (EMAC Offset: 0x4) Network Configuration Register --------
1504#define AT91C_EMAC_SPD ((unsigned int) 0x1 << 0) // (EMAC) Speed.
1505#define AT91C_EMAC_FD ((unsigned int) 0x1 << 1) // (EMAC) Full duplex.
1506#define AT91C_EMAC_BR ((unsigned int) 0x1 << 2) // (EMAC) Bit rate.
1507#define AT91C_EMAC_CAF ((unsigned int) 0x1 << 4) // (EMAC) Copy all frames.
1508#define AT91C_EMAC_NBC ((unsigned int) 0x1 << 5) // (EMAC) No broadcast.
1509#define AT91C_EMAC_MTI ((unsigned int) 0x1 << 6) // (EMAC) Multicast hash enable
1510#define AT91C_EMAC_UNI ((unsigned int) 0x1 << 7) // (EMAC) Unicast hash enable.
1511#define AT91C_EMAC_BIG ((unsigned int) 0x1 << 8) // (EMAC) Receive 1522 bytes.
1512#define AT91C_EMAC_EAE ((unsigned int) 0x1 << 9) // (EMAC) External address match enable.
1513#define AT91C_EMAC_CLK ((unsigned int) 0x3 << 10) // (EMAC)
1514#define AT91C_EMAC_CLK_HCLK_8 ((unsigned int) 0x0 << 10) // (EMAC) HCLK divided by 8
1515#define AT91C_EMAC_CLK_HCLK_16 ((unsigned int) 0x1 << 10) // (EMAC) HCLK divided by 16
1516#define AT91C_EMAC_CLK_HCLK_32 ((unsigned int) 0x2 << 10) // (EMAC) HCLK divided by 32
1517#define AT91C_EMAC_CLK_HCLK_64 ((unsigned int) 0x3 << 10) // (EMAC) HCLK divided by 64
1518#define AT91C_EMAC_RTY ((unsigned int) 0x1 << 12) // (EMAC)
1519#define AT91C_EMAC_RMII ((unsigned int) 0x1 << 13) // (EMAC)
1520// -------- EMAC_SR : (EMAC Offset: 0x8) Network Status Register --------
1521#define AT91C_EMAC_MDIO ((unsigned int) 0x1 << 1) // (EMAC)
1522#define AT91C_EMAC_IDLE ((unsigned int) 0x1 << 2) // (EMAC)
1523// -------- EMAC_TCR : (EMAC Offset: 0x10) Transmit Control Register --------
1524#define AT91C_EMAC_LEN ((unsigned int) 0x7FF << 0) // (EMAC)
1525#define AT91C_EMAC_NCRC ((unsigned int) 0x1 << 15) // (EMAC)
1526// -------- EMAC_TSR : (EMAC Offset: 0x14) Transmit Control Register --------
1527#define AT91C_EMAC_OVR ((unsigned int) 0x1 << 0) // (EMAC)
1528#define AT91C_EMAC_COL ((unsigned int) 0x1 << 1) // (EMAC)
1529#define AT91C_EMAC_RLE ((unsigned int) 0x1 << 2) // (EMAC)
1530#define AT91C_EMAC_TXIDLE ((unsigned int) 0x1 << 3) // (EMAC)
1531#define AT91C_EMAC_BNQ ((unsigned int) 0x1 << 4) // (EMAC)
1532#define AT91C_EMAC_COMP ((unsigned int) 0x1 << 5) // (EMAC)
1533#define AT91C_EMAC_UND ((unsigned int) 0x1 << 6) // (EMAC)
1534// -------- EMAC_RSR : (EMAC Offset: 0x20) Receive Status Register --------
1535#define AT91C_EMAC_BNA ((unsigned int) 0x1 << 0) // (EMAC)
1536#define AT91C_EMAC_REC ((unsigned int) 0x1 << 1) // (EMAC)
1537// -------- EMAC_ISR : (EMAC Offset: 0x24) Interrupt Status Register --------
1538#define AT91C_EMAC_DONE ((unsigned int) 0x1 << 0) // (EMAC)
1539#define AT91C_EMAC_RCOM ((unsigned int) 0x1 << 1) // (EMAC)
1540#define AT91C_EMAC_RBNA ((unsigned int) 0x1 << 2) // (EMAC)
1541#define AT91C_EMAC_TOVR ((unsigned int) 0x1 << 3) // (EMAC)
1542#define AT91C_EMAC_TUND ((unsigned int) 0x1 << 4) // (EMAC)
1543#define AT91C_EMAC_RTRY ((unsigned int) 0x1 << 5) // (EMAC)
1544#define AT91C_EMAC_TBRE ((unsigned int) 0x1 << 6) // (EMAC)
1545#define AT91C_EMAC_TCOM ((unsigned int) 0x1 << 7) // (EMAC)
1546#define AT91C_EMAC_TIDLE ((unsigned int) 0x1 << 8) // (EMAC)
1547#define AT91C_EMAC_LINK ((unsigned int) 0x1 << 9) // (EMAC)
1548#define AT91C_EMAC_ROVR ((unsigned int) 0x1 << 10) // (EMAC)
1549#define AT91C_EMAC_HRESP ((unsigned int) 0x1 << 11) // (EMAC)
1550// -------- EMAC_IER : (EMAC Offset: 0x28) Interrupt Enable Register --------
1551// -------- EMAC_IDR : (EMAC Offset: 0x2c) Interrupt Disable Register --------
1552// -------- EMAC_IMR : (EMAC Offset: 0x30) Interrupt Mask Register --------
1553// -------- EMAC_MAN : (EMAC Offset: 0x34) PHY Maintenance Register --------
1554#define AT91C_EMAC_DATA ((unsigned int) 0xFFFF << 0) // (EMAC)
1555#define AT91C_EMAC_CODE ((unsigned int) 0x3 << 16) // (EMAC)
1556#define AT91C_EMAC_REGA ((unsigned int) 0x1F << 18) // (EMAC)
1557#define AT91C_EMAC_PHYA ((unsigned int) 0x1F << 23) // (EMAC)
1558#define AT91C_EMAC_RW ((unsigned int) 0x3 << 28) // (EMAC)
1559#define AT91C_EMAC_HIGH ((unsigned int) 0x1 << 30) // (EMAC)
1560#define AT91C_EMAC_LOW ((unsigned int) 0x1 << 31) // (EMAC)
1561
1562// *****************************************************************************
1563// SOFTWARE API DEFINITION FOR External Bus Interface
1564// *****************************************************************************
1565typedef struct _AT91S_EBI {
1566    AT91_REG EBI_CSA; // Chip Select Assignment Register
1567    AT91_REG EBI_CFGR; // Configuration Register
1568} AT91S_EBI, *AT91PS_EBI;
1569
1570// -------- EBI_CSA : (EBI Offset: 0x0) Chip Select Assignment Register --------
1571#define AT91C_EBI_CS0A ((unsigned int) 0x1 << 0) // (EBI) Chip Select 0 Assignment
1572#define AT91C_EBI_CS0A_SMC ((unsigned int) 0x0) // (EBI) Chip Select 0 is assigned to the Static Memory Controller.
1573#define AT91C_EBI_CS0A_BFC ((unsigned int) 0x1) // (EBI) Chip Select 0 is assigned to the Burst Flash Controller.
1574#define AT91C_EBI_CS1A ((unsigned int) 0x1 << 1) // (EBI) Chip Select 1 Assignment
1575#define AT91C_EBI_CS1A_SMC ((unsigned int) 0x0 << 1) // (EBI) Chip Select 1 is assigned to the Static Memory Controller.
1576#define AT91C_EBI_CS1A_SDRAMC ((unsigned int) 0x1 << 1) // (EBI) Chip Select 1 is assigned to the SDRAM Controller.
1577#define AT91C_EBI_CS3A ((unsigned int) 0x1 << 3) // (EBI) Chip Select 3 Assignment
1578#define AT91C_EBI_CS3A_SMC ((unsigned int) 0x0 << 3) // (EBI) Chip Select 3 is only assigned to the Static Memory Controller and NCS3 behaves as defined by the SMC2.
1579#define AT91C_EBI_CS3A_SMC_SmartMedia ((unsigned int) 0x1 << 3) // (EBI) Chip Select 3 is assigned to the Static Memory Controller and the SmartMedia Logic is activated.
1580#define AT91C_EBI_CS4A ((unsigned int) 0x1 << 4) // (EBI) Chip Select 4 Assignment
1581#define AT91C_EBI_CS4A_SMC ((unsigned int) 0x0 << 4) // (EBI) Chip Select 4 is assigned to the Static Memory Controller and NCS4,NCS5 and NCS6 behave as defined by the SMC2.
1582#define AT91C_EBI_CS4A_SMC_CompactFlash ((unsigned int) 0x1 << 4) // (EBI) Chip Select 4 is assigned to the Static Memory Controller and the CompactFlash Logic is activated.
1583// -------- EBI_CFGR : (EBI Offset: 0x4) Configuration Register --------
1584#define AT91C_EBI_DBPUC ((unsigned int) 0x1 << 0) // (EBI) Data Bus Pull-Up Configuration
1585#define AT91C_EBI_EBSEN ((unsigned int) 0x1 << 1) // (EBI) Bus Sharing Enable
1586
1587// *****************************************************************************
1588// SOFTWARE API DEFINITION FOR Static Memory Controller 2 Interface
1589// *****************************************************************************
1590typedef struct _AT91S_SMC2 {
1591    AT91_REG SMC2_CSR[8]; // SMC2 Chip Select Register
1592} AT91S_SMC2, *AT91PS_SMC2;
1593
1594// -------- SMC2_CSR : (SMC2 Offset: 0x0) SMC2 Chip Select Register --------
1595#define AT91C_SMC2_NWS ((unsigned int) 0x7F << 0) // (SMC2) Number of Wait States
1596#define AT91C_SMC2_WSEN ((unsigned int) 0x1 << 7) // (SMC2) Wait State Enable
1597#define AT91C_SMC2_TDF ((unsigned int) 0xF << 8) // (SMC2) Data Float Time
1598#define AT91C_SMC2_BAT ((unsigned int) 0x1 << 12) // (SMC2) Byte Access Type
1599#define AT91C_SMC2_DBW ((unsigned int) 0x1 << 13) // (SMC2) Data Bus Width
1600#define AT91C_SMC2_DBW_16 ((unsigned int) 0x1 << 13) // (SMC2) 16-bit.
1601#define AT91C_SMC2_DBW_8 ((unsigned int) 0x2 << 13) // (SMC2) 8-bit.
1602#define AT91C_SMC2_DRP ((unsigned int) 0x1 << 15) // (SMC2) Data Read Protocol
1603#define AT91C_SMC2_ACSS ((unsigned int) 0x3 << 16) // (SMC2) Address to Chip Select Setup
1604#define AT91C_SMC2_ACSS_STANDARD ((unsigned int) 0x0 << 16) // (SMC2) Standard, asserted at the beginning of the access and deasserted at the end.
1605#define AT91C_SMC2_ACSS_1_CYCLE ((unsigned int) 0x1 << 16) // (SMC2) One cycle less at the beginning and the end of the access.
1606#define AT91C_SMC2_ACSS_2_CYCLES ((unsigned int) 0x2 << 16) // (SMC2) Two cycles less at the beginning and the end of the access.
1607#define AT91C_SMC2_ACSS_3_CYCLES ((unsigned int) 0x3 << 16) // (SMC2) Three cycles less at the beginning and the end of the access.
1608#define AT91C_SMC2_RWSETUP ((unsigned int) 0x7 << 24) // (SMC2) Read and Write Signal Setup Time
1609#define AT91C_SMC2_RWHOLD ((unsigned int) 0x7 << 29) // (SMC2) Read and Write Signal Hold Time
1610
1611// *****************************************************************************
1612// SOFTWARE API DEFINITION FOR SDRAM Controller Interface
1613// *****************************************************************************
1614typedef struct _AT91S_SDRC {
1615    AT91_REG SDRC_MR; // SDRAM Controller Mode Register
1616    AT91_REG SDRC_TR; // SDRAM Controller Refresh Timer Register
1617    AT91_REG SDRC_CR; // SDRAM Controller Configuration Register
1618    AT91_REG SDRC_SRR; // SDRAM Controller Self Refresh Register
1619    AT91_REG SDRC_LPR; // SDRAM Controller Low Power Register
1620    AT91_REG SDRC_IER; // SDRAM Controller Interrupt Enable Register
1621    AT91_REG SDRC_IDR; // SDRAM Controller Interrupt Disable Register
1622    AT91_REG SDRC_IMR; // SDRAM Controller Interrupt Mask Register
1623    AT91_REG SDRC_ISR; // SDRAM Controller Interrupt Mask Register
1624} AT91S_SDRC, *AT91PS_SDRC;
1625
1626// -------- SDRC_MR : (SDRC Offset: 0x0) SDRAM Controller Mode Register --------
1627#define AT91C_SDRC_MODE ((unsigned int) 0xF << 0) // (SDRC) Mode
1628#define AT91C_SDRC_MODE_NORMAL_CMD ((unsigned int) 0x0) // (SDRC) Normal Mode
1629#define AT91C_SDRC_MODE_NOP_CMD ((unsigned int) 0x1) // (SDRC) NOP Command
1630#define AT91C_SDRC_MODE_PRCGALL_CMD ((unsigned int) 0x2) // (SDRC) All Banks Precharge Command
1631#define AT91C_SDRC_MODE_LMR_CMD ((unsigned int) 0x3) // (SDRC) Load Mode Register Command
1632#define AT91C_SDRC_MODE_RFSH_CMD ((unsigned int) 0x4) // (SDRC) Refresh Command
1633#define AT91C_SDRC_DBW ((unsigned int) 0x1 << 4) // (SDRC) Data Bus Width
1634#define AT91C_SDRC_DBW_32_BITS ((unsigned int) 0x0 << 4) // (SDRC) 32 Bits datas bus
1635#define AT91C_SDRC_DBW_16_BITS ((unsigned int) 0x1 << 4) // (SDRC) 16 Bits datas bus
1636// -------- SDRC_TR : (SDRC Offset: 0x4) SDRC Refresh Timer Register --------
1637#define AT91C_SDRC_COUNT ((unsigned int) 0xFFF << 0) // (SDRC) Refresh Counter
1638// -------- SDRC_CR : (SDRC Offset: 0x8) SDRAM Configuration Register --------
1639#define AT91C_SDRC_NC ((unsigned int) 0x3 << 0) // (SDRC) Number of Column Bits
1640#define AT91C_SDRC_NC_8 ((unsigned int) 0x0) // (SDRC) 8 Bits
1641#define AT91C_SDRC_NC_9 ((unsigned int) 0x1) // (SDRC) 9 Bits
1642#define AT91C_SDRC_NC_10 ((unsigned int) 0x2) // (SDRC) 10 Bits
1643#define AT91C_SDRC_NC_11 ((unsigned int) 0x3) // (SDRC) 11 Bits
1644#define AT91C_SDRC_NR ((unsigned int) 0x3 << 2) // (SDRC) Number of Row Bits
1645#define AT91C_SDRC_NR_11 ((unsigned int) 0x0 << 2) // (SDRC) 11 Bits
1646#define AT91C_SDRC_NR_12 ((unsigned int) 0x1 << 2) // (SDRC) 12 Bits
1647#define AT91C_SDRC_NR_13 ((unsigned int) 0x2 << 2) // (SDRC) 13 Bits
1648#define AT91C_SDRC_NB ((unsigned int) 0x1 << 4) // (SDRC) Number of Banks
1649#define AT91C_SDRC_NB_2_BANKS ((unsigned int) 0x0 << 4) // (SDRC) 2 banks
1650#define AT91C_SDRC_NB_4_BANKS ((unsigned int) 0x1 << 4) // (SDRC) 4 banks
1651#define AT91C_SDRC_CAS ((unsigned int) 0x3 << 5) // (SDRC) CAS Latency
1652#define AT91C_SDRC_CAS_2 ((unsigned int) 0x2 << 5) // (SDRC) 2 cycles
1653#define AT91C_SDRC_TWR ((unsigned int) 0xF << 7) // (SDRC) Number of Write Recovery Time Cycles
1654#define AT91C_SDRC_TRC ((unsigned int) 0xF << 11) // (SDRC) Number of RAS Cycle Time Cycles
1655#define AT91C_SDRC_TRP ((unsigned int) 0xF << 15) // (SDRC) Number of RAS Precharge Time Cycles
1656#define AT91C_SDRC_TRCD ((unsigned int) 0xF << 19) // (SDRC) Number of RAS to CAS Delay Cycles
1657#define AT91C_SDRC_TRAS ((unsigned int) 0xF << 23) // (SDRC) Number of RAS Active Time Cycles
1658#define AT91C_SDRC_TXSR ((unsigned int) 0xF << 27) // (SDRC) Number of Command Recovery Time Cycles
1659// -------- SDRC_SRR : (SDRC Offset: 0xc) SDRAM Controller Self-refresh Register --------
1660#define AT91C_SDRC_SRCB ((unsigned int) 0x1 << 0) // (SDRC) Self-refresh Command Bit
1661// -------- SDRC_LPR : (SDRC Offset: 0x10) SDRAM Controller Low-power Register --------
1662#define AT91C_SDRC_LPCB ((unsigned int) 0x1 << 0) // (SDRC) Low-power Command Bit
1663// -------- SDRC_IER : (SDRC Offset: 0x14) SDRAM Controller Interrupt Enable Register --------
1664#define AT91C_SDRC_RES ((unsigned int) 0x1 << 0) // (SDRC) Refresh Error Status
1665// -------- SDRC_IDR : (SDRC Offset: 0x18) SDRAM Controller Interrupt Disable Register --------
1666// -------- SDRC_IMR : (SDRC Offset: 0x1c) SDRAM Controller Interrupt Mask Register --------
1667// -------- SDRC_ISR : (SDRC Offset: 0x20) SDRAM Controller Interrupt Status Register --------
1668
1669// *****************************************************************************
1670// SOFTWARE API DEFINITION FOR Burst Flash Controller Interface
1671// *****************************************************************************
1672typedef struct _AT91S_BFC {
1673    AT91_REG BFC_MR; // BFC Mode Register
1674} AT91S_BFC, *AT91PS_BFC;
1675
1676// -------- BFC_MR : (BFC Offset: 0x0) BFC Mode Register --------
1677#define AT91C_BFC_BFCOM ((unsigned int) 0x3 << 0) // (BFC) Burst Flash Controller Operating Mode
1678#define AT91C_BFC_BFCOM_DISABLED ((unsigned int) 0x0) // (BFC) NPCS0 is driven by the SMC or remains high.
1679#define AT91C_BFC_BFCOM_ASYNC ((unsigned int) 0x1) // (BFC) Asynchronous
1680#define AT91C_BFC_BFCOM_BURST_READ ((unsigned int) 0x2) // (BFC) Burst Read
1681#define AT91C_BFC_BFCC ((unsigned int) 0x3 << 2) // (BFC) Burst Flash Controller Operating Mode
1682#define AT91C_BFC_BFCC_MCK ((unsigned int) 0x1 << 2) // (BFC) Master Clock.
1683#define AT91C_BFC_BFCC_MCK_DIV_2 ((unsigned int) 0x2 << 2) // (BFC) Master Clock divided by 2.
1684#define AT91C_BFC_BFCC_MCK_DIV_4 ((unsigned int) 0x3 << 2) // (BFC) Master Clock divided by 4.
1685#define AT91C_BFC_AVL ((unsigned int) 0xF << 4) // (BFC) Address Valid Latency
1686#define AT91C_BFC_PAGES ((unsigned int) 0x7 << 8) // (BFC) Page Size
1687#define AT91C_BFC_PAGES_NO_PAGE ((unsigned int) 0x0 << 8) // (BFC) No page handling.
1688#define AT91C_BFC_PAGES_16 ((unsigned int) 0x1 << 8) // (BFC) 16 bytes page size.
1689#define AT91C_BFC_PAGES_32 ((unsigned int) 0x2 << 8) // (BFC) 32 bytes page size.
1690#define AT91C_BFC_PAGES_64 ((unsigned int) 0x3 << 8) // (BFC) 64 bytes page size.
1691#define AT91C_BFC_PAGES_128 ((unsigned int) 0x4 << 8) // (BFC) 128 bytes page size.
1692#define AT91C_BFC_PAGES_256 ((unsigned int) 0x5 << 8) // (BFC) 256 bytes page size.
1693#define AT91C_BFC_PAGES_512 ((unsigned int) 0x6 << 8) // (BFC) 512 bytes page size.
1694#define AT91C_BFC_PAGES_1024 ((unsigned int) 0x7 << 8) // (BFC) 1024 bytes page size.
1695#define AT91C_BFC_OEL ((unsigned int) 0x3 << 12) // (BFC) Output Enable Latency
1696#define AT91C_BFC_BAAEN ((unsigned int) 0x1 << 16) // (BFC) Burst Address Advance Enable
1697#define AT91C_BFC_BFOEH ((unsigned int) 0x1 << 17) // (BFC) Burst Flash Output Enable Handling
1698#define AT91C_BFC_MUXEN ((unsigned int) 0x1 << 18) // (BFC) Multiplexed Bus Enable
1699#define AT91C_BFC_RDYEN ((unsigned int) 0x1 << 19) // (BFC) Ready Enable Mode
1700
1701// *****************************************************************************
1702// REGISTER ADDRESS DEFINITION FOR AT91RM9200
1703// *****************************************************************************
1704// ========== Register definition for SYS peripheral ==========
1705// ========== Register definition for MC peripheral ==========
1706#define AT91C_MC_PUER ((AT91_REG *) 0xFFFFFF54) // (MC) MC Protection Unit Enable Register
1707#define AT91C_MC_ASR ((AT91_REG *) 0xFFFFFF04) // (MC) MC Abort Status Register
1708#define AT91C_MC_PUP ((AT91_REG *) 0xFFFFFF50) // (MC) MC Protection Unit Peripherals
1709#define AT91C_MC_PUIA ((AT91_REG *) 0xFFFFFF10) // (MC) MC Protection Unit Area
1710#define AT91C_MC_AASR ((AT91_REG *) 0xFFFFFF08) // (MC) MC Abort Address Status Register
1711#define AT91C_MC_RCR ((AT91_REG *) 0xFFFFFF00) // (MC) MC Remap Control Register
1712// ========== Register definition for RTC peripheral ==========
1713#define AT91C_RTC_IMR ((AT91_REG *) 0xFFFFFE28) // (RTC) Interrupt Mask Register
1714#define AT91C_RTC_IER ((AT91_REG *) 0xFFFFFE20) // (RTC) Interrupt Enable Register
1715#define AT91C_RTC_SR ((AT91_REG *) 0xFFFFFE18) // (RTC) Status Register
1716#define AT91C_RTC_TIMALR ((AT91_REG *) 0xFFFFFE10) // (RTC) Time Alarm Register
1717#define AT91C_RTC_TIMR ((AT91_REG *) 0xFFFFFE08) // (RTC) Time Register
1718#define AT91C_RTC_CR ((AT91_REG *) 0xFFFFFE00) // (RTC) Control Register
1719#define AT91C_RTC_VER ((AT91_REG *) 0xFFFFFE2C) // (RTC) Valid Entry Register
1720#define AT91C_RTC_IDR ((AT91_REG *) 0xFFFFFE24) // (RTC) Interrupt Disable Register
1721#define AT91C_RTC_SCCR ((AT91_REG *) 0xFFFFFE1C) // (RTC) Status Clear Command Register
1722#define AT91C_RTC_CALALR ((AT91_REG *) 0xFFFFFE14) // (RTC) Calendar Alarm Register
1723#define AT91C_RTC_CALR ((AT91_REG *) 0xFFFFFE0C) // (RTC) Calendar Register
1724#define AT91C_RTC_MR ((AT91_REG *) 0xFFFFFE04) // (RTC) Mode Register
1725// ========== Register definition for ST peripheral ==========
1726#define AT91C_ST_CRTR ((AT91_REG *) 0xFFFFFD24) // (ST) Current Real-time Register
1727#define AT91C_ST_IMR ((AT91_REG *) 0xFFFFFD1C) // (ST) Interrupt Mask Register
1728#define AT91C_ST_IER ((AT91_REG *) 0xFFFFFD14) // (ST) Interrupt Enable Register
1729#define AT91C_ST_RTMR ((AT91_REG *) 0xFFFFFD0C) // (ST) Real-time Mode Register
1730#define AT91C_ST_PIMR ((AT91_REG *) 0xFFFFFD04) // (ST) Period Interval Mode Register
1731#define AT91C_ST_RTAR ((AT91_REG *) 0xFFFFFD20) // (ST) Real-time Alarm Register
1732#define AT91C_ST_IDR ((AT91_REG *) 0xFFFFFD18) // (ST) Interrupt Disable Register
1733#define AT91C_ST_SR ((AT91_REG *) 0xFFFFFD10) // (ST) Status Register
1734#define AT91C_ST_WDMR ((AT91_REG *) 0xFFFFFD08) // (ST) Watchdog Mode Register
1735#define AT91C_ST_CR ((AT91_REG *) 0xFFFFFD00) // (ST) Control Register
1736// ========== Register definition for PMC peripheral ==========
1737#define AT91C_PMC_SCSR ((AT91_REG *) 0xFFFFFC08) // (PMC) System Clock Status Register
1738#define AT91C_PMC_SCER ((AT91_REG *) 0xFFFFFC00) // (PMC) System Clock Enable Register
1739#define AT91C_PMC_IMR ((AT91_REG *) 0xFFFFFC6C) // (PMC) Interrupt Mask Register
1740#define AT91C_PMC_IDR ((AT91_REG *) 0xFFFFFC64) // (PMC) Interrupt Disable Register
1741#define AT91C_PMC_PCDR ((AT91_REG *) 0xFFFFFC14) // (PMC) Peripheral Clock Disable Register
1742#define AT91C_PMC_SCDR ((AT91_REG *) 0xFFFFFC04) // (PMC) System Clock Disable Register
1743#define AT91C_PMC_SR ((AT91_REG *) 0xFFFFFC68) // (PMC) Status Register
1744#define AT91C_PMC_IER ((AT91_REG *) 0xFFFFFC60) // (PMC) Interrupt Enable Register
1745#define AT91C_PMC_MCKR ((AT91_REG *) 0xFFFFFC30) // (PMC) Master Clock Register
1746#define AT91C_PMC_PCER ((AT91_REG *) 0xFFFFFC10) // (PMC) Peripheral Clock Enable Register
1747#define AT91C_PMC_PCSR ((AT91_REG *) 0xFFFFFC18) // (PMC) Peripheral Clock Status Register
1748#define AT91C_PMC_PCKR ((AT91_REG *) 0xFFFFFC40) // (PMC) Programmable Clock Register
1749// ========== Register definition for CKGR peripheral ==========
1750#define AT91C_CKGR_PLLBR ((AT91_REG *) 0xFFFFFC2C) // (CKGR) PLL B Register
1751#define AT91C_CKGR_MCFR ((AT91_REG *) 0xFFFFFC24) // (CKGR) Main Clock Frequency Register
1752#define AT91C_CKGR_PLLAR ((AT91_REG *) 0xFFFFFC28) // (CKGR) PLL A Register
1753#define AT91C_CKGR_MOR ((AT91_REG *) 0xFFFFFC20) // (CKGR) Main Oscillator Register
1754// ========== Register definition for PIOD peripheral ==========
1755#define AT91C_PIOD_PDSR ((AT91_REG *) 0xFFFFFA3C) // (PIOD) Pin Data Status Register
1756#define AT91C_PIOD_CODR ((AT91_REG *) 0xFFFFFA34) // (PIOD) Clear Output Data Register
1757#define AT91C_PIOD_OWER ((AT91_REG *) 0xFFFFFAA0) // (PIOD) Output Write Enable Register
1758#define AT91C_PIOD_MDER ((AT91_REG *) 0xFFFFFA50) // (PIOD) Multi-driver Enable Register
1759#define AT91C_PIOD_IMR ((AT91_REG *) 0xFFFFFA48) // (PIOD) Interrupt Mask Register
1760#define AT91C_PIOD_IER ((AT91_REG *) 0xFFFFFA40) // (PIOD) Interrupt Enable Register
1761#define AT91C_PIOD_ODSR ((AT91_REG *) 0xFFFFFA38) // (PIOD) Output Data Status Register
1762#define AT91C_PIOD_SODR ((AT91_REG *) 0xFFFFFA30) // (PIOD) Set Output Data Register
1763#define AT91C_PIOD_PER ((AT91_REG *) 0xFFFFFA00) // (PIOD) PIO Enable Register
1764#define AT91C_PIOD_OWDR ((AT91_REG *) 0xFFFFFAA4) // (PIOD) Output Write Disable Register
1765#define AT91C_PIOD_PPUER ((AT91_REG *) 0xFFFFFA64) // (PIOD) Pull-up Enable Register
1766#define AT91C_PIOD_MDDR ((AT91_REG *) 0xFFFFFA54) // (PIOD) Multi-driver Disable Register
1767#define AT91C_PIOD_ISR ((AT91_REG *) 0xFFFFFA4C) // (PIOD) Interrupt Status Register
1768#define AT91C_PIOD_IDR ((AT91_REG *) 0xFFFFFA44) // (PIOD) Interrupt Disable Register
1769#define AT91C_PIOD_PDR ((AT91_REG *) 0xFFFFFA04) // (PIOD) PIO Disable Register
1770#define AT91C_PIOD_ODR ((AT91_REG *) 0xFFFFFA14) // (PIOD) Output Disable Registerr
1771#define AT91C_PIOD_OWSR ((AT91_REG *) 0xFFFFFAA8) // (PIOD) Output Write Status Register
1772#define AT91C_PIOD_ABSR ((AT91_REG *) 0xFFFFFA78) // (PIOD) AB Select Status Register
1773#define AT91C_PIOD_ASR ((AT91_REG *) 0xFFFFFA70) // (PIOD) Select A Register
1774#define AT91C_PIOD_PPUSR ((AT91_REG *) 0xFFFFFA68) // (PIOD) Pad Pull-up Status Register
1775#define AT91C_PIOD_PPUDR ((AT91_REG *) 0xFFFFFA60) // (PIOD) Pull-up Disable Register
1776#define AT91C_PIOD_MDSR ((AT91_REG *) 0xFFFFFA58) // (PIOD) Multi-driver Status Register
1777#define AT91C_PIOD_PSR ((AT91_REG *) 0xFFFFFA08) // (PIOD) PIO Status Register
1778#define AT91C_PIOD_OER ((AT91_REG *) 0xFFFFFA10) // (PIOD) Output Enable Register
1779#define AT91C_PIOD_OSR ((AT91_REG *) 0xFFFFFA18) // (PIOD) Output Status Register
1780#define AT91C_PIOD_IFER ((AT91_REG *) 0xFFFFFA20) // (PIOD) Input Filter Enable Register
1781#define AT91C_PIOD_BSR ((AT91_REG *) 0xFFFFFA74) // (PIOD) Select B Register
1782#define AT91C_PIOD_IFDR ((AT91_REG *) 0xFFFFFA24) // (PIOD) Input Filter Disable Register
1783#define AT91C_PIOD_IFSR ((AT91_REG *) 0xFFFFFA28) // (PIOD) Input Filter Status Register
1784// ========== Register definition for PIOC peripheral ==========
1785#define AT91C_PIOC_IFDR ((AT91_REG *) 0xFFFFF824) // (PIOC) Input Filter Disable Register
1786#define AT91C_PIOC_ODR ((AT91_REG *) 0xFFFFF814) // (PIOC) Output Disable Registerr
1787#define AT91C_PIOC_ABSR ((AT91_REG *) 0xFFFFF878) // (PIOC) AB Select Status Register
1788#define AT91C_PIOC_SODR ((AT91_REG *) 0xFFFFF830) // (PIOC) Set Output Data Register
1789#define AT91C_PIOC_IFSR ((AT91_REG *) 0xFFFFF828) // (PIOC) Input Filter Status Register
1790#define AT91C_PIOC_CODR ((AT91_REG *) 0xFFFFF834) // (PIOC) Clear Output Data Register
1791#define AT91C_PIOC_ODSR ((AT91_REG *) 0xFFFFF838) // (PIOC) Output Data Status Register
1792#define AT91C_PIOC_IER ((AT91_REG *) 0xFFFFF840) // (PIOC) Interrupt Enable Register
1793#define AT91C_PIOC_IMR ((AT91_REG *) 0xFFFFF848) // (PIOC) Interrupt Mask Register
1794#define AT91C_PIOC_OWDR ((AT91_REG *) 0xFFFFF8A4) // (PIOC) Output Write Disable Register
1795#define AT91C_PIOC_MDDR ((AT91_REG *) 0xFFFFF854) // (PIOC) Multi-driver Disable Register
1796#define AT91C_PIOC_PDSR ((AT91_REG *) 0xFFFFF83C) // (PIOC) Pin Data Status Register
1797#define AT91C_PIOC_IDR ((AT91_REG *) 0xFFFFF844) // (PIOC) Interrupt Disable Register
1798#define AT91C_PIOC_ISR ((AT91_REG *) 0xFFFFF84C) // (PIOC) Interrupt Status Register
1799#define AT91C_PIOC_PDR ((AT91_REG *) 0xFFFFF804) // (PIOC) PIO Disable Register
1800#define AT91C_PIOC_OWSR ((AT91_REG *) 0xFFFFF8A8) // (PIOC) Output Write Status Register
1801#define AT91C_PIOC_OWER ((AT91_REG *) 0xFFFFF8A0) // (PIOC) Output Write Enable Register
1802#define AT91C_PIOC_ASR ((AT91_REG *) 0xFFFFF870) // (PIOC) Select A Register
1803#define AT91C_PIOC_PPUSR ((AT91_REG *) 0xFFFFF868) // (PIOC) Pad Pull-up Status Register
1804#define AT91C_PIOC_PPUDR ((AT91_REG *) 0xFFFFF860) // (PIOC) Pull-up Disable Register
1805#define AT91C_PIOC_MDSR ((AT91_REG *) 0xFFFFF858) // (PIOC) Multi-driver Status Register
1806#define AT91C_PIOC_MDER ((AT91_REG *) 0xFFFFF850) // (PIOC) Multi-driver Enable Register
1807#define AT91C_PIOC_IFER ((AT91_REG *) 0xFFFFF820) // (PIOC) Input Filter Enable Register
1808#define AT91C_PIOC_OSR ((AT91_REG *) 0xFFFFF818) // (PIOC) Output Status Register
1809#define AT91C_PIOC_OER ((AT91_REG *) 0xFFFFF810) // (PIOC) Output Enable Register
1810#define AT91C_PIOC_PSR ((AT91_REG *) 0xFFFFF808) // (PIOC) PIO Status Register
1811#define AT91C_PIOC_PER ((AT91_REG *) 0xFFFFF800) // (PIOC) PIO Enable Register
1812#define AT91C_PIOC_BSR ((AT91_REG *) 0xFFFFF874) // (PIOC) Select B Register
1813#define AT91C_PIOC_PPUER ((AT91_REG *) 0xFFFFF864) // (PIOC) Pull-up Enable Register
1814// ========== Register definition for PIOB peripheral ==========
1815#define AT91C_PIOB_OWSR ((AT91_REG *) 0xFFFFF6A8) // (PIOB) Output Write Status Register
1816#define AT91C_PIOB_PPUSR ((AT91_REG *) 0xFFFFF668) // (PIOB) Pad Pull-up Status Register
1817#define AT91C_PIOB_PPUDR ((AT91_REG *) 0xFFFFF660) // (PIOB) Pull-up Disable Register
1818#define AT91C_PIOB_MDSR ((AT91_REG *) 0xFFFFF658) // (PIOB) Multi-driver Status Register
1819#define AT91C_PIOB_MDER ((AT91_REG *) 0xFFFFF650) // (PIOB) Multi-driver Enable Register
1820#define AT91C_PIOB_IMR ((AT91_REG *) 0xFFFFF648) // (PIOB) Interrupt Mask Register
1821#define AT91C_PIOB_OSR ((AT91_REG *) 0xFFFFF618) // (PIOB) Output Status Register
1822#define AT91C_PIOB_OER ((AT91_REG *) 0xFFFFF610) // (PIOB) Output Enable Register
1823#define AT91C_PIOB_PSR ((AT91_REG *) 0xFFFFF608) // (PIOB) PIO Status Register
1824#define AT91C_PIOB_PER ((AT91_REG *) 0xFFFFF600) // (PIOB) PIO Enable Register
1825#define AT91C_PIOB_BSR ((AT91_REG *) 0xFFFFF674) // (PIOB) Select B Register
1826#define AT91C_PIOB_PPUER ((AT91_REG *) 0xFFFFF664) // (PIOB) Pull-up Enable Register
1827#define AT91C_PIOB_IFDR ((AT91_REG *) 0xFFFFF624) // (PIOB) Input Filter Disable Register
1828#define AT91C_PIOB_ODR ((AT91_REG *) 0xFFFFF614) // (PIOB) Output Disable Registerr
1829#define AT91C_PIOB_ABSR ((AT91_REG *) 0xFFFFF678) // (PIOB) AB Select Status Register
1830#define AT91C_PIOB_ASR ((AT91_REG *) 0xFFFFF670) // (PIOB) Select A Register
1831#define AT91C_PIOB_IFER ((AT91_REG *) 0xFFFFF620) // (PIOB) Input Filter Enable Register
1832#define AT91C_PIOB_IFSR ((AT91_REG *) 0xFFFFF628) // (PIOB) Input Filter Status Register
1833#define AT91C_PIOB_SODR ((AT91_REG *) 0xFFFFF630) // (PIOB) Set Output Data Register
1834#define AT91C_PIOB_ODSR ((AT91_REG *) 0xFFFFF638) // (PIOB) Output Data Status Register
1835#define AT91C_PIOB_CODR ((AT91_REG *) 0xFFFFF634) // (PIOB) Clear Output Data Register
1836#define AT91C_PIOB_PDSR ((AT91_REG *) 0xFFFFF63C) // (PIOB) Pin Data Status Register
1837#define AT91C_PIOB_OWER ((AT91_REG *) 0xFFFFF6A0) // (PIOB) Output Write Enable Register
1838#define AT91C_PIOB_IER ((AT91_REG *) 0xFFFFF640) // (PIOB) Interrupt Enable Register
1839#define AT91C_PIOB_OWDR ((AT91_REG *) 0xFFFFF6A4) // (PIOB) Output Write Disable Register
1840#define AT91C_PIOB_MDDR ((AT91_REG *) 0xFFFFF654) // (PIOB) Multi-driver Disable Register
1841#define AT91C_PIOB_ISR ((AT91_REG *) 0xFFFFF64C) // (PIOB) Interrupt Status Register
1842#define AT91C_PIOB_IDR ((AT91_REG *) 0xFFFFF644) // (PIOB) Interrupt Disable Register
1843#define AT91C_PIOB_PDR ((AT91_REG *) 0xFFFFF604) // (PIOB) PIO Disable Register
1844// ========== Register definition for PIOA peripheral ==========
1845#define AT91C_PIOA_IMR ((AT91_REG *) 0xFFFFF448) // (PIOA) Interrupt Mask Register
1846#define AT91C_PIOA_IER ((AT91_REG *) 0xFFFFF440) // (PIOA) Interrupt Enable Register
1847#define AT91C_PIOA_OWDR ((AT91_REG *) 0xFFFFF4A4) // (PIOA) Output Write Disable Register
1848#define AT91C_PIOA_ISR ((AT91_REG *) 0xFFFFF44C) // (PIOA) Interrupt Status Register
1849#define AT91C_PIOA_PPUDR ((AT91_REG *) 0xFFFFF460) // (PIOA) Pull-up Disable Register
1850#define AT91C_PIOA_MDSR ((AT91_REG *) 0xFFFFF458) // (PIOA) Multi-driver Status Register
1851#define AT91C_PIOA_MDER ((AT91_REG *) 0xFFFFF450) // (PIOA) Multi-driver Enable Register
1852#define AT91C_PIOA_PER ((AT91_REG *) 0xFFFFF400) // (PIOA) PIO Enable Register
1853#define AT91C_PIOA_PSR ((AT91_REG *) 0xFFFFF408) // (PIOA) PIO Status Register
1854#define AT91C_PIOA_OER ((AT91_REG *) 0xFFFFF410) // (PIOA) Output Enable Register
1855#define AT91C_PIOA_BSR ((AT91_REG *) 0xFFFFF474) // (PIOA) Select B Register
1856#define AT91C_PIOA_PPUER ((AT91_REG *) 0xFFFFF464) // (PIOA) Pull-up Enable Register
1857#define AT91C_PIOA_MDDR ((AT91_REG *) 0xFFFFF454) // (PIOA) Multi-driver Disable Register
1858#define AT91C_PIOA_PDR ((AT91_REG *) 0xFFFFF404) // (PIOA) PIO Disable Register
1859#define AT91C_PIOA_ODR ((AT91_REG *) 0xFFFFF414) // (PIOA) Output Disable Registerr
1860#define AT91C_PIOA_IFDR ((AT91_REG *) 0xFFFFF424) // (PIOA) Input Filter Disable Register
1861#define AT91C_PIOA_ABSR ((AT91_REG *) 0xFFFFF478) // (PIOA) AB Select Status Register
1862#define AT91C_PIOA_ASR ((AT91_REG *) 0xFFFFF470) // (PIOA) Select A Register
1863#define AT91C_PIOA_PPUSR ((AT91_REG *) 0xFFFFF468) // (PIOA) Pad Pull-up Status Register
1864#define AT91C_PIOA_ODSR ((AT91_REG *) 0xFFFFF438) // (PIOA) Output Data Status Register
1865#define AT91C_PIOA_SODR ((AT91_REG *) 0xFFFFF430) // (PIOA) Set Output Data Register
1866#define AT91C_PIOA_IFSR ((AT91_REG *) 0xFFFFF428) // (PIOA) Input Filter Status Register
1867#define AT91C_PIOA_IFER ((AT91_REG *) 0xFFFFF420) // (PIOA) Input Filter Enable Register
1868#define AT91C_PIOA_OSR ((AT91_REG *) 0xFFFFF418) // (PIOA) Output Status Register
1869#define AT91C_PIOA_IDR ((AT91_REG *) 0xFFFFF444) // (PIOA) Interrupt Disable Register
1870#define AT91C_PIOA_PDSR ((AT91_REG *) 0xFFFFF43C) // (PIOA) Pin Data Status Register
1871#define AT91C_PIOA_CODR ((AT91_REG *) 0xFFFFF434) // (PIOA) Clear Output Data Register
1872#define AT91C_PIOA_OWSR ((AT91_REG *) 0xFFFFF4A8) // (PIOA) Output Write Status Register
1873#define AT91C_PIOA_OWER ((AT91_REG *) 0xFFFFF4A0) // (PIOA) Output Write Enable Register
1874// ========== Register definition for DBGU peripheral ==========
1875#define AT91C_DBGU_C2R ((AT91_REG *) 0xFFFFF244) // (DBGU) Chip ID2 Register
1876#define AT91C_DBGU_THR ((AT91_REG *) 0xFFFFF21C) // (DBGU) Transmitter Holding Register
1877#define AT91C_DBGU_CSR ((AT91_REG *) 0xFFFFF214) // (DBGU) Channel Status Register
1878#define AT91C_DBGU_IDR ((AT91_REG *) 0xFFFFF20C) // (DBGU) Interrupt Disable Register
1879#define AT91C_DBGU_MR ((AT91_REG *) 0xFFFFF204) // (DBGU) Mode Register
1880#define AT91C_DBGU_FNTR ((AT91_REG *) 0xFFFFF248) // (DBGU) Force NTRST Register
1881#define AT91C_DBGU_C1R ((AT91_REG *) 0xFFFFF240) // (DBGU) Chip ID1 Register
1882#define AT91C_DBGU_BRGR ((AT91_REG *) 0xFFFFF220) // (DBGU) Baud Rate Generator Register
1883#define AT91C_DBGU_RHR ((AT91_REG *) 0xFFFFF218) // (DBGU) Receiver Holding Register
1884#define AT91C_DBGU_IMR ((AT91_REG *) 0xFFFFF210) // (DBGU) Interrupt Mask Register
1885#define AT91C_DBGU_IER ((AT91_REG *) 0xFFFFF208) // (DBGU) Interrupt Enable Register
1886#define AT91C_DBGU_CR ((AT91_REG *) 0xFFFFF200) // (DBGU) Control Register
1887// ========== Register definition for PDC_DBGU peripheral ==========
1888#define AT91C_DBGU_TNCR ((AT91_REG *) 0xFFFFF31C) // (PDC_DBGU) Transmit Next Counter Register
1889#define AT91C_DBGU_RNCR ((AT91_REG *) 0xFFFFF314) // (PDC_DBGU) Receive Next Counter Register
1890#define AT91C_DBGU_PTCR ((AT91_REG *) 0xFFFFF320) // (PDC_DBGU) PDC Transfer Control Register
1891#define AT91C_DBGU_PTSR ((AT91_REG *) 0xFFFFF324) // (PDC_DBGU) PDC Transfer Status Register
1892#define AT91C_DBGU_RCR ((AT91_REG *) 0xFFFFF304) // (PDC_DBGU) Receive Counter Register
1893#define AT91C_DBGU_TCR ((AT91_REG *) 0xFFFFF30C) // (PDC_DBGU) Transmit Counter Register
1894#define AT91C_DBGU_RPR ((AT91_REG *) 0xFFFFF300) // (PDC_DBGU) Receive Pointer Register
1895#define AT91C_DBGU_TPR ((AT91_REG *) 0xFFFFF308) // (PDC_DBGU) Transmit Pointer Register
1896#define AT91C_DBGU_RNPR ((AT91_REG *) 0xFFFFF310) // (PDC_DBGU) Receive Next Pointer Register
1897#define AT91C_DBGU_TNPR ((AT91_REG *) 0xFFFFF318) // (PDC_DBGU) Transmit Next Pointer Register
1898// ========== Register definition for AIC peripheral ==========
1899#define AT91C_AIC_ICCR ((AT91_REG *) 0xFFFFF128) // (AIC) Interrupt Clear Command Register
1900#define AT91C_AIC_IECR ((AT91_REG *) 0xFFFFF120) // (AIC) Interrupt Enable Command Register
1901#define AT91C_AIC_SMR ((AT91_REG *) 0xFFFFF000) // (AIC) Source Mode Register
1902#define AT91C_AIC_ISCR ((AT91_REG *) 0xFFFFF12C) // (AIC) Interrupt Set Command Register
1903#define AT91C_AIC_EOICR ((AT91_REG *) 0xFFFFF130) // (AIC) End of Interrupt Command Register
1904#define AT91C_AIC_DCR ((AT91_REG *) 0xFFFFF138) // (AIC) Debug Control Register (Protect)
1905#define AT91C_AIC_FFER ((AT91_REG *) 0xFFFFF140) // (AIC) Fast Forcing Enable Register
1906#define AT91C_AIC_SVR ((AT91_REG *) 0xFFFFF080) // (AIC) Source Vector Register
1907#define AT91C_AIC_SPU ((AT91_REG *) 0xFFFFF134) // (AIC) Spurious Vector Register
1908#define AT91C_AIC_FFDR ((AT91_REG *) 0xFFFFF144) // (AIC) Fast Forcing Disable Register
1909#define AT91C_AIC_FVR ((AT91_REG *) 0xFFFFF104) // (AIC) FIQ Vector Register
1910#define AT91C_AIC_FFSR ((AT91_REG *) 0xFFFFF148) // (AIC) Fast Forcing Status Register
1911#define AT91C_AIC_IMR ((AT91_REG *) 0xFFFFF110) // (AIC) Interrupt Mask Register
1912#define AT91C_AIC_ISR ((AT91_REG *) 0xFFFFF108) // (AIC) Interrupt Status Register
1913#define AT91C_AIC_IVR ((AT91_REG *) 0xFFFFF100) // (AIC) IRQ Vector Register
1914#define AT91C_AIC_IDCR ((AT91_REG *) 0xFFFFF124) // (AIC) Interrupt Disable Command Register
1915#define AT91C_AIC_CISR ((AT91_REG *) 0xFFFFF114) // (AIC) Core Interrupt Status Register
1916#define AT91C_AIC_IPR ((AT91_REG *) 0xFFFFF10C) // (AIC) Interrupt Pending Register
1917// ========== Register definition for PDC_SPI peripheral ==========
1918#define AT91C_SPI_PTCR ((AT91_REG *) 0xFFFE0120) // (PDC_SPI) PDC Transfer Control Register
1919#define AT91C_SPI_TNPR ((AT91_REG *) 0xFFFE0118) // (PDC_SPI) Transmit Next Pointer Register
1920#define AT91C_SPI_RNPR ((AT91_REG *) 0xFFFE0110) // (PDC_SPI) Receive Next Pointer Register
1921#define AT91C_SPI_TPR ((AT91_REG *) 0xFFFE0108) // (PDC_SPI) Transmit Pointer Register
1922#define AT91C_SPI_RPR ((AT91_REG *) 0xFFFE0100) // (PDC_SPI) Receive Pointer Register
1923#define AT91C_SPI_PTSR ((AT91_REG *) 0xFFFE0124) // (PDC_SPI) PDC Transfer Status Register
1924#define AT91C_SPI_TNCR ((AT91_REG *) 0xFFFE011C) // (PDC_SPI) Transmit Next Counter Register
1925#define AT91C_SPI_RNCR ((AT91_REG *) 0xFFFE0114) // (PDC_SPI) Receive Next Counter Register
1926#define AT91C_SPI_TCR ((AT91_REG *) 0xFFFE010C) // (PDC_SPI) Transmit Counter Register
1927#define AT91C_SPI_RCR ((AT91_REG *) 0xFFFE0104) // (PDC_SPI) Receive Counter Register
1928// ========== Register definition for SPI peripheral ==========
1929#define AT91C_SPI_CSR ((AT91_REG *) 0xFFFE0030) // (SPI) Chip Select Register
1930#define AT91C_SPI_IDR ((AT91_REG *) 0xFFFE0018) // (SPI) Interrupt Disable Register
1931#define AT91C_SPI_SR ((AT91_REG *) 0xFFFE0010) // (SPI) Status Register
1932#define AT91C_SPI_RDR ((AT91_REG *) 0xFFFE0008) // (SPI) Receive Data Register
1933#define AT91C_SPI_CR ((AT91_REG *) 0xFFFE0000) // (SPI) Control Register
1934#define AT91C_SPI_IMR ((AT91_REG *) 0xFFFE001C) // (SPI) Interrupt Mask Register
1935#define AT91C_SPI_IER ((AT91_REG *) 0xFFFE0014) // (SPI) Interrupt Enable Register
1936#define AT91C_SPI_TDR ((AT91_REG *) 0xFFFE000C) // (SPI) Transmit Data Register
1937#define AT91C_SPI_MR ((AT91_REG *) 0xFFFE0004) // (SPI) Mode Register
1938// ========== Register definition for PDC_SSC2 peripheral ==========
1939#define AT91C_SSC2_PTCR ((AT91_REG *) 0xFFFD8120) // (PDC_SSC2) PDC Transfer Control Register
1940#define AT91C_SSC2_TNPR ((AT91_REG *) 0xFFFD8118) // (PDC_SSC2) Transmit Next Pointer Register
1941#define AT91C_SSC2_RNPR ((AT91_REG *) 0xFFFD8110) // (PDC_SSC2) Receive Next Pointer Register
1942#define AT91C_SSC2_TPR ((AT91_REG *) 0xFFFD8108) // (PDC_SSC2) Transmit Pointer Register
1943#define AT91C_SSC2_RPR ((AT91_REG *) 0xFFFD8100) // (PDC_SSC2) Receive Pointer Register
1944#define AT91C_SSC2_PTSR ((AT91_REG *) 0xFFFD8124) // (PDC_SSC2) PDC Transfer Status Register
1945#define AT91C_SSC2_TNCR ((AT91_REG *) 0xFFFD811C) // (PDC_SSC2) Transmit Next Counter Register
1946#define AT91C_SSC2_RNCR ((AT91_REG *) 0xFFFD8114) // (PDC_SSC2) Receive Next Counter Register
1947#define AT91C_SSC2_TCR ((AT91_REG *) 0xFFFD810C) // (PDC_SSC2) Transmit Counter Register
1948#define AT91C_SSC2_RCR ((AT91_REG *) 0xFFFD8104) // (PDC_SSC2) Receive Counter Register
1949// ========== Register definition for SSC2 peripheral ==========
1950#define AT91C_SSC2_IMR ((AT91_REG *) 0xFFFD804C) // (SSC2) Interrupt Mask Register
1951#define AT91C_SSC2_IER ((AT91_REG *) 0xFFFD8044) // (SSC2) Interrupt Enable Register
1952#define AT91C_SSC2_RC1R ((AT91_REG *) 0xFFFD803C) // (SSC2) Receive Compare 1 Register
1953#define AT91C_SSC2_TSHR ((AT91_REG *) 0xFFFD8034) // (SSC2) Transmit Sync Holding Register
1954#define AT91C_SSC2_CMR ((AT91_REG *) 0xFFFD8004) // (SSC2) Clock Mode Register
1955#define AT91C_SSC2_IDR ((AT91_REG *) 0xFFFD8048) // (SSC2) Interrupt Disable Register
1956#define AT91C_SSC2_TCMR ((AT91_REG *) 0xFFFD8018) // (SSC2) Transmit Clock Mode Register
1957#define AT91C_SSC2_RCMR ((AT91_REG *) 0xFFFD8010) // (SSC2) Receive Clock ModeRegister
1958#define AT91C_SSC2_CR ((AT91_REG *) 0xFFFD8000) // (SSC2) Control Register
1959#define AT91C_SSC2_RFMR ((AT91_REG *) 0xFFFD8014) // (SSC2) Receive Frame Mode Register
1960#define AT91C_SSC2_TFMR ((AT91_REG *) 0xFFFD801C) // (SSC2) Transmit Frame Mode Register
1961#define AT91C_SSC2_THR ((AT91_REG *) 0xFFFD8024) // (SSC2) Transmit Holding Register
1962#define AT91C_SSC2_SR ((AT91_REG *) 0xFFFD8040) // (SSC2) Status Register
1963#define AT91C_SSC2_RC0R ((AT91_REG *) 0xFFFD8038) // (SSC2) Receive Compare 0 Register
1964#define AT91C_SSC2_RSHR ((AT91_REG *) 0xFFFD8030) // (SSC2) Receive Sync Holding Register
1965#define AT91C_SSC2_RHR ((AT91_REG *) 0xFFFD8020) // (SSC2) Receive Holding Register
1966// ========== Register definition for PDC_SSC1 peripheral ==========
1967#define AT91C_SSC1_PTCR ((AT91_REG *) 0xFFFD4120) // (PDC_SSC1) PDC Transfer Control Register
1968#define AT91C_SSC1_TNPR ((AT91_REG *) 0xFFFD4118) // (PDC_SSC1) Transmit Next Pointer Register
1969#define AT91C_SSC1_RNPR ((AT91_REG *) 0xFFFD4110) // (PDC_SSC1) Receive Next Pointer Register
1970#define AT91C_SSC1_TPR ((AT91_REG *) 0xFFFD4108) // (PDC_SSC1) Transmit Pointer Register
1971#define AT91C_SSC1_RPR ((AT91_REG *) 0xFFFD4100) // (PDC_SSC1) Receive Pointer Register
1972#define AT91C_SSC1_PTSR ((AT91_REG *) 0xFFFD4124) // (PDC_SSC1) PDC Transfer Status Register
1973#define AT91C_SSC1_TNCR ((AT91_REG *) 0xFFFD411C) // (PDC_SSC1) Transmit Next Counter Register
1974#define AT91C_SSC1_RNCR ((AT91_REG *) 0xFFFD4114) // (PDC_SSC1) Receive Next Counter Register
1975#define AT91C_SSC1_TCR ((AT91_REG *) 0xFFFD410C) // (PDC_SSC1) Transmit Counter Register
1976#define AT91C_SSC1_RCR ((AT91_REG *) 0xFFFD4104) // (PDC_SSC1) Receive Counter Register
1977// ========== Register definition for SSC1 peripheral ==========
1978#define AT91C_SSC1_RFMR ((AT91_REG *) 0xFFFD4014) // (SSC1) Receive Frame Mode Register
1979#define AT91C_SSC1_CMR ((AT91_REG *) 0xFFFD4004) // (SSC1) Clock Mode Register
1980#define AT91C_SSC1_IDR ((AT91_REG *) 0xFFFD4048) // (SSC1) Interrupt Disable Register
1981#define AT91C_SSC1_SR ((AT91_REG *) 0xFFFD4040) // (SSC1) Status Register
1982#define AT91C_SSC1_RC0R ((AT91_REG *) 0xFFFD4038) // (SSC1) Receive Compare 0 Register
1983#define AT91C_SSC1_RSHR ((AT91_REG *) 0xFFFD4030) // (SSC1) Receive Sync Holding Register
1984#define AT91C_SSC1_RHR ((AT91_REG *) 0xFFFD4020) // (SSC1) Receive Holding Register
1985#define AT91C_SSC1_TCMR ((AT91_REG *) 0xFFFD4018) // (SSC1) Transmit Clock Mode Register
1986#define AT91C_SSC1_RCMR ((AT91_REG *) 0xFFFD4010) // (SSC1) Receive Clock ModeRegister
1987#define AT91C_SSC1_CR ((AT91_REG *) 0xFFFD4000) // (SSC1) Control Register
1988#define AT91C_SSC1_IMR ((AT91_REG *) 0xFFFD404C) // (SSC1) Interrupt Mask Register
1989#define AT91C_SSC1_IER ((AT91_REG *) 0xFFFD4044) // (SSC1) Interrupt Enable Register
1990#define AT91C_SSC1_RC1R ((AT91_REG *) 0xFFFD403C) // (SSC1) Receive Compare 1 Register
1991#define AT91C_SSC1_TSHR ((AT91_REG *) 0xFFFD4034) // (SSC1) Transmit Sync Holding Register
1992#define AT91C_SSC1_THR ((AT91_REG *) 0xFFFD4024) // (SSC1) Transmit Holding Register
1993#define AT91C_SSC1_TFMR ((AT91_REG *) 0xFFFD401C) // (SSC1) Transmit Frame Mode Register
1994// ========== Register definition for PDC_SSC0 peripheral ==========
1995#define AT91C_SSC0_PTCR ((AT91_REG *) 0xFFFD0120) // (PDC_SSC0) PDC Transfer Control Register
1996#define AT91C_SSC0_TNPR ((AT91_REG *) 0xFFFD0118) // (PDC_SSC0) Transmit Next Pointer Register
1997#define AT91C_SSC0_RNPR ((AT91_REG *) 0xFFFD0110) // (PDC_SSC0) Receive Next Pointer Register
1998#define AT91C_SSC0_TPR ((AT91_REG *) 0xFFFD0108) // (PDC_SSC0) Transmit Pointer Register
1999#define AT91C_SSC0_RPR ((AT91_REG *) 0xFFFD0100) // (PDC_SSC0) Receive Pointer Register
2000#define AT91C_SSC0_PTSR ((AT91_REG *) 0xFFFD0124) // (PDC_SSC0) PDC Transfer Status Register
2001#define AT91C_SSC0_TNCR ((AT91_REG *) 0xFFFD011C) // (PDC_SSC0) Transmit Next Counter Register
2002#define AT91C_SSC0_RNCR ((AT91_REG *) 0xFFFD0114) // (PDC_SSC0) Receive Next Counter Register
2003#define AT91C_SSC0_TCR ((AT91_REG *) 0xFFFD010C) // (PDC_SSC0) Transmit Counter Register
2004#define AT91C_SSC0_RCR ((AT91_REG *) 0xFFFD0104) // (PDC_SSC0) Receive Counter Register
2005// ========== Register definition for SSC0 peripheral ==========
2006#define AT91C_SSC0_IMR ((AT91_REG *) 0xFFFD004C) // (SSC0) Interrupt Mask Register
2007#define AT91C_SSC0_IER ((AT91_REG *) 0xFFFD0044) // (SSC0) Interrupt Enable Register
2008#define AT91C_SSC0_RC1R ((AT91_REG *) 0xFFFD003C) // (SSC0) Receive Compare 1 Register
2009#define AT91C_SSC0_TSHR ((AT91_REG *) 0xFFFD0034) // (SSC0) Transmit Sync Holding Register
2010#define AT91C_SSC0_THR ((AT91_REG *) 0xFFFD0024) // (SSC0) Transmit Holding Register
2011#define AT91C_SSC0_TFMR ((AT91_REG *) 0xFFFD001C) // (SSC0) Transmit Frame Mode Register
2012#define AT91C_SSC0_RFMR ((AT91_REG *) 0xFFFD0014) // (SSC0) Receive Frame Mode Register
2013#define AT91C_SSC0_CMR ((AT91_REG *) 0xFFFD0004) // (SSC0) Clock Mode Register
2014#define AT91C_SSC0_IDR ((AT91_REG *) 0xFFFD0048) // (SSC0) Interrupt Disable Register
2015#define AT91C_SSC0_SR ((AT91_REG *) 0xFFFD0040) // (SSC0) Status Register
2016#define AT91C_SSC0_RC0R ((AT91_REG *) 0xFFFD0038) // (SSC0) Receive Compare 0 Register
2017#define AT91C_SSC0_RSHR ((AT91_REG *) 0xFFFD0030) // (SSC0) Receive Sync Holding Register
2018#define AT91C_SSC0_RHR ((AT91_REG *) 0xFFFD0020) // (SSC0) Receive Holding Register
2019#define AT91C_SSC0_TCMR ((AT91_REG *) 0xFFFD0018) // (SSC0) Transmit Clock Mode Register
2020#define AT91C_SSC0_RCMR ((AT91_REG *) 0xFFFD0010) // (SSC0) Receive Clock ModeRegister
2021#define AT91C_SSC0_CR ((AT91_REG *) 0xFFFD0000) // (SSC0) Control Register
2022// ========== Register definition for PDC_US3 peripheral ==========
2023#define AT91C_US3_PTSR ((AT91_REG *) 0xFFFCC124) // (PDC_US3) PDC Transfer Status Register
2024#define AT91C_US3_TNCR ((AT91_REG *) 0xFFFCC11C) // (PDC_US3) Transmit Next Counter Register
2025#define AT91C_US3_RNCR ((AT91_REG *) 0xFFFCC114) // (PDC_US3) Receive Next Counter Register
2026#define AT91C_US3_TCR ((AT91_REG *) 0xFFFCC10C) // (PDC_US3) Transmit Counter Register
2027#define AT91C_US3_RCR ((AT91_REG *) 0xFFFCC104) // (PDC_US3) Receive Counter Register
2028#define AT91C_US3_PTCR ((AT91_REG *) 0xFFFCC120) // (PDC_US3) PDC Transfer Control Register
2029#define AT91C_US3_TNPR ((AT91_REG *) 0xFFFCC118) // (PDC_US3) Transmit Next Pointer Register
2030#define AT91C_US3_RNPR ((AT91_REG *) 0xFFFCC110) // (PDC_US3) Receive Next Pointer Register
2031#define AT91C_US3_TPR ((AT91_REG *) 0xFFFCC108) // (PDC_US3) Transmit Pointer Register
2032#define AT91C_US3_RPR ((AT91_REG *) 0xFFFCC100) // (PDC_US3) Receive Pointer Register
2033// ========== Register definition for US3 peripheral ==========
2034#define AT91C_US3_IF ((AT91_REG *) 0xFFFCC04C) // (US3) IRDA_FILTER Register
2035#define AT91C_US3_NER ((AT91_REG *) 0xFFFCC044) // (US3) Nb Errors Register
2036#define AT91C_US3_RTOR ((AT91_REG *) 0xFFFCC024) // (US3) Receiver Time-out Register
2037#define AT91C_US3_THR ((AT91_REG *) 0xFFFCC01C) // (US3) Transmitter Holding Register
2038#define AT91C_US3_CSR ((AT91_REG *) 0xFFFCC014) // (US3) Channel Status Register
2039#define AT91C_US3_IDR ((AT91_REG *) 0xFFFCC00C) // (US3) Interrupt Disable Register
2040#define AT91C_US3_MR ((AT91_REG *) 0xFFFCC004) // (US3) Mode Register
2041#define AT91C_US3_XXR ((AT91_REG *) 0xFFFCC048) // (US3) XON_XOFF Register
2042#define AT91C_US3_FIDI ((AT91_REG *) 0xFFFCC040) // (US3) FI_DI_Ratio Register
2043#define AT91C_US3_TTGR ((AT91_REG *) 0xFFFCC028) // (US3) Transmitter Time-guard Register
2044#define AT91C_US3_BRGR ((AT91_REG *) 0xFFFCC020) // (US3) Baud Rate Generator Register
2045#define AT91C_US3_RHR ((AT91_REG *) 0xFFFCC018) // (US3) Receiver Holding Register
2046#define AT91C_US3_IMR ((AT91_REG *) 0xFFFCC010) // (US3) Interrupt Mask Register
2047#define AT91C_US3_IER ((AT91_REG *) 0xFFFCC008) // (US3) Interrupt Enable Register
2048#define AT91C_US3_CR ((AT91_REG *) 0xFFFCC000) // (US3) Control Register
2049// ========== Register definition for PDC_US2 peripheral ==========
2050#define AT91C_US2_PTSR ((AT91_REG *) 0xFFFC8124) // (PDC_US2) PDC Transfer Status Register
2051#define AT91C_US2_TNCR ((AT91_REG *) 0xFFFC811C) // (PDC_US2) Transmit Next Counter Register
2052#define AT91C_US2_RNCR ((AT91_REG *) 0xFFFC8114) // (PDC_US2) Receive Next Counter Register
2053#define AT91C_US2_TCR ((AT91_REG *) 0xFFFC810C) // (PDC_US2) Transmit Counter Register
2054#define AT91C_US2_PTCR ((AT91_REG *) 0xFFFC8120) // (PDC_US2) PDC Transfer Control Register
2055#define AT91C_US2_RCR ((AT91_REG *) 0xFFFC8104) // (PDC_US2) Receive Counter Register
2056#define AT91C_US2_TNPR ((AT91_REG *) 0xFFFC8118) // (PDC_US2) Transmit Next Pointer Register
2057#define AT91C_US2_RPR ((AT91_REG *) 0xFFFC8100) // (PDC_US2) Receive Pointer Register
2058#define AT91C_US2_TPR ((AT91_REG *) 0xFFFC8108) // (PDC_US2) Transmit Pointer Register
2059#define AT91C_US2_RNPR ((AT91_REG *) 0xFFFC8110) // (PDC_US2) Receive Next Pointer Register
2060// ========== Register definition for US2 peripheral ==========
2061#define AT91C_US2_XXR ((AT91_REG *) 0xFFFC8048) // (US2) XON_XOFF Register
2062#define AT91C_US2_FIDI ((AT91_REG *) 0xFFFC8040) // (US2) FI_DI_Ratio Register
2063#define AT91C_US2_TTGR ((AT91_REG *) 0xFFFC8028) // (US2) Transmitter Time-guard Register
2064#define AT91C_US2_BRGR ((AT91_REG *) 0xFFFC8020) // (US2) Baud Rate Generator Register
2065#define AT91C_US2_RHR ((AT91_REG *) 0xFFFC8018) // (US2) Receiver Holding Register
2066#define AT91C_US2_IMR ((AT91_REG *) 0xFFFC8010) // (US2) Interrupt Mask Register
2067#define AT91C_US2_IER ((AT91_REG *) 0xFFFC8008) // (US2) Interrupt Enable Register
2068#define AT91C_US2_CR ((AT91_REG *) 0xFFFC8000) // (US2) Control Register
2069#define AT91C_US2_IF ((AT91_REG *) 0xFFFC804C) // (US2) IRDA_FILTER Register
2070#define AT91C_US2_NER ((AT91_REG *) 0xFFFC8044) // (US2) Nb Errors Register
2071#define AT91C_US2_RTOR ((AT91_REG *) 0xFFFC8024) // (US2) Receiver Time-out Register
2072#define AT91C_US2_THR ((AT91_REG *) 0xFFFC801C) // (US2) Transmitter Holding Register
2073#define AT91C_US2_CSR ((AT91_REG *) 0xFFFC8014) // (US2) Channel Status Register
2074#define AT91C_US2_IDR ((AT91_REG *) 0xFFFC800C) // (US2) Interrupt Disable Register
2075#define AT91C_US2_MR ((AT91_REG *) 0xFFFC8004) // (US2) Mode Register
2076// ========== Register definition for PDC_US1 peripheral ==========
2077#define AT91C_US1_PTSR ((AT91_REG *) 0xFFFC4124) // (PDC_US1) PDC Transfer Status Register
2078#define AT91C_US1_TNCR ((AT91_REG *) 0xFFFC411C) // (PDC_US1) Transmit Next Counter Register
2079#define AT91C_US1_RNCR ((AT91_REG *) 0xFFFC4114) // (PDC_US1) Receive Next Counter Register
2080#define AT91C_US1_TCR ((AT91_REG *) 0xFFFC410C) // (PDC_US1) Transmit Counter Register
2081#define AT91C_US1_RCR ((AT91_REG *) 0xFFFC4104) // (PDC_US1) Receive Counter Register
2082#define AT91C_US1_PTCR ((AT91_REG *) 0xFFFC4120) // (PDC_US1) PDC Transfer Control Register
2083#define AT91C_US1_TNPR ((AT91_REG *) 0xFFFC4118) // (PDC_US1) Transmit Next Pointer Register
2084#define AT91C_US1_RNPR ((AT91_REG *) 0xFFFC4110) // (PDC_US1) Receive Next Pointer Register
2085#define AT91C_US1_TPR ((AT91_REG *) 0xFFFC4108) // (PDC_US1) Transmit Pointer Register
2086#define AT91C_US1_RPR ((AT91_REG *) 0xFFFC4100) // (PDC_US1) Receive Pointer Register
2087// ========== Register definition for US1 peripheral ==========
2088#define AT91C_US1_XXR ((AT91_REG *) 0xFFFC4048) // (US1) XON_XOFF Register
2089#define AT91C_US1_RHR ((AT91_REG *) 0xFFFC4018) // (US1) Receiver Holding Register
2090#define AT91C_US1_IMR ((AT91_REG *) 0xFFFC4010) // (US1) Interrupt Mask Register
2091#define AT91C_US1_IER ((AT91_REG *) 0xFFFC4008) // (US1) Interrupt Enable Register
2092#define AT91C_US1_CR ((AT91_REG *) 0xFFFC4000) // (US1) Control Register
2093#define AT91C_US1_RTOR ((AT91_REG *) 0xFFFC4024) // (US1) Receiver Time-out Register
2094#define AT91C_US1_THR ((AT91_REG *) 0xFFFC401C) // (US1) Transmitter Holding Register
2095#define AT91C_US1_CSR ((AT91_REG *) 0xFFFC4014) // (US1) Channel Status Register
2096#define AT91C_US1_IDR ((AT91_REG *) 0xFFFC400C) // (US1) Interrupt Disable Register
2097#define AT91C_US1_FIDI ((AT91_REG *) 0xFFFC4040) // (US1) FI_DI_Ratio Register
2098#define AT91C_US1_BRGR ((AT91_REG *) 0xFFFC4020) // (US1) Baud Rate Generator Register
2099#define AT91C_US1_TTGR ((AT91_REG *) 0xFFFC4028) // (US1) Transmitter Time-guard Register
2100#define AT91C_US1_IF ((AT91_REG *) 0xFFFC404C) // (US1) IRDA_FILTER Register
2101#define AT91C_US1_NER ((AT91_REG *) 0xFFFC4044) // (US1) Nb Errors Register
2102#define AT91C_US1_MR ((AT91_REG *) 0xFFFC4004) // (US1) Mode Register
2103// ========== Register definition for PDC_US0 peripheral ==========
2104#define AT91C_US0_PTCR ((AT91_REG *) 0xFFFC0120) // (PDC_US0) PDC Transfer Control Register
2105#define AT91C_US0_TNPR ((AT91_REG *) 0xFFFC0118) // (PDC_US0) Transmit Next Pointer Register
2106#define AT91C_US0_RNPR ((AT91_REG *) 0xFFFC0110) // (PDC_US0) Receive Next Pointer Register
2107#define AT91C_US0_TPR ((AT91_REG *) 0xFFFC0108) // (PDC_US0) Transmit Pointer Register
2108#define AT91C_US0_RPR ((AT91_REG *) 0xFFFC0100) // (PDC_US0) Receive Pointer Register
2109#define AT91C_US0_PTSR ((AT91_REG *) 0xFFFC0124) // (PDC_US0) PDC Transfer Status Register
2110#define AT91C_US0_TNCR ((AT91_REG *) 0xFFFC011C) // (PDC_US0) Transmit Next Counter Register
2111#define AT91C_US0_RNCR ((AT91_REG *) 0xFFFC0114) // (PDC_US0) Receive Next Counter Register
2112#define AT91C_US0_TCR ((AT91_REG *) 0xFFFC010C) // (PDC_US0) Transmit Counter Register
2113#define AT91C_US0_RCR ((AT91_REG *) 0xFFFC0104) // (PDC_US0) Receive Counter Register
2114// ========== Register definition for US0 peripheral ==========
2115#define AT91C_US0_TTGR ((AT91_REG *) 0xFFFC0028) // (US0) Transmitter Time-guard Register
2116#define AT91C_US0_BRGR ((AT91_REG *) 0xFFFC0020) // (US0) Baud Rate Generator Register
2117#define AT91C_US0_RHR ((AT91_REG *) 0xFFFC0018) // (US0) Receiver Holding Register
2118#define AT91C_US0_IMR ((AT91_REG *) 0xFFFC0010) // (US0) Interrupt Mask Register
2119#define AT91C_US0_NER ((AT91_REG *) 0xFFFC0044) // (US0) Nb Errors Register
2120#define AT91C_US0_RTOR ((AT91_REG *) 0xFFFC0024) // (US0) Receiver Time-out Register
2121#define AT91C_US0_XXR ((AT91_REG *) 0xFFFC0048) // (US0) XON_XOFF Register
2122#define AT91C_US0_FIDI ((AT91_REG *) 0xFFFC0040) // (US0) FI_DI_Ratio Register
2123#define AT91C_US0_CR ((AT91_REG *) 0xFFFC0000) // (US0) Control Register
2124#define AT91C_US0_IER ((AT91_REG *) 0xFFFC0008) // (US0) Interrupt Enable Register
2125#define AT91C_US0_IF ((AT91_REG *) 0xFFFC004C) // (US0) IRDA_FILTER Register
2126#define AT91C_US0_MR ((AT91_REG *) 0xFFFC0004) // (US0) Mode Register
2127#define AT91C_US0_IDR ((AT91_REG *) 0xFFFC000C) // (US0) Interrupt Disable Register
2128#define AT91C_US0_CSR ((AT91_REG *) 0xFFFC0014) // (US0) Channel Status Register
2129#define AT91C_US0_THR ((AT91_REG *) 0xFFFC001C) // (US0) Transmitter Holding Register
2130// ========== Register definition for TWI peripheral ==========
2131#define AT91C_TWI_RHR ((AT91_REG *) 0xFFFB8030) // (TWI) Receive Holding Register
2132#define AT91C_TWI_IDR ((AT91_REG *) 0xFFFB8028) // (TWI) Interrupt Disable Register
2133#define AT91C_TWI_SR ((AT91_REG *) 0xFFFB8020) // (TWI) Status Register
2134#define AT91C_TWI_CWGR ((AT91_REG *) 0xFFFB8010) // (TWI) Clock Waveform Generator Register
2135#define AT91C_TWI_SMR ((AT91_REG *) 0xFFFB8008) // (TWI) Slave Mode Register
2136#define AT91C_TWI_CR ((AT91_REG *) 0xFFFB8000) // (TWI) Control Register
2137#define AT91C_TWI_THR ((AT91_REG *) 0xFFFB8034) // (TWI) Transmit Holding Register
2138#define AT91C_TWI_IMR ((AT91_REG *) 0xFFFB802C) // (TWI) Interrupt Mask Register
2139#define AT91C_TWI_IER ((AT91_REG *) 0xFFFB8024) // (TWI) Interrupt Enable Register
2140#define AT91C_TWI_IADR ((AT91_REG *) 0xFFFB800C) // (TWI) Internal Address Register
2141#define AT91C_TWI_MMR ((AT91_REG *) 0xFFFB8004) // (TWI) Master Mode Register
2142// ========== Register definition for PDC_MCI peripheral ==========
2143#define AT91C_MCI_PTCR ((AT91_REG *) 0xFFFB4120) // (PDC_MCI) PDC Transfer Control Register
2144#define AT91C_MCI_TNPR ((AT91_REG *) 0xFFFB4118) // (PDC_MCI) Transmit Next Pointer Register
2145#define AT91C_MCI_RNPR ((AT91_REG *) 0xFFFB4110) // (PDC_MCI) Receive Next Pointer Register
2146#define AT91C_MCI_TPR ((AT91_REG *) 0xFFFB4108) // (PDC_MCI) Transmit Pointer Register
2147#define AT91C_MCI_RPR ((AT91_REG *) 0xFFFB4100) // (PDC_MCI) Receive Pointer Register
2148#define AT91C_MCI_PTSR ((AT91_REG *) 0xFFFB4124) // (PDC_MCI) PDC Transfer Status Register
2149#define AT91C_MCI_TNCR ((AT91_REG *) 0xFFFB411C) // (PDC_MCI) Transmit Next Counter Register
2150#define AT91C_MCI_RNCR ((AT91_REG *) 0xFFFB4114) // (PDC_MCI) Receive Next Counter Register
2151#define AT91C_MCI_TCR ((AT91_REG *) 0xFFFB410C) // (PDC_MCI) Transmit Counter Register
2152#define AT91C_MCI_RCR ((AT91_REG *) 0xFFFB4104) // (PDC_MCI) Receive Counter Register
2153// ========== Register definition for MCI peripheral ==========
2154#define AT91C_MCI_IDR ((AT91_REG *) 0xFFFB4048) // (MCI) MCI Interrupt Disable Register
2155#define AT91C_MCI_SR ((AT91_REG *) 0xFFFB4040) // (MCI) MCI Status Register
2156#define AT91C_MCI_RDR ((AT91_REG *) 0xFFFB4030) // (MCI) MCI Receive Data Register
2157#define AT91C_MCI_RSPR ((AT91_REG *) 0xFFFB4020) // (MCI) MCI Response Register
2158#define AT91C_MCI_ARGR ((AT91_REG *) 0xFFFB4010) // (MCI) MCI Argument Register
2159#define AT91C_MCI_DTOR ((AT91_REG *) 0xFFFB4008) // (MCI) MCI Data Timeout Register
2160#define AT91C_MCI_CR ((AT91_REG *) 0xFFFB4000) // (MCI) MCI Control Register
2161#define AT91C_MCI_IMR ((AT91_REG *) 0xFFFB404C) // (MCI) MCI Interrupt Mask Register
2162#define AT91C_MCI_IER ((AT91_REG *) 0xFFFB4044) // (MCI) MCI Interrupt Enable Register
2163#define AT91C_MCI_TDR ((AT91_REG *) 0xFFFB4034) // (MCI) MCI Transmit Data Register
2164#define AT91C_MCI_CMDR ((AT91_REG *) 0xFFFB4014) // (MCI) MCI Command Register
2165#define AT91C_MCI_SDCR ((AT91_REG *) 0xFFFB400C) // (MCI) MCI SD Card Register
2166#define AT91C_MCI_MR ((AT91_REG *) 0xFFFB4004) // (MCI) MCI Mode Register
2167// ========== Register definition for UDP peripheral ==========
2168#define AT91C_UDP_ISR ((AT91_REG *) 0xFFFB001C) // (UDP) Interrupt Status Register
2169#define AT91C_UDP_IDR ((AT91_REG *) 0xFFFB0014) // (UDP) Interrupt Disable Register
2170#define AT91C_UDP_GLBSTATE ((AT91_REG *) 0xFFFB0004) // (UDP) Global State Register
2171#define AT91C_UDP_FDR ((AT91_REG *) 0xFFFB0050) // (UDP) Endpoint FIFO Data Register
2172#define AT91C_UDP_CSR ((AT91_REG *) 0xFFFB0030) // (UDP) Endpoint Control and Status Register
2173#define AT91C_UDP_RSTEP ((AT91_REG *) 0xFFFB0028) // (UDP) Reset Endpoint Register
2174#define AT91C_UDP_ICR ((AT91_REG *) 0xFFFB0020) // (UDP) Interrupt Clear Register
2175#define AT91C_UDP_IMR ((AT91_REG *) 0xFFFB0018) // (UDP) Interrupt Mask Register
2176#define AT91C_UDP_IER ((AT91_REG *) 0xFFFB0010) // (UDP) Interrupt Enable Register
2177#define AT91C_UDP_FADDR ((AT91_REG *) 0xFFFB0008) // (UDP) Function Address Register
2178#define AT91C_UDP_NUM ((AT91_REG *) 0xFFFB0000) // (UDP) Frame Number Register
2179// ========== Register definition for TC5 peripheral ==========
2180#define AT91C_TC5_CMR ((AT91_REG *) 0xFFFA4084) // (TC5) Channel Mode Register
2181#define AT91C_TC5_IDR ((AT91_REG *) 0xFFFA40A8) // (TC5) Interrupt Disable Register
2182#define AT91C_TC5_SR ((AT91_REG *) 0xFFFA40A0) // (TC5) Status Register
2183#define AT91C_TC5_RB ((AT91_REG *) 0xFFFA4098) // (TC5) Register B
2184#define AT91C_TC5_CV ((AT91_REG *) 0xFFFA4090) // (TC5) Counter Value
2185#define AT91C_TC5_CCR ((AT91_REG *) 0xFFFA4080) // (TC5) Channel Control Register
2186#define AT91C_TC5_IMR ((AT91_REG *) 0xFFFA40AC) // (TC5) Interrupt Mask Register
2187#define AT91C_TC5_IER ((AT91_REG *) 0xFFFA40A4) // (TC5) Interrupt Enable Register
2188#define AT91C_TC5_RC ((AT91_REG *) 0xFFFA409C) // (TC5) Register C
2189#define AT91C_TC5_RA ((AT91_REG *) 0xFFFA4094) // (TC5) Register A
2190// ========== Register definition for TC4 peripheral ==========
2191#define AT91C_TC4_IMR ((AT91_REG *) 0xFFFA406C) // (TC4) Interrupt Mask Register
2192#define AT91C_TC4_IER ((AT91_REG *) 0xFFFA4064) // (TC4) Interrupt Enable Register
2193#define AT91C_TC4_RC ((AT91_REG *) 0xFFFA405C) // (TC4) Register C
2194#define AT91C_TC4_RA ((AT91_REG *) 0xFFFA4054) // (TC4) Register A
2195#define AT91C_TC4_CMR ((AT91_REG *) 0xFFFA4044) // (TC4) Channel Mode Register
2196#define AT91C_TC4_IDR ((AT91_REG *) 0xFFFA4068) // (TC4) Interrupt Disable Register
2197#define AT91C_TC4_SR ((AT91_REG *) 0xFFFA4060) // (TC4) Status Register
2198#define AT91C_TC4_RB ((AT91_REG *) 0xFFFA4058) // (TC4) Register B
2199#define AT91C_TC4_CV ((AT91_REG *) 0xFFFA4050) // (TC4) Counter Value
2200#define AT91C_TC4_CCR ((AT91_REG *) 0xFFFA4040) // (TC4) Channel Control Register
2201// ========== Register definition for TC3 peripheral ==========
2202#define AT91C_TC3_IMR ((AT91_REG *) 0xFFFA402C) // (TC3) Interrupt Mask Register
2203#define AT91C_TC3_CV ((AT91_REG *) 0xFFFA4010) // (TC3) Counter Value
2204#define AT91C_TC3_CCR ((AT91_REG *) 0xFFFA4000) // (TC3) Channel Control Register
2205#define AT91C_TC3_IER ((AT91_REG *) 0xFFFA4024) // (TC3) Interrupt Enable Register
2206#define AT91C_TC3_CMR ((AT91_REG *) 0xFFFA4004) // (TC3) Channel Mode Register
2207#define AT91C_TC3_RA ((AT91_REG *) 0xFFFA4014) // (TC3) Register A
2208#define AT91C_TC3_RC ((AT91_REG *) 0xFFFA401C) // (TC3) Register C
2209#define AT91C_TC3_IDR ((AT91_REG *) 0xFFFA4028) // (TC3) Interrupt Disable Register
2210#define AT91C_TC3_RB ((AT91_REG *) 0xFFFA4018) // (TC3) Register B
2211#define AT91C_TC3_SR ((AT91_REG *) 0xFFFA4020) // (TC3) Status Register
2212// ========== Register definition for TCB1 peripheral ==========
2213#define AT91C_TCB1_BCR ((AT91_REG *) 0xFFFA4140) // (TCB1) TC Block Control Register
2214#define AT91C_TCB1_BMR ((AT91_REG *) 0xFFFA4144) // (TCB1) TC Block Mode Register
2215// ========== Register definition for TC2 peripheral ==========
2216#define AT91C_TC2_IMR ((AT91_REG *) 0xFFFA00AC) // (TC2) Interrupt Mask Register
2217#define AT91C_TC2_IER ((AT91_REG *) 0xFFFA00A4) // (TC2) Interrupt Enable Register
2218#define AT91C_TC2_RC ((AT91_REG *) 0xFFFA009C) // (TC2) Register C
2219#define AT91C_TC2_RA ((AT91_REG *) 0xFFFA0094) // (TC2) Register A
2220#define AT91C_TC2_CMR ((AT91_REG *) 0xFFFA0084) // (TC2) Channel Mode Register
2221#define AT91C_TC2_IDR ((AT91_REG *) 0xFFFA00A8) // (TC2) Interrupt Disable Register
2222#define AT91C_TC2_SR ((AT91_REG *) 0xFFFA00A0) // (TC2) Status Register
2223#define AT91C_TC2_RB ((AT91_REG *) 0xFFFA0098) // (TC2) Register B
2224#define AT91C_TC2_CV ((AT91_REG *) 0xFFFA0090) // (TC2) Counter Value
2225#define AT91C_TC2_CCR ((AT91_REG *) 0xFFFA0080) // (TC2) Channel Control Register
2226// ========== Register definition for TC1 peripheral ==========
2227#define AT91C_TC1_IMR ((AT91_REG *) 0xFFFA006C) // (TC1) Interrupt Mask Register
2228#define AT91C_TC1_IER ((AT91_REG *) 0xFFFA0064) // (TC1) Interrupt Enable Register
2229#define AT91C_TC1_RC ((AT91_REG *) 0xFFFA005C) // (TC1) Register C
2230#define AT91C_TC1_RA ((AT91_REG *) 0xFFFA0054) // (TC1) Register A
2231#define AT91C_TC1_CMR ((AT91_REG *) 0xFFFA0044) // (TC1) Channel Mode Register
2232#define AT91C_TC1_IDR ((AT91_REG *) 0xFFFA0068) // (TC1) Interrupt Disable Register
2233#define AT91C_TC1_SR ((AT91_REG *) 0xFFFA0060) // (TC1) Status Register
2234#define AT91C_TC1_RB ((AT91_REG *) 0xFFFA0058) // (TC1) Register B
2235#define AT91C_TC1_CV ((AT91_REG *) 0xFFFA0050) // (TC1) Counter Value
2236#define AT91C_TC1_CCR ((AT91_REG *) 0xFFFA0040) // (TC1) Channel Control Register
2237// ========== Register definition for TC0 peripheral ==========
2238#define AT91C_TC0_IMR ((AT91_REG *) 0xFFFA002C) // (TC0) Interrupt Mask Register
2239#define AT91C_TC0_IER ((AT91_REG *) 0xFFFA0024) // (TC0) Interrupt Enable Register
2240#define AT91C_TC0_RC ((AT91_REG *) 0xFFFA001C) // (TC0) Register C
2241#define AT91C_TC0_RA ((AT91_REG *) 0xFFFA0014) // (TC0) Register A
2242#define AT91C_TC0_CMR ((AT91_REG *) 0xFFFA0004) // (TC0) Channel Mode Register
2243#define AT91C_TC0_IDR ((AT91_REG *) 0xFFFA0028) // (TC0) Interrupt Disable Register
2244#define AT91C_TC0_SR ((AT91_REG *) 0xFFFA0020) // (TC0) Status Register
2245#define AT91C_TC0_RB ((AT91_REG *) 0xFFFA0018) // (TC0) Register B
2246#define AT91C_TC0_CV ((AT91_REG *) 0xFFFA0010) // (TC0) Counter Value
2247#define AT91C_TC0_CCR ((AT91_REG *) 0xFFFA0000) // (TC0) Channel Control Register
2248// ========== Register definition for TCB0 peripheral ==========
2249#define AT91C_TCB0_BMR ((AT91_REG *) 0xFFFA00C4) // (TCB0) TC Block Mode Register
2250#define AT91C_TCB0_BCR ((AT91_REG *) 0xFFFA00C0) // (TCB0) TC Block Control Register
2251// ========== Register definition for UHP peripheral ==========
2252#define AT91C_UHP_HcRhDescriptorA ((AT91_REG *) 0x00300048) // (UHP) Root Hub characteristics A
2253#define AT91C_UHP_HcRhPortStatus ((AT91_REG *) 0x00300054) // (UHP) Root Hub Port Status Register
2254#define AT91C_UHP_HcRhDescriptorB ((AT91_REG *) 0x0030004C) // (UHP) Root Hub characteristics B
2255#define AT91C_UHP_HcControl ((AT91_REG *) 0x00300004) // (UHP) Operating modes for the Host Controller
2256#define AT91C_UHP_HcInterruptStatus ((AT91_REG *) 0x0030000C) // (UHP) Interrupt Status Register
2257#define AT91C_UHP_HcRhStatus ((AT91_REG *) 0x00300050) // (UHP) Root Hub Status register
2258#define AT91C_UHP_HcRevision ((AT91_REG *) 0x00300000) // (UHP) Revision
2259#define AT91C_UHP_HcCommandStatus ((AT91_REG *) 0x00300008) // (UHP) Command & status Register
2260#define AT91C_UHP_HcInterruptEnable ((AT91_REG *) 0x00300010) // (UHP) Interrupt Enable Register
2261#define AT91C_UHP_HcHCCA ((AT91_REG *) 0x00300018) // (UHP) Pointer to the Host Controller Communication Area
2262#define AT91C_UHP_HcControlHeadED ((AT91_REG *) 0x00300020) // (UHP) First Endpoint Descriptor of the Control list
2263#define AT91C_UHP_HcInterruptDisable ((AT91_REG *) 0x00300014) // (UHP) Interrupt Disable Register
2264#define AT91C_UHP_HcPeriodCurrentED ((AT91_REG *) 0x0030001C) // (UHP) Current Isochronous or Interrupt Endpoint Descriptor
2265#define AT91C_UHP_HcControlCurrentED ((AT91_REG *) 0x00300024) // (UHP) Endpoint Control and Status Register
2266#define AT91C_UHP_HcBulkCurrentED ((AT91_REG *) 0x0030002C) // (UHP) Current endpoint of the Bulk list
2267#define AT91C_UHP_HcFmInterval ((AT91_REG *) 0x00300034) // (UHP) Bit time between 2 consecutive SOFs
2268#define AT91C_UHP_HcBulkHeadED ((AT91_REG *) 0x00300028) // (UHP) First endpoint register of the Bulk list
2269#define AT91C_UHP_HcBulkDoneHead ((AT91_REG *) 0x00300030) // (UHP) Last completed transfer descriptor
2270#define AT91C_UHP_HcFmRemaining ((AT91_REG *) 0x00300038) // (UHP) Bit time remaining in the current Frame
2271#define AT91C_UHP_HcPeriodicStart ((AT91_REG *) 0x00300040) // (UHP) Periodic Start
2272#define AT91C_UHP_HcLSThreshold ((AT91_REG *) 0x00300044) // (UHP) LS Threshold
2273#define AT91C_UHP_HcFmNumber ((AT91_REG *) 0x0030003C) // (UHP) Frame number
2274// ========== Register definition for EMAC peripheral ==========
2275#define AT91C_EMAC_RSR ((AT91_REG *) 0xFFFBC020) // (EMAC) Receive Status Register
2276#define AT91C_EMAC_MAN ((AT91_REG *) 0xFFFBC034) // (EMAC) PHY Maintenance Register
2277#define AT91C_EMAC_HSH ((AT91_REG *) 0xFFFBC090) // (EMAC) Hash Address High[63:32]
2278#define AT91C_EMAC_MCOL ((AT91_REG *) 0xFFFBC048) // (EMAC) Multiple Collision Frame Register
2279#define AT91C_EMAC_IER ((AT91_REG *) 0xFFFBC028) // (EMAC) Interrupt Enable Register
2280#define AT91C_EMAC_SA2H ((AT91_REG *) 0xFFFBC0A4) // (EMAC) Specific Address 2 High, Last 2 bytes
2281#define AT91C_EMAC_HSL ((AT91_REG *) 0xFFFBC094) // (EMAC) Hash Address Low[31:0]
2282#define AT91C_EMAC_LCOL ((AT91_REG *) 0xFFFBC05C) // (EMAC) Late Collision Register
2283#define AT91C_EMAC_OK ((AT91_REG *) 0xFFFBC04C) // (EMAC) Frames Received OK Register
2284#define AT91C_EMAC_CFG ((AT91_REG *) 0xFFFBC004) // (EMAC) Network Configuration Register
2285#define AT91C_EMAC_SA3L ((AT91_REG *) 0xFFFBC0A8) // (EMAC) Specific Address 3 Low, First 4 bytes
2286#define AT91C_EMAC_SEQE ((AT91_REG *) 0xFFFBC050) // (EMAC) Frame Check Sequence Error Register
2287#define AT91C_EMAC_ECOL ((AT91_REG *) 0xFFFBC060) // (EMAC) Excessive Collision Register
2288#define AT91C_EMAC_ELR ((AT91_REG *) 0xFFFBC070) // (EMAC) Excessive Length Error Register
2289#define AT91C_EMAC_SR ((AT91_REG *) 0xFFFBC008) // (EMAC) Network Status Register
2290#define AT91C_EMAC_RBQP ((AT91_REG *) 0xFFFBC018) // (EMAC) Receive Buffer Queue Pointer
2291#define AT91C_EMAC_CSE ((AT91_REG *) 0xFFFBC064) // (EMAC) Carrier Sense Error Register
2292#define AT91C_EMAC_RJB ((AT91_REG *) 0xFFFBC074) // (EMAC) Receive Jabber Register
2293#define AT91C_EMAC_USF ((AT91_REG *) 0xFFFBC078) // (EMAC) Undersize Frame Register
2294#define AT91C_EMAC_IDR ((AT91_REG *) 0xFFFBC02C) // (EMAC) Interrupt Disable Register
2295#define AT91C_EMAC_SA1L ((AT91_REG *) 0xFFFBC098) // (EMAC) Specific Address 1 Low, First 4 bytes
2296#define AT91C_EMAC_IMR ((AT91_REG *) 0xFFFBC030) // (EMAC) Interrupt Mask Register
2297#define AT91C_EMAC_FRA ((AT91_REG *) 0xFFFBC040) // (EMAC) Frames Transmitted OK Register
2298#define AT91C_EMAC_SA3H ((AT91_REG *) 0xFFFBC0AC) // (EMAC) Specific Address 3 High, Last 2 bytes
2299#define AT91C_EMAC_SA1H ((AT91_REG *) 0xFFFBC09C) // (EMAC) Specific Address 1 High, Last 2 bytes
2300#define AT91C_EMAC_SCOL ((AT91_REG *) 0xFFFBC044) // (EMAC) Single Collision Frame Register
2301#define AT91C_EMAC_ALE ((AT91_REG *) 0xFFFBC054) // (EMAC) Alignment Error Register
2302#define AT91C_EMAC_TAR ((AT91_REG *) 0xFFFBC00C) // (EMAC) Transmit Address Register
2303#define AT91C_EMAC_SA4L ((AT91_REG *) 0xFFFBC0B0) // (EMAC) Specific Address 4 Low, First 4 bytes
2304#define AT91C_EMAC_SA2L ((AT91_REG *) 0xFFFBC0A0) // (EMAC) Specific Address 2 Low, First 4 bytes
2305#define AT91C_EMAC_TUE ((AT91_REG *) 0xFFFBC068) // (EMAC) Transmit Underrun Error Register
2306#define AT91C_EMAC_DTE ((AT91_REG *) 0xFFFBC058) // (EMAC) Deferred Transmission Frame Register
2307#define AT91C_EMAC_TCR ((AT91_REG *) 0xFFFBC010) // (EMAC) Transmit Control Register
2308#define AT91C_EMAC_CTL ((AT91_REG *) 0xFFFBC000) // (EMAC) Network Control Register
2309#define AT91C_EMAC_SA4H ((AT91_REG *) 0xFFFBC0B4) // (EMAC) Specific Address 4 High, Last 2 bytesr
2310#define AT91C_EMAC_CDE ((AT91_REG *) 0xFFFBC06C) // (EMAC) Code Error Register
2311#define AT91C_EMAC_SQEE ((AT91_REG *) 0xFFFBC07C) // (EMAC) SQE Test Error Register
2312#define AT91C_EMAC_TSR ((AT91_REG *) 0xFFFBC014) // (EMAC) Transmit Status Register
2313#define AT91C_EMAC_DRFC ((AT91_REG *) 0xFFFBC080) // (EMAC) Discarded RX Frame Register
2314// ========== Register definition for EBI peripheral ==========
2315#define AT91C_EBI_CFGR ((AT91_REG *) 0xFFFFFF64) // (EBI) Configuration Register
2316#define AT91C_EBI_CSA ((AT91_REG *) 0xFFFFFF60) // (EBI) Chip Select Assignment Register
2317// ========== Register definition for SMC2 peripheral ==========
2318#define AT91C_SMC2_CSR ((AT91_REG *) 0xFFFFFF70) // (SMC2) SMC2 Chip Select Register
2319// ========== Register definition for SDRC peripheral ==========
2320#define AT91C_SDRC_IMR ((AT91_REG *) 0xFFFFFFAC) // (SDRC) SDRAM Controller Interrupt Mask Register
2321#define AT91C_SDRC_IER ((AT91_REG *) 0xFFFFFFA4) // (SDRC) SDRAM Controller Interrupt Enable Register
2322#define AT91C_SDRC_SRR ((AT91_REG *) 0xFFFFFF9C) // (SDRC) SDRAM Controller Self Refresh Register
2323#define AT91C_SDRC_TR ((AT91_REG *) 0xFFFFFF94) // (SDRC) SDRAM Controller Refresh Timer Register
2324#define AT91C_SDRC_ISR ((AT91_REG *) 0xFFFFFFB0) // (SDRC) SDRAM Controller Interrupt Mask Register
2325#define AT91C_SDRC_IDR ((AT91_REG *) 0xFFFFFFA8) // (SDRC) SDRAM Controller Interrupt Disable Register
2326#define AT91C_SDRC_LPR ((AT91_REG *) 0xFFFFFFA0) // (SDRC) SDRAM Controller Low Power Register
2327#define AT91C_SDRC_CR ((AT91_REG *) 0xFFFFFF98) // (SDRC) SDRAM Controller Configuration Register
2328#define AT91C_SDRC_MR ((AT91_REG *) 0xFFFFFF90) // (SDRC) SDRAM Controller Mode Register
2329// ========== Register definition for BFC peripheral ==========
2330#define AT91C_BFC_MR ((AT91_REG *) 0xFFFFFFC0) // (BFC) BFC Mode Register
2331
2332// *****************************************************************************
2333// PIO DEFINITIONS FOR AT91RM9200
2334// *****************************************************************************
2335#define AT91C_PIO_PA0 ((unsigned int) 1 << 0) // Pin Controlled by PA0
2336#define AT91C_PA0_MISO ((unsigned int) AT91C_PIO_PA0) // SPI Master In Slave
2337#define AT91C_PA0_PCK3 ((unsigned int) AT91C_PIO_PA0) // PMC Programmable Clock Output 3
2338#define AT91C_PIO_PA1 ((unsigned int) 1 << 1) // Pin Controlled by PA1
2339#define AT91C_PA1_MOSI ((unsigned int) AT91C_PIO_PA1) // SPI Master Out Slave
2340#define AT91C_PA1_PCK0 ((unsigned int) AT91C_PIO_PA1) // PMC Programmable Clock Output 0
2341#define AT91C_PIO_PA10 ((unsigned int) 1 << 10) // Pin Controlled by PA10
2342#define AT91C_PA10_ETX1 ((unsigned int) AT91C_PIO_PA10) // Ethernet MAC Transmit Data 1
2343#define AT91C_PA10_MCDB1 ((unsigned int) AT91C_PIO_PA10) // Multimedia Card B Data 1
2344#define AT91C_PIO_PA11 ((unsigned int) 1 << 11) // Pin Controlled by PA11
2345#define AT91C_PA11_ECRS_ECRSDV ((unsigned int) AT91C_PIO_PA11) // Ethernet MAC Carrier Sense/Carrier Sense and Data Valid
2346#define AT91C_PA11_MCDB2 ((unsigned int) AT91C_PIO_PA11) // Multimedia Card B Data 2
2347#define AT91C_PIO_PA12 ((unsigned int) 1 << 12) // Pin Controlled by PA12
2348#define AT91C_PA12_ERX0 ((unsigned int) AT91C_PIO_PA12) // Ethernet MAC Receive Data 0
2349#define AT91C_PA12_MCDB3 ((unsigned int) AT91C_PIO_PA12) // Multimedia Card B Data 3
2350#define AT91C_PIO_PA13 ((unsigned int) 1 << 13) // Pin Controlled by PA13
2351#define AT91C_PA13_ERX1 ((unsigned int) AT91C_PIO_PA13) // Ethernet MAC Receive Data 1
2352#define AT91C_PA13_TCLK0 ((unsigned int) AT91C_PIO_PA13) // Timer Counter 0 external clock input
2353#define AT91C_PIO_PA14 ((unsigned int) 1 << 14) // Pin Controlled by PA14
2354#define AT91C_PA14_ERXER ((unsigned int) AT91C_PIO_PA14) // Ethernet MAC Receive Error
2355#define AT91C_PA14_TCLK1 ((unsigned int) AT91C_PIO_PA14) // Timer Counter 1 external clock input
2356#define AT91C_PIO_PA15 ((unsigned int) 1 << 15) // Pin Controlled by PA15
2357#define AT91C_PA15_EMDC ((unsigned int) AT91C_PIO_PA15) // Ethernet MAC Management Data Clock
2358#define AT91C_PA15_TCLK2 ((unsigned int) AT91C_PIO_PA15) // Timer Counter 2 external clock input
2359#define AT91C_PIO_PA16 ((unsigned int) 1 << 16) // Pin Controlled by PA16
2360#define AT91C_PA16_EMDIO ((unsigned int) AT91C_PIO_PA16) // Ethernet MAC Management Data Input/Output
2361#define AT91C_PA16_IRQ6 ((unsigned int) AT91C_PIO_PA16) // AIC Interrupt input 6
2362#define AT91C_PIO_PA17 ((unsigned int) 1 << 17) // Pin Controlled by PA17
2363#define AT91C_PA17_TXD0 ((unsigned int) AT91C_PIO_PA17) // USART 0 Transmit Data
2364#define AT91C_PA17_TIOA0 ((unsigned int) AT91C_PIO_PA17) // Timer Counter 0 Multipurpose Timer I/O Pin A
2365#define AT91C_PIO_PA18 ((unsigned int) 1 << 18) // Pin Controlled by PA18
2366#define AT91C_PA18_RXD0 ((unsigned int) AT91C_PIO_PA18) // USART 0 Receive Data
2367#define AT91C_PA18_TIOB0 ((unsigned int) AT91C_PIO_PA18) // Timer Counter 0 Multipurpose Timer I/O Pin B
2368#define AT91C_PIO_PA19 ((unsigned int) 1 << 19) // Pin Controlled by PA19
2369#define AT91C_PA19_SCK0 ((unsigned int) AT91C_PIO_PA19) // USART 0 Serial Clock
2370#define AT91C_PA19_TIOA1 ((unsigned int) AT91C_PIO_PA19) // Timer Counter 1 Multipurpose Timer I/O Pin A
2371#define AT91C_PIO_PA2 ((unsigned int) 1 << 2) // Pin Controlled by PA2
2372#define AT91C_PA2_SPCK ((unsigned int) AT91C_PIO_PA2) // SPI Serial Clock
2373#define AT91C_PA2_IRQ4 ((unsigned int) AT91C_PIO_PA2) // AIC Interrupt Input 4
2374#define AT91C_PIO_PA20 ((unsigned int) 1 << 20) // Pin Controlled by PA20
2375#define AT91C_PA20_CTS0 ((unsigned int) AT91C_PIO_PA20) // USART 0 Clear To Send
2376#define AT91C_PA20_TIOB1 ((unsigned int) AT91C_PIO_PA20) // Timer Counter 1 Multipurpose Timer I/O Pin B
2377#define AT91C_PIO_PA21 ((unsigned int) 1 << 21) // Pin Controlled by PA21
2378#define AT91C_PA21_RTS0 ((unsigned int) AT91C_PIO_PA21) // Usart 0 Ready To Send
2379#define AT91C_PA21_TIOA2 ((unsigned int) AT91C_PIO_PA21) // Timer Counter 2 Multipurpose Timer I/O Pin A
2380#define AT91C_PIO_PA22 ((unsigned int) 1 << 22) // Pin Controlled by PA22
2381#define AT91C_PA22_RXD2 ((unsigned int) AT91C_PIO_PA22) // USART 2 Receive Data
2382#define AT91C_PA22_TIOB2 ((unsigned int) AT91C_PIO_PA22) // Timer Counter 2 Multipurpose Timer I/O Pin B
2383#define AT91C_PIO_PA23 ((unsigned int) 1 << 23) // Pin Controlled by PA23
2384#define AT91C_PA23_TXD2 ((unsigned int) AT91C_PIO_PA23) // USART 2 Transmit Data
2385#define AT91C_PA23_IRQ3 ((unsigned int) AT91C_PIO_PA23) // Interrupt input 3
2386#define AT91C_PIO_PA24 ((unsigned int) 1 << 24) // Pin Controlled by PA24
2387#define AT91C_PA24_SCK2 ((unsigned int) AT91C_PIO_PA24) // USART2 Serial Clock
2388#define AT91C_PA24_PCK1 ((unsigned int) AT91C_PIO_PA24) // PMC Programmable Clock Output 1
2389#define AT91C_PIO_PA25 ((unsigned int) 1 << 25) // Pin Controlled by PA25
2390#define AT91C_PA25_TWD ((unsigned int) AT91C_PIO_PA25) // TWI Two-wire Serial Data
2391#define AT91C_PA25_IRQ2 ((unsigned int) AT91C_PIO_PA25) // Interrupt input 2
2392#define AT91C_PIO_PA26 ((unsigned int) 1 << 26) // Pin Controlled by PA26
2393#define AT91C_PA26_TWCK ((unsigned int) AT91C_PIO_PA26) // TWI Two-wire Serial Clock
2394#define AT91C_PA26_IRQ1 ((unsigned int) AT91C_PIO_PA26) // Interrupt input 1
2395#define AT91C_PIO_PA27 ((unsigned int) 1 << 27) // Pin Controlled by PA27
2396#define AT91C_PA27_MCCK ((unsigned int) AT91C_PIO_PA27) // Multimedia Card Clock
2397#define AT91C_PA27_TCLK3 ((unsigned int) AT91C_PIO_PA27) // Timer Counter 3 External Clock Input
2398#define AT91C_PIO_PA28 ((unsigned int) 1 << 28) // Pin Controlled by PA28
2399#define AT91C_PA28_MCCDA ((unsigned int) AT91C_PIO_PA28) // Multimedia Card A Command
2400#define AT91C_PA28_TCLK4 ((unsigned int) AT91C_PIO_PA28) // Timer Counter 4 external Clock Input
2401#define AT91C_PIO_PA29 ((unsigned int) 1 << 29) // Pin Controlled by PA29
2402#define AT91C_PA29_MCDA0 ((unsigned int) AT91C_PIO_PA29) // Multimedia Card A Data 0
2403#define AT91C_PA29_TCLK5 ((unsigned int) AT91C_PIO_PA29) // Timer Counter 5 external clock input
2404#define AT91C_PIO_PA3 ((unsigned int) 1 << 3) // Pin Controlled by PA3
2405#define AT91C_PA3_NPCS0 ((unsigned int) AT91C_PIO_PA3) // SPI Peripheral Chip Select 0
2406#define AT91C_PA3_IRQ5 ((unsigned int) AT91C_PIO_PA3) // AIC Interrupt Input 5
2407#define AT91C_PIO_PA30 ((unsigned int) 1 << 30) // Pin Controlled by PA30
2408#define AT91C_PA30_DRXD ((unsigned int) AT91C_PIO_PA30) // DBGU Debug Receive Data
2409#define AT91C_PA30_CTS2 ((unsigned int) AT91C_PIO_PA30) // Usart 2 Clear To Send
2410#define AT91C_PIO_PA31 ((unsigned int) 1 << 31) // Pin Controlled by PA31
2411#define AT91C_PA31_DTXD ((unsigned int) AT91C_PIO_PA31) // DBGU Debug Transmit Data
2412#define AT91C_PA31_RTS2 ((unsigned int) AT91C_PIO_PA31) // USART 2 Ready To Send
2413#define AT91C_PIO_PA4 ((unsigned int) 1 << 4) // Pin Controlled by PA4
2414#define AT91C_PA4_NPCS1 ((unsigned int) AT91C_PIO_PA4) // SPI Peripheral Chip Select 1
2415#define AT91C_PA4_PCK1 ((unsigned int) AT91C_PIO_PA4) // PMC Programmable Clock Output 1
2416#define AT91C_PIO_PA5 ((unsigned int) 1 << 5) // Pin Controlled by PA5
2417#define AT91C_PA5_NPCS2 ((unsigned int) AT91C_PIO_PA5) // SPI Peripheral Chip Select 2
2418#define AT91C_PA5_TXD3 ((unsigned int) AT91C_PIO_PA5) // USART 3 Transmit Data
2419#define AT91C_PIO_PA6 ((unsigned int) 1 << 6) // Pin Controlled by PA6
2420#define AT91C_PA6_NPCS3 ((unsigned int) AT91C_PIO_PA6) // SPI Peripheral Chip Select 3
2421#define AT91C_PA6_RXD3 ((unsigned int) AT91C_PIO_PA6) // USART 3 Receive Data
2422#define AT91C_PIO_PA7 ((unsigned int) 1 << 7) // Pin Controlled by PA7
2423#define AT91C_PA7_ETXCK_EREFCK ((unsigned int) AT91C_PIO_PA7) // Ethernet MAC Transmit Clock/Reference Clock
2424#define AT91C_PA7_PCK2 ((unsigned int) AT91C_PIO_PA7) // PMC Programmable Clock 2
2425#define AT91C_PIO_PA8 ((unsigned int) 1 << 8) // Pin Controlled by PA8
2426#define AT91C_PA8_ETXEN ((unsigned int) AT91C_PIO_PA8) // Ethernet MAC Transmit Enable
2427#define AT91C_PA8_MCCDB ((unsigned int) AT91C_PIO_PA8) // Multimedia Card B Command
2428#define AT91C_PIO_PA9 ((unsigned int) 1 << 9) // Pin Controlled by PA9
2429#define AT91C_PA9_ETX0 ((unsigned int) AT91C_PIO_PA9) // Ethernet MAC Transmit Data 0
2430#define AT91C_PA9_MCDB0 ((unsigned int) AT91C_PIO_PA9) // Multimedia Card B Data 0
2431#define AT91C_PIO_PB0 ((unsigned int) 1 << 0) // Pin Controlled by PB0
2432#define AT91C_PB0_TF0 ((unsigned int) AT91C_PIO_PB0) // SSC Transmit Frame Sync 0
2433#define AT91C_PB0_TIOB3 ((unsigned int) AT91C_PIO_PB0) // Timer Counter 3 Multipurpose Timer I/O Pin B
2434#define AT91C_PIO_PB1 ((unsigned int) 1 << 1) // Pin Controlled by PB1
2435#define AT91C_PB1_TK0 ((unsigned int) AT91C_PIO_PB1) // SSC Transmit Clock 0
2436#define AT91C_PB1_CTS3 ((unsigned int) AT91C_PIO_PB1) // USART 3 Clear To Send
2437#define AT91C_PIO_PB10 ((unsigned int) 1 << 10) // Pin Controlled by PB10
2438#define AT91C_PB10_RK1 ((unsigned int) AT91C_PIO_PB10) // SSC Receive Clock 1
2439#define AT91C_PB10_TIOA5 ((unsigned int) AT91C_PIO_PB10) // Timer Counter 5 Multipurpose Timer I/O Pin A
2440#define AT91C_PIO_PB11 ((unsigned int) 1 << 11) // Pin Controlled by PB11
2441#define AT91C_PB11_RF1 ((unsigned int) AT91C_PIO_PB11) // SSC Receive Frame Sync 1
2442#define AT91C_PB11_TIOB5 ((unsigned int) AT91C_PIO_PB11) // Timer Counter 5 Multipurpose Timer I/O Pin B
2443#define AT91C_PIO_PB12 ((unsigned int) 1 << 12) // Pin Controlled by PB12
2444#define AT91C_PB12_TF2 ((unsigned int) AT91C_PIO_PB12) // SSC Transmit Frame Sync 2
2445#define AT91C_PB12_ETX2 ((unsigned int) AT91C_PIO_PB12) // Ethernet MAC Transmit Data 2
2446#define AT91C_PIO_PB13 ((unsigned int) 1 << 13) // Pin Controlled by PB13
2447#define AT91C_PB13_TK2 ((unsigned int) AT91C_PIO_PB13) // SSC Transmit Clock 2
2448#define AT91C_PB13_ETX3 ((unsigned int) AT91C_PIO_PB13) // Ethernet MAC Transmit Data 3
2449#define AT91C_PIO_PB14 ((unsigned int) 1 << 14) // Pin Controlled by PB14
2450#define AT91C_PB14_TD2 ((unsigned int) AT91C_PIO_PB14) // SSC Transmit Data 2
2451#define AT91C_PB14_ETXER ((unsigned int) AT91C_PIO_PB14) // Ethernet MAC Transmikt Coding Error
2452#define AT91C_PIO_PB15 ((unsigned int) 1 << 15) // Pin Controlled by PB15
2453#define AT91C_PB15_RD2 ((unsigned int) AT91C_PIO_PB15) // SSC Receive Data 2
2454#define AT91C_PB15_ERX2 ((unsigned int) AT91C_PIO_PB15) // Ethernet MAC Receive Data 2
2455#define AT91C_PIO_PB16 ((unsigned int) 1 << 16) // Pin Controlled by PB16
2456#define AT91C_PB16_RK2 ((unsigned int) AT91C_PIO_PB16) // SSC Receive Clock 2
2457#define AT91C_PB16_ERX3 ((unsigned int) AT91C_PIO_PB16) // Ethernet MAC Receive Data 3
2458#define AT91C_PIO_PB17 ((unsigned int) 1 << 17) // Pin Controlled by PB17
2459#define AT91C_PB17_RF2 ((unsigned int) AT91C_PIO_PB17) // SSC Receive Frame Sync 2
2460#define AT91C_PB17_ERXDV ((unsigned int) AT91C_PIO_PB17) // Ethernet MAC Receive Data Valid
2461#define AT91C_PIO_PB18 ((unsigned int) 1 << 18) // Pin Controlled by PB18
2462#define AT91C_PB18_RI1 ((unsigned int) AT91C_PIO_PB18) // USART 1 Ring Indicator
2463#define AT91C_PB18_ECOL ((unsigned int) AT91C_PIO_PB18) // Ethernet MAC Collision Detected
2464#define AT91C_PIO_PB19 ((unsigned int) 1 << 19) // Pin Controlled by PB19
2465#define AT91C_PB19_DTR1 ((unsigned int) AT91C_PIO_PB19) // USART 1 Data Terminal ready
2466#define AT91C_PB19_ERXCK ((unsigned int) AT91C_PIO_PB19) // Ethernet MAC Receive Clock
2467#define AT91C_PIO_PB2 ((unsigned int) 1 << 2) // Pin Controlled by PB2
2468#define AT91C_PB2_TD0 ((unsigned int) AT91C_PIO_PB2) // SSC Transmit data
2469#define AT91C_PB2_SCK3 ((unsigned int) AT91C_PIO_PB2) // USART 3 Serial Clock
2470#define AT91C_PIO_PB20 ((unsigned int) 1 << 20) // Pin Controlled by PB20
2471#define AT91C_PB20_TXD1 ((unsigned int) AT91C_PIO_PB20) // USART 1 Transmit Data
2472#define AT91C_PIO_PB21 ((unsigned int) 1 << 21) // Pin Controlled by PB21
2473#define AT91C_PB21_RXD1 ((unsigned int) AT91C_PIO_PB21) // USART 1 Receive Data
2474#define AT91C_PIO_PB22 ((unsigned int) 1 << 22) // Pin Controlled by PB22
2475#define AT91C_PB22_SCK1 ((unsigned int) AT91C_PIO_PB22) // USART1 Serial Clock
2476#define AT91C_PIO_PB23 ((unsigned int) 1 << 23) // Pin Controlled by PB23
2477#define AT91C_PB23_DCD1 ((unsigned int) AT91C_PIO_PB23) // USART 1 Data Carrier Detect
2478#define AT91C_PIO_PB24 ((unsigned int) 1 << 24) // Pin Controlled by PB24
2479#define AT91C_PB24_CTS1 ((unsigned int) AT91C_PIO_PB24) // USART 1 Clear To Send
2480#define AT91C_PIO_PB25 ((unsigned int) 1 << 25) // Pin Controlled by PB25
2481#define AT91C_PB25_DSR1 ((unsigned int) AT91C_PIO_PB25) // USART 1 Data Set ready
2482#define AT91C_PB25_EF100 ((unsigned int) AT91C_PIO_PB25) // Ethernet MAC Force 100 Mbits/sec
2483#define AT91C_PIO_PB26 ((unsigned int) 1 << 26) // Pin Controlled by PB26
2484#define AT91C_PB26_RTS1 ((unsigned int) AT91C_PIO_PB26) // Usart 0 Ready To Send
2485#define AT91C_PIO_PB27 ((unsigned int) 1 << 27) // Pin Controlled by PB27
2486#define AT91C_PB27_PCK0 ((unsigned int) AT91C_PIO_PB27) // PMC Programmable Clock Output 0
2487#define AT91C_PIO_PB28 ((unsigned int) 1 << 28) // Pin Controlled by PB28
2488#define AT91C_PB28_FIQ ((unsigned int) AT91C_PIO_PB28) // AIC Fast Interrupt Input
2489#define AT91C_PIO_PB29 ((unsigned int) 1 << 29) // Pin Controlled by PB29
2490#define AT91C_PB29_IRQ0 ((unsigned int) AT91C_PIO_PB29) // Interrupt input 0
2491#define AT91C_PIO_PB3 ((unsigned int) 1 << 3) // Pin Controlled by PB3
2492#define AT91C_PB3_RD0 ((unsigned int) AT91C_PIO_PB3) // SSC Receive Data
2493#define AT91C_PB3_MCDA1 ((unsigned int) AT91C_PIO_PB3) // Multimedia Card A Data 1
2494#define AT91C_PIO_PB4 ((unsigned int) 1 << 4) // Pin Controlled by PB4
2495#define AT91C_PB4_RK0 ((unsigned int) AT91C_PIO_PB4) // SSC Receive Clock
2496#define AT91C_PB4_MCDA2 ((unsigned int) AT91C_PIO_PB4) // Multimedia Card A Data 2
2497#define AT91C_PIO_PB5 ((unsigned int) 1 << 5) // Pin Controlled by PB5
2498#define AT91C_PB5_RF0 ((unsigned int) AT91C_PIO_PB5) // SSC Receive Frame Sync 0
2499#define AT91C_PB5_MCDA3 ((unsigned int) AT91C_PIO_PB5) // Multimedia Card A Data 3
2500#define AT91C_PIO_PB6 ((unsigned int) 1 << 6) // Pin Controlled by PB6
2501#define AT91C_PB6_TF1 ((unsigned int) AT91C_PIO_PB6) // SSC Transmit Frame Sync 1
2502#define AT91C_PB6_TIOA3 ((unsigned int) AT91C_PIO_PB6) // Timer Counter 4 Multipurpose Timer I/O Pin A
2503#define AT91C_PIO_PB7 ((unsigned int) 1 << 7) // Pin Controlled by PB7
2504#define AT91C_PB7_TK1 ((unsigned int) AT91C_PIO_PB7) // SSC Transmit Clock 1
2505#define AT91C_PB7_TIOB3 ((unsigned int) AT91C_PIO_PB7) // Timer Counter 3 Multipurpose Timer I/O Pin B
2506#define AT91C_PIO_PB8 ((unsigned int) 1 << 8) // Pin Controlled by PB8
2507#define AT91C_PB8_TD1 ((unsigned int) AT91C_PIO_PB8) // SSC Transmit Data 1
2508#define AT91C_PB8_TIOA4 ((unsigned int) AT91C_PIO_PB8) // Timer Counter 4 Multipurpose Timer I/O Pin A
2509#define AT91C_PIO_PB9 ((unsigned int) 1 << 9) // Pin Controlled by PB9
2510#define AT91C_PB9_RD1 ((unsigned int) AT91C_PIO_PB9) // SSC Receive Data 1
2511#define AT91C_PB9_TIOB4 ((unsigned int) AT91C_PIO_PB9) // Timer Counter 4 Multipurpose Timer I/O Pin B
2512#define AT91C_PIO_PC0 ((unsigned int) 1 << 0) // Pin Controlled by PC0
2513#define AT91C_PC0_BFCK ((unsigned int) AT91C_PIO_PC0) // Burst Flash Clock
2514#define AT91C_PIO_PC1 ((unsigned int) 1 << 1) // Pin Controlled by PC1
2515#define AT91C_PC1_BFRDY_SMOE ((unsigned int) AT91C_PIO_PC1) // Burst Flash Ready
2516#define AT91C_PIO_PC10 ((unsigned int) 1 << 10) // Pin Controlled by PC10
2517#define AT91C_PC10_NCS4_CFCS ((unsigned int) AT91C_PIO_PC10) // Compact Flash Chip Select
2518#define AT91C_PIO_PC11 ((unsigned int) 1 << 11) // Pin Controlled by PC11
2519#define AT91C_PC11_NCS5_CFCE1 ((unsigned int) AT91C_PIO_PC11) // Chip Select 5 / Compact Flash Chip Enable 1
2520#define AT91C_PIO_PC12 ((unsigned int) 1 << 12) // Pin Controlled by PC12
2521#define AT91C_PC12_NCS6_CFCE2 ((unsigned int) AT91C_PIO_PC12) // Chip Select 6 / Compact Flash Chip Enable 2
2522#define AT91C_PIO_PC13 ((unsigned int) 1 << 13) // Pin Controlled by PC13
2523#define AT91C_PC13_NCS7 ((unsigned int) AT91C_PIO_PC13) // Chip Select 7
2524#define AT91C_PIO_PC14 ((unsigned int) 1 << 14) // Pin Controlled by PC14
2525#define AT91C_PIO_PC15 ((unsigned int) 1 << 15) // Pin Controlled by PC15
2526#define AT91C_PIO_PC16 ((unsigned int) 1 << 16) // Pin Controlled by PC16
2527#define AT91C_PC16_D16 ((unsigned int) AT91C_PIO_PC16) // Data Bus [16]
2528#define AT91C_PIO_PC17 ((unsigned int) 1 << 17) // Pin Controlled by PC17
2529#define AT91C_PC17_D17 ((unsigned int) AT91C_PIO_PC17) // Data Bus [17]
2530#define AT91C_PIO_PC18 ((unsigned int) 1 << 18) // Pin Controlled by PC18
2531#define AT91C_PC18_D18 ((unsigned int) AT91C_PIO_PC18) // Data Bus [18]
2532#define AT91C_PIO_PC19 ((unsigned int) 1 << 19) // Pin Controlled by PC19
2533#define AT91C_PC19_D19 ((unsigned int) AT91C_PIO_PC19) // Data Bus [19]
2534#define AT91C_PIO_PC2 ((unsigned int) 1 << 2) // Pin Controlled by PC2
2535#define AT91C_PC2_BFAVD ((unsigned int) AT91C_PIO_PC2) // Burst Flash Address Valid
2536#define AT91C_PIO_PC20 ((unsigned int) 1 << 20) // Pin Controlled by PC20
2537#define AT91C_PC20_D20 ((unsigned int) AT91C_PIO_PC20) // Data Bus [20]
2538#define AT91C_PIO_PC21 ((unsigned int) 1 << 21) // Pin Controlled by PC21
2539#define AT91C_PC21_D21 ((unsigned int) AT91C_PIO_PC21) // Data Bus [21]
2540#define AT91C_PIO_PC22 ((unsigned int) 1 << 22) // Pin Controlled by PC22
2541#define AT91C_PC22_D22 ((unsigned int) AT91C_PIO_PC22) // Data Bus [22]
2542#define AT91C_PIO_PC23 ((unsigned int) 1 << 23) // Pin Controlled by PC23
2543#define AT91C_PC23_D23 ((unsigned int) AT91C_PIO_PC23) // Data Bus [23]
2544#define AT91C_PIO_PC24 ((unsigned int) 1 << 24) // Pin Controlled by PC24
2545#define AT91C_PC24_D24 ((unsigned int) AT91C_PIO_PC24) // Data Bus [24]
2546#define AT91C_PIO_PC25 ((unsigned int) 1 << 25) // Pin Controlled by PC25
2547#define AT91C_PC25_D25 ((unsigned int) AT91C_PIO_PC25) // Data Bus [25]
2548#define AT91C_PIO_PC26 ((unsigned int) 1 << 26) // Pin Controlled by PC26
2549#define AT91C_PC26_D26 ((unsigned int) AT91C_PIO_PC26) // Data Bus [26]
2550#define AT91C_PIO_PC27 ((unsigned int) 1 << 27) // Pin Controlled by PC27
2551#define AT91C_PC27_D27 ((unsigned int) AT91C_PIO_PC27) // Data Bus [27]
2552#define AT91C_PIO_PC28 ((unsigned int) 1 << 28) // Pin Controlled by PC28
2553#define AT91C_PC28_D28 ((unsigned int) AT91C_PIO_PC28) // Data Bus [28]
2554#define AT91C_PIO_PC29 ((unsigned int) 1 << 29) // Pin Controlled by PC29
2555#define AT91C_PC29_D29 ((unsigned int) AT91C_PIO_PC29) // Data Bus [29]
2556#define AT91C_PIO_PC3 ((unsigned int) 1 << 3) // Pin Controlled by PC3
2557#define AT91C_PC3_BFBAA_SMWE ((unsigned int) AT91C_PIO_PC3) // Burst Flash Address Advance / SmartMedia Write Enable
2558#define AT91C_PIO_PC30 ((unsigned int) 1 << 30) // Pin Controlled by PC30
2559#define AT91C_PC30_D30 ((unsigned int) AT91C_PIO_PC30) // Data Bus [30]
2560#define AT91C_PIO_PC31 ((unsigned int) 1 << 31) // Pin Controlled by PC31
2561#define AT91C_PC31_D31 ((unsigned int) AT91C_PIO_PC31) // Data Bus [31]
2562#define AT91C_PIO_PC4 ((unsigned int) 1 << 4) // Pin Controlled by PC4
2563#define AT91C_PC4_BFOE ((unsigned int) AT91C_PIO_PC4) // Burst Flash Output Enable
2564#define AT91C_PIO_PC5 ((unsigned int) 1 << 5) // Pin Controlled by PC5
2565#define AT91C_PC5_BFWE ((unsigned int) AT91C_PIO_PC5) // Burst Flash Write Enable
2566#define AT91C_PIO_PC6 ((unsigned int) 1 << 6) // Pin Controlled by PC6
2567#define AT91C_PC6_NWAIT ((unsigned int) AT91C_PIO_PC6) // NWAIT
2568#define AT91C_PIO_PC7 ((unsigned int) 1 << 7) // Pin Controlled by PC7
2569#define AT91C_PC7_A23 ((unsigned int) AT91C_PIO_PC7) // Address Bus[23]
2570#define AT91C_PIO_PC8 ((unsigned int) 1 << 8) // Pin Controlled by PC8
2571#define AT91C_PC8_A24 ((unsigned int) AT91C_PIO_PC8) // Address Bus[24]
2572#define AT91C_PIO_PC9 ((unsigned int) 1 << 9) // Pin Controlled by PC9
2573#define AT91C_PC9_A25_CFRNW ((unsigned int) AT91C_PIO_PC9) // Address Bus[25] / Compact Flash Read Not Write
2574#define AT91C_PIO_PD0 ((unsigned int) 1 << 0) // Pin Controlled by PD0
2575#define AT91C_PD0_ETX0 ((unsigned int) AT91C_PIO_PD0) // Ethernet MAC Transmit Data 0
2576#define AT91C_PIO_PD1 ((unsigned int) 1 << 1) // Pin Controlled by PD1
2577#define AT91C_PD1_ETX1 ((unsigned int) AT91C_PIO_PD1) // Ethernet MAC Transmit Data 1
2578#define AT91C_PIO_PD10 ((unsigned int) 1 << 10) // Pin Controlled by PD10
2579#define AT91C_PD10_PCK3 ((unsigned int) AT91C_PIO_PD10) // PMC Programmable Clock Output 3
2580#define AT91C_PD10_TPS1 ((unsigned int) AT91C_PIO_PD10) // ETM ARM9 pipeline status 1
2581#define AT91C_PIO_PD11 ((unsigned int) 1 << 11) // Pin Controlled by PD11
2582#define AT91C_PD11_ ((unsigned int) AT91C_PIO_PD11) //
2583#define AT91C_PD11_TPS2 ((unsigned int) AT91C_PIO_PD11) // ETM ARM9 pipeline status 2
2584#define AT91C_PIO_PD12 ((unsigned int) 1 << 12) // Pin Controlled by PD12
2585#define AT91C_PD12_ ((unsigned int) AT91C_PIO_PD12) //
2586#define AT91C_PD12_TPK0 ((unsigned int) AT91C_PIO_PD12) // ETM Trace Packet 0
2587#define AT91C_PIO_PD13 ((unsigned int) 1 << 13) // Pin Controlled by PD13
2588#define AT91C_PD13_ ((unsigned int) AT91C_PIO_PD13) //
2589#define AT91C_PD13_TPK1 ((unsigned int) AT91C_PIO_PD13) // ETM Trace Packet 1
2590#define AT91C_PIO_PD14 ((unsigned int) 1 << 14) // Pin Controlled by PD14
2591#define AT91C_PD14_ ((unsigned int) AT91C_PIO_PD14) //
2592#define AT91C_PD14_TPK2 ((unsigned int) AT91C_PIO_PD14) // ETM Trace Packet 2
2593#define AT91C_PIO_PD15 ((unsigned int) 1 << 15) // Pin Controlled by PD15
2594#define AT91C_PD15_TD0 ((unsigned int) AT91C_PIO_PD15) // SSC Transmit data
2595#define AT91C_PD15_TPK3 ((unsigned int) AT91C_PIO_PD15) // ETM Trace Packet 3
2596#define AT91C_PIO_PD16 ((unsigned int) 1 << 16) // Pin Controlled by PD16
2597#define AT91C_PD16_TD1 ((unsigned int) AT91C_PIO_PD16) // SSC Transmit Data 1
2598#define AT91C_PD16_TPK4 ((unsigned int) AT91C_PIO_PD16) // ETM Trace Packet 4
2599#define AT91C_PIO_PD17 ((unsigned int) 1 << 17) // Pin Controlled by PD17
2600#define AT91C_PD17_TD2 ((unsigned int) AT91C_PIO_PD17) // SSC Transmit Data 2
2601#define AT91C_PD17_TPK5 ((unsigned int) AT91C_PIO_PD17) // ETM Trace Packet 5
2602#define AT91C_PIO_PD18 ((unsigned int) 1 << 18) // Pin Controlled by PD18
2603#define AT91C_PD18_NPCS1 ((unsigned int) AT91C_PIO_PD18) // SPI Peripheral Chip Select 1
2604#define AT91C_PD18_TPK6 ((unsigned int) AT91C_PIO_PD18) // ETM Trace Packet 6
2605#define AT91C_PIO_PD19 ((unsigned int) 1 << 19) // Pin Controlled by PD19
2606#define AT91C_PD19_NPCS2 ((unsigned int) AT91C_PIO_PD19) // SPI Peripheral Chip Select 2
2607#define AT91C_PD19_TPK7 ((unsigned int) AT91C_PIO_PD19) // ETM Trace Packet 7
2608#define AT91C_PIO_PD2 ((unsigned int) 1 << 2) // Pin Controlled by PD2
2609#define AT91C_PD2_ETX2 ((unsigned int) AT91C_PIO_PD2) // Ethernet MAC Transmit Data 2
2610#define AT91C_PIO_PD20 ((unsigned int) 1 << 20) // Pin Controlled by PD20
2611#define AT91C_PD20_NPCS3 ((unsigned int) AT91C_PIO_PD20) // SPI Peripheral Chip Select 3
2612#define AT91C_PD20_TPK8 ((unsigned int) AT91C_PIO_PD20) // ETM Trace Packet 8
2613#define AT91C_PIO_PD21 ((unsigned int) 1 << 21) // Pin Controlled by PD21
2614#define AT91C_PD21_RTS0 ((unsigned int) AT91C_PIO_PD21) // Usart 0 Ready To Send
2615#define AT91C_PD21_TPK9 ((unsigned int) AT91C_PIO_PD21) // ETM Trace Packet 9
2616#define AT91C_PIO_PD22 ((unsigned int) 1 << 22) // Pin Controlled by PD22
2617#define AT91C_PD22_RTS1 ((unsigned int) AT91C_PIO_PD22) // Usart 0 Ready To Send
2618#define AT91C_PD22_TPK10 ((unsigned int) AT91C_PIO_PD22) // ETM Trace Packet 10
2619#define AT91C_PIO_PD23 ((unsigned int) 1 << 23) // Pin Controlled by PD23
2620#define AT91C_PD23_RTS2 ((unsigned int) AT91C_PIO_PD23) // USART 2 Ready To Send
2621#define AT91C_PD23_TPK11 ((unsigned int) AT91C_PIO_PD23) // ETM Trace Packet 11
2622#define AT91C_PIO_PD24 ((unsigned int) 1 << 24) // Pin Controlled by PD24
2623#define AT91C_PD24_RTS3 ((unsigned int) AT91C_PIO_PD24) // USART 3 Ready To Send
2624#define AT91C_PD24_TPK12 ((unsigned int) AT91C_PIO_PD24) // ETM Trace Packet 12
2625#define AT91C_PIO_PD25 ((unsigned int) 1 << 25) // Pin Controlled by PD25
2626#define AT91C_PD25_DTR1 ((unsigned int) AT91C_PIO_PD25) // USART 1 Data Terminal ready
2627#define AT91C_PD25_TPK13 ((unsigned int) AT91C_PIO_PD25) // ETM Trace Packet 13
2628#define AT91C_PIO_PD26 ((unsigned int) 1 << 26) // Pin Controlled by PD26
2629#define AT91C_PD26_TPK14 ((unsigned int) AT91C_PIO_PD26) // ETM Trace Packet 14
2630#define AT91C_PIO_PD27 ((unsigned int) 1 << 27) // Pin Controlled by PD27
2631#define AT91C_PD27_TPK15 ((unsigned int) AT91C_PIO_PD27) // ETM Trace Packet 15
2632#define AT91C_PIO_PD3 ((unsigned int) 1 << 3) // Pin Controlled by PD3
2633#define AT91C_PD3_ETX3 ((unsigned int) AT91C_PIO_PD3) // Ethernet MAC Transmit Data 3
2634#define AT91C_PIO_PD4 ((unsigned int) 1 << 4) // Pin Controlled by PD4
2635#define AT91C_PD4_ETXEN ((unsigned int) AT91C_PIO_PD4) // Ethernet MAC Transmit Enable
2636#define AT91C_PIO_PD5 ((unsigned int) 1 << 5) // Pin Controlled by PD5
2637#define AT91C_PD5_ETXER ((unsigned int) AT91C_PIO_PD5) // Ethernet MAC Transmikt Coding Error
2638#define AT91C_PIO_PD6 ((unsigned int) 1 << 6) // Pin Controlled by PD6
2639#define AT91C_PD6_DTXD ((unsigned int) AT91C_PIO_PD6) // DBGU Debug Transmit Data
2640#define AT91C_PIO_PD7 ((unsigned int) 1 << 7) // Pin Controlled by PD7
2641#define AT91C_PD7_PCK0 ((unsigned int) AT91C_PIO_PD7) // PMC Programmable Clock Output 0
2642#define AT91C_PD7_TSYNC ((unsigned int) AT91C_PIO_PD7) // ETM Synchronization signal
2643#define AT91C_PIO_PD8 ((unsigned int) 1 << 8) // Pin Controlled by PD8
2644#define AT91C_PD8_PCK1 ((unsigned int) AT91C_PIO_PD8) // PMC Programmable Clock Output 1
2645#define AT91C_PD8_TCLK ((unsigned int) AT91C_PIO_PD8) // ETM Trace Clock signal
2646#define AT91C_PIO_PD9 ((unsigned int) 1 << 9) // Pin Controlled by PD9
2647#define AT91C_PD9_PCK2 ((unsigned int) AT91C_PIO_PD9) // PMC Programmable Clock 2
2648#define AT91C_PD9_TPS0 ((unsigned int) AT91C_PIO_PD9) // ETM ARM9 pipeline status 0
2649
2650// *****************************************************************************
2651// PERIPHERAL ID DEFINITIONS FOR AT91RM9200
2652// *****************************************************************************
2653#define AT91C_ID_FIQ ((unsigned int) 0) // Advanced Interrupt Controller (FIQ)
2654#define AT91C_ID_SYS ((unsigned int) 1) // System Peripheral
2655#define AT91C_ID_PIOA ((unsigned int) 2) // Parallel IO Controller A
2656#define AT91C_ID_PIOB ((unsigned int) 3) // Parallel IO Controller B
2657#define AT91C_ID_PIOC ((unsigned int) 4) // Parallel IO Controller C
2658#define AT91C_ID_PIOD ((unsigned int) 5) // Parallel IO Controller D
2659#define AT91C_ID_US0 ((unsigned int) 6) // USART 0
2660#define AT91C_ID_US1 ((unsigned int) 7) // USART 1
2661#define AT91C_ID_US2 ((unsigned int) 8) // USART 2
2662#define AT91C_ID_US3 ((unsigned int) 9) // USART 3
2663#define AT91C_ID_MCI ((unsigned int) 10) // Multimedia Card Interface
2664#define AT91C_ID_UDP ((unsigned int) 11) // USB Device Port
2665#define AT91C_ID_TWI ((unsigned int) 12) // Two-Wire Interface
2666#define AT91C_ID_SPI ((unsigned int) 13) // Serial Peripheral Interface
2667#define AT91C_ID_SSC0 ((unsigned int) 14) // Serial Synchronous Controller 0
2668#define AT91C_ID_SSC1 ((unsigned int) 15) // Serial Synchronous Controller 1
2669#define AT91C_ID_SSC2 ((unsigned int) 16) // Serial Synchronous Controller 2
2670#define AT91C_ID_TC0 ((unsigned int) 17) // Timer Counter 0
2671#define AT91C_ID_TC1 ((unsigned int) 18) // Timer Counter 1
2672#define AT91C_ID_TC2 ((unsigned int) 19) // Timer Counter 2
2673#define AT91C_ID_TC3 ((unsigned int) 20) // Timer Counter 3
2674#define AT91C_ID_TC4 ((unsigned int) 21) // Timer Counter 4
2675#define AT91C_ID_TC5 ((unsigned int) 22) // Timer Counter 5
2676#define AT91C_ID_UHP ((unsigned int) 23) // USB Host port
2677#define AT91C_ID_EMAC ((unsigned int) 24) // Ethernet MAC
2678#define AT91C_ID_IRQ0 ((unsigned int) 25) // Advanced Interrupt Controller (IRQ0)
2679#define AT91C_ID_IRQ1 ((unsigned int) 26) // Advanced Interrupt Controller (IRQ1)
2680#define AT91C_ID_IRQ2 ((unsigned int) 27) // Advanced Interrupt Controller (IRQ2)
2681#define AT91C_ID_IRQ3 ((unsigned int) 28) // Advanced Interrupt Controller (IRQ3)
2682#define AT91C_ID_IRQ4 ((unsigned int) 29) // Advanced Interrupt Controller (IRQ4)
2683#define AT91C_ID_IRQ5 ((unsigned int) 30) // Advanced Interrupt Controller (IRQ5)
2684#define AT91C_ID_IRQ6 ((unsigned int) 31) // Advanced Interrupt Controller (IRQ6)
2685
2686// *****************************************************************************
2687// BASE ADDRESS DEFINITIONS FOR AT91RM9200
2688// *****************************************************************************
2689#define AT91C_BASE_SYS ((AT91PS_SYS) 0xFFFFF000) // (SYS) Base Address
2690#define AT91C_BASE_MC ((AT91PS_MC) 0xFFFFFF00) // (MC) Base Address
2691#define AT91C_BASE_RTC ((AT91PS_RTC) 0xFFFFFE00) // (RTC) Base Address
2692#define AT91C_BASE_ST ((AT91PS_ST) 0xFFFFFD00) // (ST) Base Address
2693#define AT91C_BASE_PMC ((AT91PS_PMC) 0xFFFFFC00) // (PMC) Base Address
2694#define AT91C_BASE_CKGR ((AT91PS_CKGR) 0xFFFFFC20) // (CKGR) Base Address
2695#define AT91C_BASE_PIOD ((AT91PS_PIO) 0xFFFFFA00) // (PIOD) Base Address
2696#define AT91C_BASE_PIOC ((AT91PS_PIO) 0xFFFFF800) // (PIOC) Base Address
2697#define AT91C_BASE_PIOB ((AT91PS_PIO) 0xFFFFF600) // (PIOB) Base Address
2698#define AT91C_BASE_PIOA ((AT91PS_PIO) 0xFFFFF400) // (PIOA) Base Address
2699#define AT91C_BASE_DBGU ((AT91PS_DBGU) 0xFFFFF200) // (DBGU) Base Address
2700#define AT91C_BASE_PDC_DBGU ((AT91PS_PDC) 0xFFFFF300) // (PDC_DBGU) Base Address
2701#define AT91C_BASE_AIC ((AT91PS_AIC) 0xFFFFF000) // (AIC) Base Address
2702#define AT91C_BASE_PDC_SPI ((AT91PS_PDC) 0xFFFE0100) // (PDC_SPI) Base Address
2703#define AT91C_BASE_SPI ((AT91PS_SPI) 0xFFFE0000) // (SPI) Base Address
2704#define AT91C_BASE_PDC_SSC2 ((AT91PS_PDC) 0xFFFD8100) // (PDC_SSC2) Base Address
2705#define AT91C_BASE_SSC2 ((AT91PS_SSC) 0xFFFD8000) // (SSC2) Base Address
2706#define AT91C_BASE_PDC_SSC1 ((AT91PS_PDC) 0xFFFD4100) // (PDC_SSC1) Base Address
2707#define AT91C_BASE_SSC1 ((AT91PS_SSC) 0xFFFD4000) // (SSC1) Base Address
2708#define AT91C_BASE_PDC_SSC0 ((AT91PS_PDC) 0xFFFD0100) // (PDC_SSC0) Base Address
2709#define AT91C_BASE_SSC0 ((AT91PS_SSC) 0xFFFD0000) // (SSC0) Base Address
2710#define AT91C_BASE_PDC_US3 ((AT91PS_PDC) 0xFFFCC100) // (PDC_US3) Base Address
2711#define AT91C_BASE_US3 ((AT91PS_USART) 0xFFFCC000) // (US3) Base Address
2712#define AT91C_BASE_PDC_US2 ((AT91PS_PDC) 0xFFFC8100) // (PDC_US2) Base Address
2713#define AT91C_BASE_US2 ((AT91PS_USART) 0xFFFC8000) // (US2) Base Address
2714#define AT91C_BASE_PDC_US1 ((AT91PS_PDC) 0xFFFC4100) // (PDC_US1) Base Address
2715#define AT91C_BASE_US1 ((AT91PS_USART) 0xFFFC4000) // (US1) Base Address
2716#define AT91C_BASE_PDC_US0 ((AT91PS_PDC) 0xFFFC0100) // (PDC_US0) Base Address
2717#define AT91C_BASE_US0 ((AT91PS_USART) 0xFFFC0000) // (US0) Base Address
2718#define AT91C_BASE_TWI ((AT91PS_TWI) 0xFFFB8000) // (TWI) Base Address
2719#define AT91C_BASE_PDC_MCI ((AT91PS_PDC) 0xFFFB4100) // (PDC_MCI) Base Address
2720#define AT91C_BASE_MCI ((AT91PS_MCI) 0xFFFB4000) // (MCI) Base Address
2721#define AT91C_BASE_UDP ((AT91PS_UDP) 0xFFFB0000) // (UDP) Base Address
2722#define AT91C_BASE_TC5 ((AT91PS_TC) 0xFFFA4080) // (TC5) Base Address
2723#define AT91C_BASE_TC4 ((AT91PS_TC) 0xFFFA4040) // (TC4) Base Address
2724#define AT91C_BASE_TC3 ((AT91PS_TC) 0xFFFA4000) // (TC3) Base Address
2725#define AT91C_BASE_TCB1 ((AT91PS_TCB) 0xFFFA4080) // (TCB1) Base Address
2726#define AT91C_BASE_TC2 ((AT91PS_TC) 0xFFFA0080) // (TC2) Base Address
2727#define AT91C_BASE_TC1 ((AT91PS_TC) 0xFFFA0040) // (TC1) Base Address
2728#define AT91C_BASE_TC0 ((AT91PS_TC) 0xFFFA0000) // (TC0) Base Address
2729#define AT91C_BASE_TCB0 ((AT91PS_TCB) 0xFFFA0000) // (TCB0) Base Address
2730#define AT91C_BASE_UHP ((AT91PS_UHP) 0x00300000) // (UHP) Base Address
2731#define AT91C_BASE_EMAC ((AT91PS_EMAC) 0xFFFBC000) // (EMAC) Base Address
2732#define AT91C_BASE_EBI ((AT91PS_EBI) 0xFFFFFF60) // (EBI) Base Address
2733#define AT91C_BASE_SMC2 ((AT91PS_SMC2) 0xFFFFFF70) // (SMC2) Base Address
2734#define AT91C_BASE_SDRC ((AT91PS_SDRC) 0xFFFFFF90) // (SDRC) Base Address
2735#define AT91C_BASE_BFC ((AT91PS_BFC) 0xFFFFFFC0) // (BFC) Base Address
2736
2737// *****************************************************************************
2738// MEMORY MAPPING DEFINITIONS FOR AT91RM9200
2739// *****************************************************************************
2740#define AT91C_ISRAM ((char *) 0x00200000) // Internal SRAM base address
2741#define AT91C_ISRAM_SIZE ((unsigned int) 0x00004000) // Internal SRAM size in byte (16 Kbyte)
2742#define AT91C_IROM ((char *) 0x00100000) // Internal ROM base address
2743#define AT91C_IROM_SIZE ((unsigned int) 0x00020000) // Internal ROM size in byte (128 Kbyte)
2744
2745#endif
2746

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