Root/target/linux/brcm47xx/patches-3.6/241-bcma-broadcom-2011-sdk-updates.patch

1--- a/drivers/bcma/core.c
2+++ b/drivers/bcma/core.c
3@@ -43,6 +43,7 @@ int bcma_core_enable(struct bcma_device
4     bcma_aread32(core, BCMA_IOCTL);
5 
6     bcma_awrite32(core, BCMA_RESET_CTL, 0);
7+ bcma_aread32(core, BCMA_RESET_CTL);
8     udelay(1);
9 
10     bcma_awrite32(core, BCMA_IOCTL, (BCMA_IOCTL_CLK | flags));
11--- a/include/linux/bcma/bcma_driver_pci.h
12+++ b/include/linux/bcma/bcma_driver_pci.h
13@@ -179,6 +179,8 @@ struct pci_dev;
14 #define BCMA_CORE_PCI_CFG_FUN_MASK 7 /* Function mask */
15 #define BCMA_CORE_PCI_CFG_OFF_MASK 0xfff /* Register mask */
16 
17+#define BCMA_CORE_PCI_CFG_DEVCTRL 0xd8
18+
19 /* PCIE Root Capability Register bits (Host mode only) */
20 #define BCMA_CORE_PCI_RC_CRS_VISIBILITY 0x0001
21 
22--- a/drivers/bcma/driver_pci_host.c
23+++ b/drivers/bcma/driver_pci_host.c
24@@ -430,7 +430,7 @@ void __devinit bcma_core_pci_hostmode_in
25     /* Reset RC */
26     usleep_range(3000, 5000);
27     pcicore_write32(pc, BCMA_CORE_PCI_CTL, BCMA_CORE_PCI_CTL_RST_OE);
28- usleep_range(1000, 2000);
29+ msleep(50);
30     pcicore_write32(pc, BCMA_CORE_PCI_CTL, BCMA_CORE_PCI_CTL_RST |
31             BCMA_CORE_PCI_CTL_RST_OE);
32 
33@@ -492,6 +492,17 @@ void __devinit bcma_core_pci_hostmode_in
34 
35     bcma_core_pci_enable_crs(pc);
36 
37+ if (bus->chipinfo.id == BCMA_CHIP_ID_BCM4706 ||
38+ bus->chipinfo.id == BCMA_CHIP_ID_BCM4716) {
39+ u16 val16;
40+ bcma_extpci_read_config(pc, 0, 0, BCMA_CORE_PCI_CFG_DEVCTRL,
41+ &val16, sizeof(val16));
42+ val16 |= (2 << 5); /* Max payload size of 512 */
43+ val16 |= (2 << 12); /* MRRS 512 */
44+ bcma_extpci_write_config(pc, 0, 0, BCMA_CORE_PCI_CFG_DEVCTRL,
45+ &val16, sizeof(val16));
46+ }
47+
48     /* Enable PCI bridge BAR0 memory & master access */
49     tmp = PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
50     bcma_extpci_write_config(pc, 0, 0, PCI_COMMAND, &tmp, sizeof(tmp));
51

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