| 1 | From 357761c423c0f9e4af4aafe85be7889dc36f3584 Mon Sep 17 00:00:00 2001 |
| 2 | From: Florian Fainelli <florian@openwrt.org> |
| 3 | Date: Tue, 31 Jan 2012 15:12:23 +0100 |
| 4 | Subject: [PATCH 4/6] MIPS: BCM63XX: add RNG peripheral definitions |
| 5 | |
| 6 | Signed-off-by: Florian Fainelli <florian@openwrt.org> |
| 7 | Cc: linux-mips@linux-mips.org |
| 8 | Cc: mpm@selenic.com |
| 9 | Cc: herbert@gondor.apana.org.au |
| 10 | Patchwork: https://patchwork.linux-mips.org/patch/3326/ |
| 11 | Signed-off-by: Ralf Baechle <ralf@linux-mips.org> |
| 12 | --- |
| 13 | arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h | 9 +++++++++ |
| 14 | arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h | 14 ++++++++++++++ |
| 15 | 2 files changed, 23 insertions(+), 0 deletions(-) |
| 16 | |
| 17 | --- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h |
| 18 | +++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h |
| 19 | @@ -129,6 +129,7 @@ enum bcm63xx_regs_set { |
| 20 | RSET_PCMDMA, |
| 21 | RSET_PCMDMAC, |
| 22 | RSET_PCMDMAS, |
| 23 | + RSET_RNG |
| 24 | }; |
| 25 | |
| 26 | #define RSET_DSL_LMEM_SIZE (64 * 1024 * 4) |
| 27 | @@ -152,6 +153,7 @@ enum bcm63xx_regs_set { |
| 28 | #define RSET_XTMDMA_SIZE 256 |
| 29 | #define RSET_XTMDMAC_SIZE(chans) (16 * (chans)) |
| 30 | #define RSET_XTMDMAS_SIZE(chans) (16 * (chans)) |
| 31 | +#define RSET_RNG_SIZE 20 |
| 32 | |
| 33 | /* |
| 34 | * 6338 register sets base address |
| 35 | @@ -195,6 +197,7 @@ enum bcm63xx_regs_set { |
| 36 | #define BCM_6338_PCMDMA_BASE (0xdeadbeef) |
| 37 | #define BCM_6338_PCMDMAC_BASE (0xdeadbeef) |
| 38 | #define BCM_6338_PCMDMAS_BASE (0xdeadbeef) |
| 39 | +#define BCM_6338_RNG_BASE (0xdeadbeef) |
| 40 | |
| 41 | /* |
| 42 | * 6345 register sets base address |
| 43 | @@ -238,6 +241,7 @@ enum bcm63xx_regs_set { |
| 44 | #define BCM_6345_PCMDMA_BASE (0xdeadbeef) |
| 45 | #define BCM_6345_PCMDMAC_BASE (0xdeadbeef) |
| 46 | #define BCM_6345_PCMDMAS_BASE (0xdeadbeef) |
| 47 | +#define BCM_6345_RNG_BASE (0xdeadbeef) |
| 48 | |
| 49 | /* |
| 50 | * 6348 register sets base address |
| 51 | @@ -278,6 +282,7 @@ enum bcm63xx_regs_set { |
| 52 | #define BCM_6348_PCMDMA_BASE (0xdeadbeef) |
| 53 | #define BCM_6348_PCMDMAC_BASE (0xdeadbeef) |
| 54 | #define BCM_6348_PCMDMAS_BASE (0xdeadbeef) |
| 55 | +#define BCM_6348_RNG_BASE (0xdeadbeef) |
| 56 | |
| 57 | /* |
| 58 | * 6358 register sets base address |
| 59 | @@ -318,6 +323,7 @@ enum bcm63xx_regs_set { |
| 60 | #define BCM_6358_PCMDMA_BASE (0xfffe1800) |
| 61 | #define BCM_6358_PCMDMAC_BASE (0xfffe1900) |
| 62 | #define BCM_6358_PCMDMAS_BASE (0xfffe1a00) |
| 63 | +#define BCM_6358_RNG_BASE (0xdeadbeef) |
| 64 | |
| 65 | |
| 66 | /* |
| 67 | @@ -359,6 +365,7 @@ enum bcm63xx_regs_set { |
| 68 | #define BCM_6368_PCMDMA_BASE (0xb0005800) |
| 69 | #define BCM_6368_PCMDMAC_BASE (0xb0005a00) |
| 70 | #define BCM_6368_PCMDMAS_BASE (0xb0005c00) |
| 71 | +#define BCM_6368_RNG_BASE (0xb0004180) |
| 72 | |
| 73 | |
| 74 | extern const unsigned long *bcm63xx_regs_base; |
| 75 | @@ -404,6 +411,7 @@ extern const unsigned long *bcm63xx_regs |
| 76 | __GEN_RSET_BASE(__cpu, PCMDMA) \ |
| 77 | __GEN_RSET_BASE(__cpu, PCMDMAC) \ |
| 78 | __GEN_RSET_BASE(__cpu, PCMDMAS) \ |
| 79 | + __GEN_RSET_BASE(__cpu, RNG) \ |
| 80 | } |
| 81 | |
| 82 | #define __GEN_CPU_REGS_TABLE(__cpu) \ |
| 83 | @@ -442,6 +450,7 @@ extern const unsigned long *bcm63xx_regs |
| 84 | [RSET_PCMDMA] = BCM_## __cpu ##_PCMDMA_BASE, \ |
| 85 | [RSET_PCMDMAC] = BCM_## __cpu ##_PCMDMAC_BASE, \ |
| 86 | [RSET_PCMDMAS] = BCM_## __cpu ##_PCMDMAS_BASE, \ |
| 87 | + [RSET_RNG] = BCM_## __cpu ##_RNG_BASE, \ |
| 88 | |
| 89 | |
| 90 | static inline unsigned long bcm63xx_regset_address(enum bcm63xx_regs_set set) |
| 91 | --- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h |
| 92 | +++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h |
| 93 | @@ -974,6 +974,20 @@ |
| 94 | #define M2M_DSTID_REG(x) ((x) * 0x40 + 0x18) |
| 95 | |
| 96 | /************************************************************************* |
| 97 | + * _REG relative to RSET_RNG |
| 98 | + *************************************************************************/ |
| 99 | + |
| 100 | +#define RNG_CTRL 0x00 |
| 101 | +#define RNG_EN (1 << 0) |
| 102 | + |
| 103 | +#define RNG_STAT 0x04 |
| 104 | +#define RNG_AVAIL_MASK (0xff000000) |
| 105 | + |
| 106 | +#define RNG_DATA 0x08 |
| 107 | +#define RNG_THRES 0x0c |
| 108 | +#define RNG_MASK 0x10 |
| 109 | + |
| 110 | +/************************************************************************* |
| 111 | * _REG relative to RSET_SPI |
| 112 | *************************************************************************/ |
| 113 | |
| 114 | |
