| 1 | From 0c921d542eb4359791cffd1737bf45184f6ae352 Mon Sep 17 00:00:00 2001 |
| 2 | From: Jonas Gorski <jonas.gorski@gmail.com> |
| 3 | Date: Tue, 12 Jun 2012 10:23:39 +0200 |
| 4 | Subject: [PATCH 2/8] MIPS: BCM63XX: Add flash type detection |
| 5 | |
| 6 | On BCM6358 and BCM6368 the attached flash type is exposed through a |
| 7 | bootstrapping register. Use it for auto detecting the flash type on |
| 8 | those and default to parallel flash for earlier SoCs. |
| 9 | |
| 10 | Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com> |
| 11 | Cc: linux-mips@linux-mips.org |
| 12 | Cc: Maxime Bizon <mbizon@freebox.fr> |
| 13 | Cc: Florian Fainelli <florian@openwrt.org> |
| 14 | Cc: Kevin Cernekee <cernekee@gmail.com> |
| 15 | Patchwork: https://patchwork.linux-mips.org/patch/3954/ |
| 16 | Reviewed-by: Florian Fainelli <florian@openwrt.org> |
| 17 | Signed-off-by: Ralf Baechle <ralf@linux-mips.org> |
| 18 | --- |
| 19 | arch/mips/bcm63xx/dev-flash.c | 60 ++++++++++++++++++-- |
| 20 | .../include/asm/mach-bcm63xx/bcm63xx_dev_flash.h | 6 ++ |
| 21 | arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h | 9 +++ |
| 22 | 3 files changed, 69 insertions(+), 6 deletions(-) |
| 23 | |
| 24 | --- a/arch/mips/bcm63xx/dev-flash.c |
| 25 | +++ b/arch/mips/bcm63xx/dev-flash.c |
| 26 | @@ -7,6 +7,7 @@ |
| 27 | * |
| 28 | * Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr> |
| 29 | * Copyright (C) 2008 Florian Fainelli <florian@openwrt.org> |
| 30 | + * Copyright (C) 2012 Jonas Gorski <jonas.gorski@gmail.com> |
| 31 | */ |
| 32 | |
| 33 | #include <linux/init.h> |
| 34 | @@ -54,16 +55,63 @@ static struct platform_device mtd_dev = |
| 35 | }, |
| 36 | }; |
| 37 | |
| 38 | -int __init bcm63xx_flash_register(void) |
| 39 | +static int __init bcm63xx_detect_flash_type(void) |
| 40 | { |
| 41 | u32 val; |
| 42 | |
| 43 | - /* read base address of boot chip select (0) */ |
| 44 | - val = bcm_mpi_readl(MPI_CSBASE_REG(0)); |
| 45 | - val &= MPI_CSBASE_BASE_MASK; |
| 46 | + switch (bcm63xx_get_cpu_id()) { |
| 47 | + case BCM6338_CPU_ID: |
| 48 | + case BCM6345_CPU_ID: |
| 49 | + case BCM6348_CPU_ID: |
| 50 | + /* no way to auto detect so assume parallel */ |
| 51 | + return BCM63XX_FLASH_TYPE_PARALLEL; |
| 52 | + case BCM6358_CPU_ID: |
| 53 | + val = bcm_gpio_readl(GPIO_STRAPBUS_REG); |
| 54 | + if (val & STRAPBUS_6358_BOOT_SEL_PARALLEL) |
| 55 | + return BCM63XX_FLASH_TYPE_PARALLEL; |
| 56 | + else |
| 57 | + return BCM63XX_FLASH_TYPE_SERIAL; |
| 58 | + case BCM6368_CPU_ID: |
| 59 | + val = bcm_gpio_readl(GPIO_STRAPBUS_REG); |
| 60 | + switch (val & STRAPBUS_6368_BOOT_SEL_MASK) { |
| 61 | + case STRAPBUS_6368_BOOT_SEL_NAND: |
| 62 | + return BCM63XX_FLASH_TYPE_NAND; |
| 63 | + case STRAPBUS_6368_BOOT_SEL_SERIAL: |
| 64 | + return BCM63XX_FLASH_TYPE_SERIAL; |
| 65 | + case STRAPBUS_6368_BOOT_SEL_PARALLEL: |
| 66 | + return BCM63XX_FLASH_TYPE_PARALLEL; |
| 67 | + } |
| 68 | + default: |
| 69 | + return -EINVAL; |
| 70 | + } |
| 71 | +} |
| 72 | + |
| 73 | +int __init bcm63xx_flash_register(void) |
| 74 | +{ |
| 75 | + int flash_type; |
| 76 | + u32 val; |
| 77 | |
| 78 | - mtd_resources[0].start = val; |
| 79 | - mtd_resources[0].end = 0x1FFFFFFF; |
| 80 | + flash_type = bcm63xx_detect_flash_type(); |
| 81 | |
| 82 | - return platform_device_register(&mtd_dev); |
| 83 | + switch (flash_type) { |
| 84 | + case BCM63XX_FLASH_TYPE_PARALLEL: |
| 85 | + /* read base address of boot chip select (0) */ |
| 86 | + val = bcm_mpi_readl(MPI_CSBASE_REG(0)); |
| 87 | + val &= MPI_CSBASE_BASE_MASK; |
| 88 | + |
| 89 | + mtd_resources[0].start = val; |
| 90 | + mtd_resources[0].end = 0x1FFFFFFF; |
| 91 | + |
| 92 | + return platform_device_register(&mtd_dev); |
| 93 | + case BCM63XX_FLASH_TYPE_SERIAL: |
| 94 | + pr_warn("unsupported serial flash detected\n"); |
| 95 | + return -ENODEV; |
| 96 | + case BCM63XX_FLASH_TYPE_NAND: |
| 97 | + pr_warn("unsupported NAND flash detected\n"); |
| 98 | + return -ENODEV; |
| 99 | + default: |
| 100 | + pr_err("flash detection failed for BCM%x: %d\n", |
| 101 | + bcm63xx_get_cpu_id(), flash_type); |
| 102 | + return -ENODEV; |
| 103 | + } |
| 104 | } |
| 105 | --- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_flash.h |
| 106 | +++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_flash.h |
| 107 | @@ -1,6 +1,12 @@ |
| 108 | #ifndef __BCM63XX_FLASH_H |
| 109 | #define __BCM63XX_FLASH_H |
| 110 | |
| 111 | +enum { |
| 112 | + BCM63XX_FLASH_TYPE_PARALLEL, |
| 113 | + BCM63XX_FLASH_TYPE_SERIAL, |
| 114 | + BCM63XX_FLASH_TYPE_NAND, |
| 115 | +}; |
| 116 | + |
| 117 | int __init bcm63xx_flash_register(void); |
| 118 | |
| 119 | #endif /* __BCM63XX_FLASH_H */ |
| 120 | --- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h |
| 121 | +++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h |
| 122 | @@ -507,6 +507,15 @@ |
| 123 | #define GPIO_BASEMODE_6368_MASK 0x7 |
| 124 | /* those bits must be kept as read in gpio basemode register*/ |
| 125 | |
| 126 | +#define GPIO_STRAPBUS_REG 0x40 |
| 127 | +#define STRAPBUS_6358_BOOT_SEL_PARALLEL (1 << 1) |
| 128 | +#define STRAPBUS_6358_BOOT_SEL_SERIAL (0 << 1) |
| 129 | +#define STRAPBUS_6368_BOOT_SEL_MASK 0x3 |
| 130 | +#define STRAPBUS_6368_BOOT_SEL_NAND 0 |
| 131 | +#define STRAPBUS_6368_BOOT_SEL_SERIAL 1 |
| 132 | +#define STRAPBUS_6368_BOOT_SEL_PARALLEL 3 |
| 133 | + |
| 134 | + |
| 135 | /************************************************************************* |
| 136 | * _REG relative to RSET_ENET |
| 137 | *************************************************************************/ |
| 138 | |
