Root/target/linux/brcm63xx/patches-3.3/025-MIPS-BCM63XX-Add-basic-BCM6328-support.patch

1From 8f9ed2e5502ed3ba3d4c89678cb44f43ccd5b9e0 Mon Sep 17 00:00:00 2001
2From: Jonas Gorski <jonas.gorski@gmail.com>
3Date: Wed, 13 Jun 2012 16:46:54 +0100
4Subject: [PATCH 4/8] MIPS: BCM63XX: Add basic BCM6328 support
5
6This includes CPU speed, memory size detection and working UART, but
7lacking the appropriate drivers, no support for attached flash.
8
9Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com>
10Cc: linux-mips@linux-mips.org
11Cc: Maxime Bizon <mbizon@freebox.fr>
12Cc: Florian Fainelli <florian@openwrt.org>
13Cc: Kevin Cernekee <cernekee@gmail.com>
14Patchwork: https://patchwork.linux-mips.org/patch/3951/
15Reviewed-by: Florian Fainelli <florian@openwrt.org>
16Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
17---
18 arch/mips/bcm63xx/Kconfig | 3 +
19 arch/mips/bcm63xx/boards/board_bcm963xx.c | 12 ++-
20 arch/mips/bcm63xx/cpu.c | 43 ++++++++
21 arch/mips/bcm63xx/dev-flash.c | 6 +
22 arch/mips/bcm63xx/dev-spi.c | 2 +-
23 arch/mips/bcm63xx/irq.c | 21 ++++
24 arch/mips/bcm63xx/prom.c | 4 +-
25 arch/mips/bcm63xx/setup.c | 13 ++-
26 arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h | 111 ++++++++++++++++++++-
27 arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h | 2 +
28 arch/mips/include/asm/mach-bcm63xx/bcm63xx_io.h | 2 +
29 arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h | 54 ++++++++++
30 arch/mips/include/asm/mach-bcm63xx/ioremap.h | 1 +
31 13 files changed, 265 insertions(+), 9 deletions(-)
32
33--- a/arch/mips/bcm63xx/Kconfig
34+++ b/arch/mips/bcm63xx/Kconfig
35@@ -1,6 +1,9 @@
36 menu "CPU support"
37     depends on BCM63XX
38 
39+config BCM63XX_CPU_6328
40+ bool "support 6328 CPU"
41+
42 config BCM63XX_CPU_6338
43     bool "support 6338 CPU"
44     select HW_HAS_PCI
45--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c
46+++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c
47@@ -708,9 +708,15 @@ void __init board_prom_init(void)
48     char cfe_version[32];
49     u32 val;
50 
51- /* read base address of boot chip select (0) */
52- val = bcm_mpi_readl(MPI_CSBASE_REG(0));
53- val &= MPI_CSBASE_BASE_MASK;
54+ /* read base address of boot chip select (0)
55+ * 6328 does not have MPI but boots from a fixed address
56+ */
57+ if (BCMCPU_IS_6328())
58+ val = 0x18000000;
59+ else {
60+ val = bcm_mpi_readl(MPI_CSBASE_REG(0));
61+ val &= MPI_CSBASE_BASE_MASK;
62+ }
63     boot_addr = (u8 *)KSEG1ADDR(val);
64 
65     /* dump cfe version */
66--- a/arch/mips/bcm63xx/cpu.c
67+++ b/arch/mips/bcm63xx/cpu.c
68@@ -29,6 +29,14 @@ static u16 bcm63xx_cpu_rev;
69 static unsigned int bcm63xx_cpu_freq;
70 static unsigned int bcm63xx_memory_size;
71 
72+static const unsigned long bcm6328_regs_base[] = {
73+ __GEN_CPU_REGS_TABLE(6328)
74+};
75+
76+static const int bcm6328_irqs[] = {
77+ __GEN_CPU_IRQ_TABLE(6328)
78+};
79+
80 static const unsigned long bcm6338_regs_base[] = {
81     __GEN_CPU_REGS_TABLE(6338)
82 };
83@@ -99,6 +107,33 @@ unsigned int bcm63xx_get_memory_size(voi
84 static unsigned int detect_cpu_clock(void)
85 {
86     switch (bcm63xx_get_cpu_id()) {
87+ case BCM6328_CPU_ID:
88+ {
89+ unsigned int tmp, mips_pll_fcvo;
90+
91+ tmp = bcm_misc_readl(MISC_STRAPBUS_6328_REG);
92+ mips_pll_fcvo = (tmp & STRAPBUS_6328_FCVO_MASK)
93+ >> STRAPBUS_6328_FCVO_SHIFT;
94+
95+ switch (mips_pll_fcvo) {
96+ case 0x12:
97+ case 0x14:
98+ case 0x19:
99+ return 160000000;
100+ case 0x1c:
101+ return 192000000;
102+ case 0x13:
103+ case 0x15:
104+ return 200000000;
105+ case 0x1a:
106+ return 384000000;
107+ case 0x16:
108+ return 400000000;
109+ default:
110+ return 320000000;
111+ }
112+
113+ }
114     case BCM6338_CPU_ID:
115         /* BCM6338 has a fixed 240 Mhz frequency */
116         return 240000000;
117@@ -170,6 +205,9 @@ static unsigned int detect_memory_size(v
118     unsigned int cols = 0, rows = 0, is_32bits = 0, banks = 0;
119     u32 val;
120 
121+ if (BCMCPU_IS_6328())
122+ return bcm_ddr_readl(DDR_CSEND_REG) << 24;
123+
124     if (BCMCPU_IS_6345()) {
125         val = bcm_sdram_readl(SDRAM_MBASE_REG);
126         return (val * 8 * 1024 * 1024);
127@@ -237,6 +275,11 @@ void __init bcm63xx_cpu_init(void)
128             u16 chip_id = bcm_readw(BCM_6368_PERF_BASE);
129 
130             switch (chip_id) {
131+ case BCM6328_CPU_ID:
132+ expected_cpu_id = BCM6328_CPU_ID;
133+ bcm63xx_regs_base = bcm6328_regs_base;
134+ bcm63xx_irqs = bcm6328_irqs;
135+ break;
136             case BCM6368_CPU_ID:
137                 expected_cpu_id = BCM6368_CPU_ID;
138                 bcm63xx_regs_base = bcm6368_regs_base;
139--- a/arch/mips/bcm63xx/dev-flash.c
140+++ b/arch/mips/bcm63xx/dev-flash.c
141@@ -60,6 +60,12 @@ static int __init bcm63xx_detect_flash_t
142     u32 val;
143 
144     switch (bcm63xx_get_cpu_id()) {
145+ case BCM6328_CPU_ID:
146+ val = bcm_misc_readl(MISC_STRAPBUS_6328_REG);
147+ if (val & STRAPBUS_6328_BOOT_SEL_SERIAL)
148+ return BCM63XX_FLASH_TYPE_SERIAL;
149+ else
150+ return BCM63XX_FLASH_TYPE_NAND;
151     case BCM6338_CPU_ID:
152     case BCM6345_CPU_ID:
153     case BCM6348_CPU_ID:
154--- a/arch/mips/bcm63xx/dev-spi.c
155+++ b/arch/mips/bcm63xx/dev-spi.c
156@@ -87,7 +87,7 @@ int __init bcm63xx_spi_register(void)
157 {
158     struct clk *periph_clk;
159 
160- if (BCMCPU_IS_6345())
161+ if (BCMCPU_IS_6328() || BCMCPU_IS_6345())
162         return -ENODEV;
163 
164     periph_clk = clk_get(NULL, "periph");
165--- a/arch/mips/bcm63xx/irq.c
166+++ b/arch/mips/bcm63xx/irq.c
167@@ -27,6 +27,17 @@ static void __internal_irq_unmask_32(uns
168 static void __internal_irq_unmask_64(unsigned int irq) __maybe_unused;
169 
170 #ifndef BCMCPU_RUNTIME_DETECT
171+#ifdef CONFIG_BCM63XX_CPU_6328
172+#define irq_stat_reg PERF_IRQSTAT_6328_REG
173+#define irq_mask_reg PERF_IRQMASK_6328_REG
174+#define irq_bits 64
175+#define is_ext_irq_cascaded 1
176+#define ext_irq_start (BCM_6328_EXT_IRQ0 - IRQ_INTERNAL_BASE)
177+#define ext_irq_end (BCM_6328_EXT_IRQ3 - IRQ_INTERNAL_BASE)
178+#define ext_irq_count 4
179+#define ext_irq_cfg_reg1 PERF_EXTIRQ_CFG_REG_6328
180+#define ext_irq_cfg_reg2 0
181+#endif
182 #ifdef CONFIG_BCM63XX_CPU_6338
183 #define irq_stat_reg PERF_IRQSTAT_6338_REG
184 #define irq_mask_reg PERF_IRQMASK_6338_REG
185@@ -118,6 +129,16 @@ static void bcm63xx_init_irq(void)
186     irq_mask_addr = bcm63xx_regset_address(RSET_PERF);
187 
188     switch (bcm63xx_get_cpu_id()) {
189+ case BCM6328_CPU_ID:
190+ irq_stat_addr += PERF_IRQSTAT_6328_REG;
191+ irq_mask_addr += PERF_IRQMASK_6328_REG;
192+ irq_bits = 64;
193+ ext_irq_count = 4;
194+ is_ext_irq_cascaded = 1;
195+ ext_irq_start = BCM_6328_EXT_IRQ0 - IRQ_INTERNAL_BASE;
196+ ext_irq_end = BCM_6328_EXT_IRQ3 - IRQ_INTERNAL_BASE;
197+ ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6328;
198+ break;
199     case BCM6338_CPU_ID:
200         irq_stat_addr += PERF_IRQSTAT_6338_REG;
201         irq_mask_addr += PERF_IRQMASK_6338_REG;
202--- a/arch/mips/bcm63xx/prom.c
203+++ b/arch/mips/bcm63xx/prom.c
204@@ -26,7 +26,9 @@ void __init prom_init(void)
205     bcm_wdt_writel(WDT_STOP_2, WDT_CTL_REG);
206 
207     /* disable all hardware blocks clock for now */
208- if (BCMCPU_IS_6338())
209+ if (BCMCPU_IS_6328())
210+ mask = CKCTL_6328_ALL_SAFE_EN;
211+ else if (BCMCPU_IS_6338())
212         mask = CKCTL_6338_ALL_SAFE_EN;
213     else if (BCMCPU_IS_6345())
214         mask = CKCTL_6345_ALL_SAFE_EN;
215--- a/arch/mips/bcm63xx/setup.c
216+++ b/arch/mips/bcm63xx/setup.c
217@@ -68,6 +68,9 @@ void bcm63xx_machine_reboot(void)
218 
219     /* mask and clear all external irq */
220     switch (bcm63xx_get_cpu_id()) {
221+ case BCM6328_CPU_ID:
222+ perf_regs[0] = PERF_EXTIRQ_CFG_REG_6328;
223+ break;
224     case BCM6338_CPU_ID:
225         perf_regs[0] = PERF_EXTIRQ_CFG_REG_6338;
226         break;
227@@ -95,9 +98,13 @@ void bcm63xx_machine_reboot(void)
228         bcm6348_a1_reboot();
229 
230     printk(KERN_INFO "triggering watchdog soft-reset...\n");
231- reg = bcm_perf_readl(PERF_SYS_PLL_CTL_REG);
232- reg |= SYS_PLL_SOFT_RESET;
233- bcm_perf_writel(reg, PERF_SYS_PLL_CTL_REG);
234+ if (BCMCPU_IS_6328()) {
235+ bcm_wdt_writel(1, WDT_SOFTRESET_REG);
236+ } else {
237+ reg = bcm_perf_readl(PERF_SYS_PLL_CTL_REG);
238+ reg |= SYS_PLL_SOFT_RESET;
239+ bcm_perf_writel(reg, PERF_SYS_PLL_CTL_REG);
240+ }
241     while (1)
242         ;
243 }
244--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
245+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
246@@ -9,6 +9,7 @@
247  * compile time if only one CPU support is enabled (idea stolen from
248  * arm mach-types)
249  */
250+#define BCM6328_CPU_ID 0x6328
251 #define BCM6338_CPU_ID 0x6338
252 #define BCM6345_CPU_ID 0x6345
253 #define BCM6348_CPU_ID 0x6348
254@@ -20,6 +21,19 @@ u16 __bcm63xx_get_cpu_id(void);
255 u16 bcm63xx_get_cpu_rev(void);
256 unsigned int bcm63xx_get_cpu_freq(void);
257 
258+#ifdef CONFIG_BCM63XX_CPU_6328
259+# ifdef bcm63xx_get_cpu_id
260+# undef bcm63xx_get_cpu_id
261+# define bcm63xx_get_cpu_id() __bcm63xx_get_cpu_id()
262+# define BCMCPU_RUNTIME_DETECT
263+# else
264+# define bcm63xx_get_cpu_id() BCM6328_CPU_ID
265+# endif
266+# define BCMCPU_IS_6328() (bcm63xx_get_cpu_id() == BCM6328_CPU_ID)
267+#else
268+# define BCMCPU_IS_6328() (0)
269+#endif
270+
271 #ifdef CONFIG_BCM63XX_CPU_6338
272 # ifdef bcm63xx_get_cpu_id
273 # undef bcm63xx_get_cpu_id
274@@ -129,7 +143,8 @@ enum bcm63xx_regs_set {
275     RSET_PCMDMA,
276     RSET_PCMDMAC,
277     RSET_PCMDMAS,
278- RSET_RNG
279+ RSET_RNG,
280+ RSET_MISC
281 };
282 
283 #define RSET_DSL_LMEM_SIZE (64 * 1024 * 4)
284@@ -156,6 +171,49 @@ enum bcm63xx_regs_set {
285 #define RSET_RNG_SIZE 20
286 
287 /*
288+ * 6328 register sets base address
289+ */
290+#define BCM_6328_DSL_LMEM_BASE (0xdeadbeef)
291+#define BCM_6328_PERF_BASE (0xb0000000)
292+#define BCM_6328_TIMER_BASE (0xb0000040)
293+#define BCM_6328_WDT_BASE (0xb000005c)
294+#define BCM_6328_UART0_BASE (0xb0000100)
295+#define BCM_6328_UART1_BASE (0xb0000120)
296+#define BCM_6328_GPIO_BASE (0xb0000080)
297+#define BCM_6328_SPI_BASE (0xdeadbeef)
298+#define BCM_6328_UDC0_BASE (0xdeadbeef)
299+#define BCM_6328_USBDMA_BASE (0xdeadbeef)
300+#define BCM_6328_OHCI0_BASE (0xdeadbeef)
301+#define BCM_6328_OHCI_PRIV_BASE (0xdeadbeef)
302+#define BCM_6328_USBH_PRIV_BASE (0xdeadbeef)
303+#define BCM_6328_MPI_BASE (0xdeadbeef)
304+#define BCM_6328_PCMCIA_BASE (0xdeadbeef)
305+#define BCM_6328_SDRAM_REGS_BASE (0xdeadbeef)
306+#define BCM_6328_DSL_BASE (0xb0001900)
307+#define BCM_6328_UBUS_BASE (0xdeadbeef)
308+#define BCM_6328_ENET0_BASE (0xdeadbeef)
309+#define BCM_6328_ENET1_BASE (0xdeadbeef)
310+#define BCM_6328_ENETDMA_BASE (0xb000d800)
311+#define BCM_6328_ENETDMAC_BASE (0xb000da00)
312+#define BCM_6328_ENETDMAS_BASE (0xb000dc00)
313+#define BCM_6328_ENETSW_BASE (0xb0e00000)
314+#define BCM_6328_EHCI0_BASE (0x10002500)
315+#define BCM_6328_SDRAM_BASE (0xdeadbeef)
316+#define BCM_6328_MEMC_BASE (0xdeadbeef)
317+#define BCM_6328_DDR_BASE (0xb0003000)
318+#define BCM_6328_M2M_BASE (0xdeadbeef)
319+#define BCM_6328_ATM_BASE (0xdeadbeef)
320+#define BCM_6328_XTM_BASE (0xdeadbeef)
321+#define BCM_6328_XTMDMA_BASE (0xb000b800)
322+#define BCM_6328_XTMDMAC_BASE (0xdeadbeef)
323+#define BCM_6328_XTMDMAS_BASE (0xdeadbeef)
324+#define BCM_6328_PCM_BASE (0xb000a800)
325+#define BCM_6328_PCMDMA_BASE (0xdeadbeef)
326+#define BCM_6328_PCMDMAC_BASE (0xdeadbeef)
327+#define BCM_6328_PCMDMAS_BASE (0xdeadbeef)
328+#define BCM_6328_RNG_BASE (0xdeadbeef)
329+#define BCM_6328_MISC_BASE (0xb0001800)
330+/*
331  * 6338 register sets base address
332  */
333 #define BCM_6338_DSL_LMEM_BASE (0xfff00000)
334@@ -198,6 +256,7 @@ enum bcm63xx_regs_set {
335 #define BCM_6338_PCMDMAC_BASE (0xdeadbeef)
336 #define BCM_6338_PCMDMAS_BASE (0xdeadbeef)
337 #define BCM_6338_RNG_BASE (0xdeadbeef)
338+#define BCM_6338_MISC_BASE (0xdeadbeef)
339 
340 /*
341  * 6345 register sets base address
342@@ -242,6 +301,7 @@ enum bcm63xx_regs_set {
343 #define BCM_6345_PCMDMAC_BASE (0xdeadbeef)
344 #define BCM_6345_PCMDMAS_BASE (0xdeadbeef)
345 #define BCM_6345_RNG_BASE (0xdeadbeef)
346+#define BCM_6345_MISC_BASE (0xdeadbeef)
347 
348 /*
349  * 6348 register sets base address
350@@ -283,6 +343,7 @@ enum bcm63xx_regs_set {
351 #define BCM_6348_PCMDMAC_BASE (0xdeadbeef)
352 #define BCM_6348_PCMDMAS_BASE (0xdeadbeef)
353 #define BCM_6348_RNG_BASE (0xdeadbeef)
354+#define BCM_6348_MISC_BASE (0xdeadbeef)
355 
356 /*
357  * 6358 register sets base address
358@@ -324,6 +385,7 @@ enum bcm63xx_regs_set {
359 #define BCM_6358_PCMDMAC_BASE (0xfffe1900)
360 #define BCM_6358_PCMDMAS_BASE (0xfffe1a00)
361 #define BCM_6358_RNG_BASE (0xdeadbeef)
362+#define BCM_6358_MISC_BASE (0xdeadbeef)
363 
364 
365 /*
366@@ -366,6 +428,7 @@ enum bcm63xx_regs_set {
367 #define BCM_6368_PCMDMAC_BASE (0xb0005a00)
368 #define BCM_6368_PCMDMAS_BASE (0xb0005c00)
369 #define BCM_6368_RNG_BASE (0xb0004180)
370+#define BCM_6368_MISC_BASE (0xdeadbeef)
371 
372 
373 extern const unsigned long *bcm63xx_regs_base;
374@@ -412,6 +475,7 @@ extern const unsigned long *bcm63xx_regs
375     __GEN_RSET_BASE(__cpu, PCMDMAC) \
376     __GEN_RSET_BASE(__cpu, PCMDMAS) \
377     __GEN_RSET_BASE(__cpu, RNG) \
378+ __GEN_RSET_BASE(__cpu, MISC) \
379     }
380 
381 #define __GEN_CPU_REGS_TABLE(__cpu) \
382@@ -451,6 +515,7 @@ extern const unsigned long *bcm63xx_regs
383     [RSET_PCMDMAC] = BCM_## __cpu ##_PCMDMAC_BASE, \
384     [RSET_PCMDMAS] = BCM_## __cpu ##_PCMDMAS_BASE, \
385     [RSET_RNG] = BCM_## __cpu ##_RNG_BASE, \
386+ [RSET_MISC] = BCM_## __cpu ##_MISC_BASE, \
387 
388 
389 static inline unsigned long bcm63xx_regset_address(enum bcm63xx_regs_set set)
390@@ -458,6 +523,9 @@ static inline unsigned long bcm63xx_regs
391 #ifdef BCMCPU_RUNTIME_DETECT
392     return bcm63xx_regs_base[set];
393 #else
394+#ifdef CONFIG_BCM63XX_CPU_6328
395+ __GEN_RSET(6328)
396+#endif
397 #ifdef CONFIG_BCM63XX_CPU_6338
398     __GEN_RSET(6338)
399 #endif
400@@ -512,6 +580,47 @@ enum bcm63xx_irq {
401 };
402 
403 /*
404+ * 6328 irqs
405+ */
406+#define BCM_6328_HIGH_IRQ_BASE (IRQ_INTERNAL_BASE + 32)
407+
408+#define BCM_6328_TIMER_IRQ (IRQ_INTERNAL_BASE + 31)
409+#define BCM_6328_SPI_IRQ 0
410+#define BCM_6328_UART0_IRQ (IRQ_INTERNAL_BASE + 28)
411+#define BCM_6328_UART1_IRQ (BCM_6328_HIGH_IRQ_BASE + 7)
412+#define BCM_6328_DSL_IRQ (IRQ_INTERNAL_BASE + 4)
413+#define BCM_6328_UDC0_IRQ 0
414+#define BCM_6328_ENET0_IRQ 0
415+#define BCM_6328_ENET1_IRQ 0
416+#define BCM_6328_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 12)
417+#define BCM_6328_OHCI0_IRQ (IRQ_INTERNAL_BASE + 9)
418+#define BCM_6328_EHCI0_IRQ (IRQ_INTERNAL_BASE + 10)
419+#define BCM_6328_PCMCIA_IRQ 0
420+#define BCM_6328_ENET0_RXDMA_IRQ 0
421+#define BCM_6328_ENET0_TXDMA_IRQ 0
422+#define BCM_6328_ENET1_RXDMA_IRQ 0
423+#define BCM_6328_ENET1_TXDMA_IRQ 0
424+#define BCM_6328_PCI_IRQ (IRQ_INTERNAL_BASE + 23)
425+#define BCM_6328_ATM_IRQ 0
426+#define BCM_6328_ENETSW_RXDMA0_IRQ (BCM_6328_HIGH_IRQ_BASE + 0)
427+#define BCM_6328_ENETSW_RXDMA1_IRQ (BCM_6328_HIGH_IRQ_BASE + 1)
428+#define BCM_6328_ENETSW_RXDMA2_IRQ (BCM_6328_HIGH_IRQ_BASE + 2)
429+#define BCM_6328_ENETSW_RXDMA3_IRQ (BCM_6328_HIGH_IRQ_BASE + 3)
430+#define BCM_6328_ENETSW_TXDMA0_IRQ (BCM_6328_HIGH_IRQ_BASE + 4)
431+#define BCM_6328_ENETSW_TXDMA1_IRQ (BCM_6328_HIGH_IRQ_BASE + 5)
432+#define BCM_6328_ENETSW_TXDMA2_IRQ (BCM_6328_HIGH_IRQ_BASE + 6)
433+#define BCM_6328_ENETSW_TXDMA3_IRQ (BCM_6328_HIGH_IRQ_BASE + 7)
434+#define BCM_6328_XTM_IRQ (BCM_6328_HIGH_IRQ_BASE + 31)
435+#define BCM_6328_XTM_DMA0_IRQ (BCM_6328_HIGH_IRQ_BASE + 11)
436+
437+#define BCM_6328_PCM_DMA0_IRQ (IRQ_INTERNAL_BASE + 2)
438+#define BCM_6328_PCM_DMA1_IRQ (IRQ_INTERNAL_BASE + 3)
439+#define BCM_6328_EXT_IRQ0 (IRQ_INTERNAL_BASE + 24)
440+#define BCM_6328_EXT_IRQ1 (IRQ_INTERNAL_BASE + 25)
441+#define BCM_6328_EXT_IRQ2 (IRQ_INTERNAL_BASE + 26)
442+#define BCM_6328_EXT_IRQ3 (IRQ_INTERNAL_BASE + 27)
443+
444+/*
445  * 6338 irqs
446  */
447 #define BCM_6338_TIMER_IRQ (IRQ_INTERNAL_BASE + 0)
448--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h
449+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h
450@@ -8,6 +8,8 @@ int __init bcm63xx_gpio_init(void);
451 static inline unsigned long bcm63xx_gpio_count(void)
452 {
453     switch (bcm63xx_get_cpu_id()) {
454+ case BCM6328_CPU_ID:
455+ return 32;
456     case BCM6358_CPU_ID:
457         return 40;
458     case BCM6338_CPU_ID:
459--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_io.h
460+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_io.h
461@@ -91,5 +91,7 @@
462 #define bcm_memc_writel(v, o) bcm_rset_writel(RSET_MEMC, (v), (o))
463 #define bcm_ddr_readl(o) bcm_rset_readl(RSET_DDR, (o))
464 #define bcm_ddr_writel(v, o) bcm_rset_writel(RSET_DDR, (v), (o))
465+#define bcm_misc_readl(o) bcm_rset_readl(RSET_MISC, (o))
466+#define bcm_misc_writel(v, o) bcm_rset_writel(RSET_MISC, (v), (o))
467 
468 #endif /* ! BCM63XX_IO_H_ */
469--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
470+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
471@@ -15,6 +15,30 @@
472 /* Clock Control register */
473 #define PERF_CKCTL_REG 0x4
474 
475+#define CKCTL_6328_PHYMIPS_EN (1 << 0)
476+#define CKCTL_6328_ADSL_QPROC_EN (1 << 1)
477+#define CKCTL_6328_ADSL_AFE_EN (1 << 2)
478+#define CKCTL_6328_ADSL_EN (1 << 3)
479+#define CKCTL_6328_MIPS_EN (1 << 4)
480+#define CKCTL_6328_SAR_EN (1 << 5)
481+#define CKCTL_6328_PCM_EN (1 << 6)
482+#define CKCTL_6328_USBD_EN (1 << 7)
483+#define CKCTL_6328_USBH_EN (1 << 8)
484+#define CKCTL_6328_HSSPI_EN (1 << 9)
485+#define CKCTL_6328_PCIE_EN (1 << 10)
486+#define CKCTL_6328_ROBOSW_EN (1 << 11)
487+
488+#define CKCTL_6328_ALL_SAFE_EN (CKCTL_6328_PHYMIPS_EN | \
489+ CKCTL_6328_ADSL_QPROC_EN | \
490+ CKCTL_6328_ADSL_AFE_EN | \
491+ CKCTL_6328_ADSL_EN | \
492+ CKCTL_6328_SAR_EN | \
493+ CKCTL_6328_PCM_EN | \
494+ CKCTL_6328_USBD_EN | \
495+ CKCTL_6328_USBH_EN | \
496+ CKCTL_6328_ROBOSW_EN | \
497+ CKCTL_6328_PCIE_EN)
498+
499 #define CKCTL_6338_ADSLPHY_EN (1 << 0)
500 #define CKCTL_6338_MPI_EN (1 << 1)
501 #define CKCTL_6338_DRAM_EN (1 << 2)
502@@ -119,6 +143,7 @@
503 #define SYS_PLL_SOFT_RESET 0x1
504 
505 /* Interrupt Mask register */
506+#define PERF_IRQMASK_6328_REG 0x20
507 #define PERF_IRQMASK_6338_REG 0xc
508 #define PERF_IRQMASK_6345_REG 0xc
509 #define PERF_IRQMASK_6348_REG 0xc
510@@ -126,6 +151,7 @@
511 #define PERF_IRQMASK_6368_REG 0x20
512 
513 /* Interrupt Status register */
514+#define PERF_IRQSTAT_6328_REG 0x28
515 #define PERF_IRQSTAT_6338_REG 0x10
516 #define PERF_IRQSTAT_6345_REG 0x10
517 #define PERF_IRQSTAT_6348_REG 0x10
518@@ -133,6 +159,7 @@
519 #define PERF_IRQSTAT_6368_REG 0x28
520 
521 /* External Interrupt Configuration register */
522+#define PERF_EXTIRQ_CFG_REG_6328 0x18
523 #define PERF_EXTIRQ_CFG_REG_6338 0x14
524 #define PERF_EXTIRQ_CFG_REG_6348 0x14
525 #define PERF_EXTIRQ_CFG_REG_6358 0x14
526@@ -162,8 +189,21 @@
527 
528 /* Soft Reset register */
529 #define PERF_SOFTRESET_REG 0x28
530+#define PERF_SOFTRESET_6328_REG 0x10
531 #define PERF_SOFTRESET_6368_REG 0x10
532 
533+#define SOFTRESET_6328_SPI_MASK (1 << 0)
534+#define SOFTRESET_6328_EPHY_MASK (1 << 1)
535+#define SOFTRESET_6328_SAR_MASK (1 << 2)
536+#define SOFTRESET_6328_ENETSW_MASK (1 << 3)
537+#define SOFTRESET_6328_USBS_MASK (1 << 4)
538+#define SOFTRESET_6328_USBH_MASK (1 << 5)
539+#define SOFTRESET_6328_PCM_MASK (1 << 6)
540+#define SOFTRESET_6328_PCIE_CORE_MASK (1 << 7)
541+#define SOFTRESET_6328_PCIE_MASK (1 << 8)
542+#define SOFTRESET_6328_PCIE_EXT_MASK (1 << 9)
543+#define SOFTRESET_6328_PCIE_HARD_MASK (1 << 10)
544+
545 #define SOFTRESET_6338_SPI_MASK (1 << 0)
546 #define SOFTRESET_6338_ENET_MASK (1 << 2)
547 #define SOFTRESET_6338_USBH_MASK (1 << 3)
548@@ -307,6 +347,8 @@
549 /* Watchdog reset length register */
550 #define WDT_RSTLEN_REG 0x8
551 
552+/* Watchdog soft reset register (BCM6328 only) */
553+#define WDT_SOFTRESET_REG 0xc
554 
555 /*************************************************************************
556  * _REG relative to RSET_UARTx
557@@ -933,6 +975,8 @@
558  * _REG relative to RSET_DDR
559  *************************************************************************/
560 
561+#define DDR_CSEND_REG 0x8
562+
563 #define DDR_DMIPSPLLCFG_REG 0x18
564 #define DMIPSPLLCFG_M1_SHIFT 0
565 #define DMIPSPLLCFG_M1_MASK (0xff << DMIPSPLLCFG_M1_SHIFT)
566@@ -1122,4 +1166,14 @@
567 #define SPI_SSOFFTIME_SHIFT 3
568 #define SPI_BYTE_SWAP 0x80
569 
570+/*************************************************************************
571+ * _REG relative to RSET_MISC
572+ *************************************************************************/
573+
574+#define MISC_STRAPBUS_6328_REG 0x240
575+#define STRAPBUS_6328_FCVO_SHIFT 7
576+#define STRAPBUS_6328_FCVO_MASK (0x1f << STRAPBUS_6328_FCVO_SHIFT)
577+#define STRAPBUS_6328_BOOT_SEL_SERIAL (1 << 28)
578+#define STRAPBUS_6328_BOOT_SEL_NAND (0 << 28)
579+
580 #endif /* BCM63XX_REGS_H_ */
581--- a/arch/mips/include/asm/mach-bcm63xx/ioremap.h
582+++ b/arch/mips/include/asm/mach-bcm63xx/ioremap.h
583@@ -18,6 +18,7 @@ static inline int is_bcm63xx_internal_re
584         if (offset >= 0xfff00000)
585             return 1;
586         break;
587+ case BCM6328_CPU_ID:
588     case BCM6368_CPU_ID:
589         if (offset >= 0xb0000000 && offset < 0xb1000000)
590             return 1;
591

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