Root/target/linux/brcm63xx/patches-3.3/443-MIPS-BCM63XX-enable-enet-for-BCM6345.patch

1[PATCH] MIPS: BCM63XX: enable ethernet for BCM6345
2
3BCM6345 has a slightly older DMA engine which is not supported by default by
4the bcm63xx_enet driver. This patch adds the missing Ethernet DMA definitions
5as well as patches all the places in the ethernet driver were the DMA
6reading/writing is different.
7
8Signed-off-by: Florian Fainelli <florian@openwrt.org>
9---
10--- a/arch/mips/bcm63xx/dev-enet.c
11+++ b/arch/mips/bcm63xx/dev-enet.c
12@@ -9,10 +9,44 @@
13 #include <linux/init.h>
14 #include <linux/kernel.h>
15 #include <linux/platform_device.h>
16+#include <linux/export.h>
17 #include <bcm63xx_dev_enet.h>
18 #include <bcm63xx_io.h>
19 #include <bcm63xx_regs.h>
20 
21+#ifdef BCMCPU_RUNTIME_DETECT
22+static const unsigned long bcm6xxx_regs_enetdmac[] = {
23+ [ENETDMAC_CHANCFG] = ENETDMAC_CHANCFG_REG,
24+ [ENETDMAC_IR] = ENETDMAC_IR_REG,
25+ [ENETDMAC_IRMASK] = ENETDMAC_IRMASK_REG,
26+ [ENETDMAC_MAXBURST] = ENETDMAC_MAXBURST_REG,
27+};
28+
29+static const unsigned long bcm6345_regs_enetdmac[] = {
30+ [ENETDMAC_CHANCFG] = ENETDMA_6345_CHANCFG_REG,
31+ [ENETDMAC_IR] = ENETDMA_6345_IR_REG,
32+ [ENETDMAC_IRMASK] = ENETDMA_6345_IRMASK_REG,
33+ [ENETDMAC_MAXBURST] = ENETDMA_6345_MAXBURST_REG,
34+ [ENETDMAC_BUFALLOC] = ENETDMA_6345_BUFALLOC_REG,
35+ [ENETDMAC_RSTART] = ENETDMA_6345_RSTART_REG,
36+ [ENETDMAC_FC] = ENETDMA_6345_FC_REG,
37+ [ENETDMAC_LEN] = ENETDMA_6345_LEN_REG,
38+};
39+
40+const unsigned long *bcm63xx_regs_enetdmac;
41+EXPORT_SYMBOL(bcm63xx_regs_enetdmac);
42+
43+static __init void bcm63xx_enetdmac_regs_init(void)
44+{
45+ if (BCMCPU_IS_6345())
46+ bcm63xx_regs_enetdmac = bcm6345_regs_enetdmac;
47+ else
48+ bcm63xx_regs_enetdmac = bcm6xxx_regs_enetdmac;
49+}
50+#else
51+static __init void bcm63xx_enetdmac_regs_init(void) { }
52+#endif
53+
54 static struct resource shared_res[] = {
55     {
56         .start = -1, /* filled at runtime */
57@@ -137,12 +171,19 @@ static int __init register_shared(void)
58     if (shared_device_registered)
59         return 0;
60 
61+ bcm63xx_enetdmac_regs_init();
62+
63     shared_res[0].start = bcm63xx_regset_address(RSET_ENETDMA);
64     shared_res[0].end = shared_res[0].start;
65- shared_res[0].end += (RSET_ENETDMA_SIZE) - 1;
66+ if (BCMCPU_IS_6345())
67+ shared_res[0].end += (RSET_6345_ENETDMA_SIZE) - 1;
68+ else
69+ shared_res[0].end += (RSET_ENETDMA_SIZE) - 1;
70 
71     if (BCMCPU_IS_6328() || BCMCPU_IS_6362() || BCMCPU_IS_6368())
72         chan_count = 32;
73+ else if (BCMCPU_IS_6345())
74+ chan_count = 8;
75     else
76         chan_count = 16;
77 
78@@ -172,7 +213,7 @@ int __init bcm63xx_enet_register(int uni
79     if (unit > 1)
80         return -ENODEV;
81 
82- if (unit == 1 && BCMCPU_IS_6338())
83+ if (unit == 1 && (BCMCPU_IS_6338() || BCMCPU_IS_6345()))
84         return -ENODEV;
85 
86     ret = register_shared();
87@@ -213,6 +254,20 @@ int __init bcm63xx_enet_register(int uni
88         dpd->phy_interrupt = bcm63xx_get_irq_number(IRQ_ENET_PHY);
89     }
90 
91+ dpd->dma_chan_en_mask = ENETDMAC_CHANCFG_EN_MASK;
92+ dpd->dma_chan_int_mask = ENETDMAC_IR_PKTDONE_MASK;
93+ if (BCMCPU_IS_6345()) {
94+ dpd->dma_chan_en_mask |= ENETDMAC_CHANCFG_CHAINING_MASK;
95+ dpd->dma_chan_en_mask |= ENETDMAC_CHANCFG_WRAP_EN_MASK;
96+ dpd->dma_chan_en_mask |= ENETDMAC_CHANCFG_FLOWC_EN_MASK;
97+ dpd->dma_chan_int_mask |= ENETDMA_IR_BUFDONE_MASK;
98+ dpd->dma_chan_int_mask |= ENETDMA_IR_NOTOWNER_MASK;
99+ dpd->dma_chan_width = ENETDMA_6345_CHAN_WIDTH;
100+ dpd->dma_no_sram = 1;
101+ dpd->dma_desc_shift = ENETDMA_6345_DESC_SHIFT;
102+ } else
103+ dpd->dma_chan_width = ENETDMA_CHAN_WIDTH;
104+
105     ret = platform_device_register(pdev);
106     if (ret)
107         return ret;
108@@ -248,6 +303,10 @@ bcm63xx_enetsw_register(const struct bcm
109     else if (BCMCPU_IS_6368())
110         enetsw_pd.num_ports = ENETSW_PORTS_6368;
111 
112+ enetsw_pd.dma_chan_width = ENETDMA_CHAN_WIDTH;
113+ enetsw_pd.dma_chan_en_mask = ENETDMAC_CHANCFG_EN_MASK;
114+ enetsw_pd.dma_chan_int_mask = ENETDMAC_IR_PKTDONE_MASK;
115+
116     ret = platform_device_register(&bcm63xx_enetsw_device);
117     if (ret)
118         return ret;
119--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
120+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
121@@ -715,6 +715,8 @@
122 /*************************************************************************
123  * _REG relative to RSET_ENETDMA
124  *************************************************************************/
125+#define ENETDMA_CHAN_WIDTH 0x10
126+#define ENETDMA_6345_CHAN_WIDTH 0x40
127 
128 /* Controller Configuration Register */
129 #define ENETDMA_CFG_REG (0x0)
130@@ -764,29 +766,54 @@
131 /* State Ram Word 4 */
132 #define ENETDMA_SRAM4_REG(x) (0x20c + (x) * 0x10)
133 
134+/* Broadcom 6345 ENET DMA definitions */
135+#define ENETDMA_6345_CHANCFG_REG (0x00)
136+
137+#define ENETDMA_6345_MAXBURST_REG (0x04)
138+
139+#define ENETDMA_6345_RSTART_REG (0x08)
140+
141+#define ENETDMA_6345_LEN_REG (0x0C)
142+
143+#define ENETDMA_6345_IR_REG (0x14)
144+
145+#define ENETDMA_6345_IRMASK_REG (0x18)
146+
147+#define ENETDMA_6345_FC_REG (0x1C)
148+
149+#define ENETDMA_6345_BUFALLOC_REG (0x20)
150+
151+/* Shift down for EOP, SOP and WRAP bits */
152+#define ENETDMA_6345_DESC_SHIFT (3)
153 
154 /*************************************************************************
155  * _REG relative to RSET_ENETDMAC
156  *************************************************************************/
157 
158 /* Channel Configuration register */
159-#define ENETDMAC_CHANCFG_REG(x) ((x) * 0x10)
160+#define ENETDMAC_CHANCFG_REG (0x0)
161 #define ENETDMAC_CHANCFG_EN_SHIFT 0
162 #define ENETDMAC_CHANCFG_EN_MASK (1 << ENETDMA_CHANCFG_EN_SHIFT)
163 #define ENETDMAC_CHANCFG_PKTHALT_SHIFT 1
164 #define ENETDMAC_CHANCFG_PKTHALT_MASK (1 << ENETDMA_CHANCFG_PKTHALT_SHIFT)
165+#define ENETDMAC_CHANCFG_CHAINING_SHIFT 2
166+#define ENETDMAC_CHANCFG_CHAINING_MASK (1 << ENETDMAC_CHANCFG_CHAINING_SHIFT)
167+#define ENETDMAC_CHANCFG_WRAP_EN_SHIFT 3
168+#define ENETDMAC_CHANCFG_WRAP_EN_MASK (1 << ENETDMAC_CHANCFG_WRAP_EN_SHIFT)
169+#define ENETDMAC_CHANCFG_FLOWC_EN_SHIFT 4
170+#define ENETDMAC_CHANCFG_FLOWC_EN_MASK (1 << ENETDMAC_CHANCFG_FLOWC_EN_SHIFT)
171 
172 /* Interrupt Control/Status register */
173-#define ENETDMAC_IR_REG(x) (0x4 + (x) * 0x10)
174+#define ENETDMAC_IR_REG (0x4)
175 #define ENETDMAC_IR_BUFDONE_MASK (1 << 0)
176 #define ENETDMAC_IR_PKTDONE_MASK (1 << 1)
177 #define ENETDMAC_IR_NOTOWNER_MASK (1 << 2)
178 
179 /* Interrupt Mask register */
180-#define ENETDMAC_IRMASK_REG(x) (0x8 + (x) * 0x10)
181+#define ENETDMAC_IRMASK_REG (0x8)
182 
183 /* Maximum Burst Length */
184-#define ENETDMAC_MAXBURST_REG(x) (0xc + (x) * 0x10)
185+#define ENETDMAC_MAXBURST_REG (0xc)
186 
187 
188 /*************************************************************************
189@@ -794,16 +821,16 @@
190  *************************************************************************/
191 
192 /* Ring Start Address register */
193-#define ENETDMAS_RSTART_REG(x) ((x) * 0x10)
194+#define ENETDMAS_RSTART_REG (0x0)
195 
196 /* State Ram Word 2 */
197-#define ENETDMAS_SRAM2_REG(x) (0x4 + (x) * 0x10)
198+#define ENETDMAS_SRAM2_REG (0x4)
199 
200 /* State Ram Word 3 */
201-#define ENETDMAS_SRAM3_REG(x) (0x8 + (x) * 0x10)
202+#define ENETDMAS_SRAM3_REG (0x8)
203 
204 /* State Ram Word 4 */
205-#define ENETDMAS_SRAM4_REG(x) (0xc + (x) * 0x10)
206+#define ENETDMAS_SRAM4_REG (0xc)
207 
208 
209 /*************************************************************************
210--- a/drivers/net/ethernet/broadcom/bcm63xx_enet.c
211+++ b/drivers/net/ethernet/broadcom/bcm63xx_enet.c
212@@ -115,26 +115,28 @@ static inline void enet_dma_writel(struc
213     bcm_writel(val, bcm_enet_shared_base[0] + off);
214 }
215 
216-static inline u32 enet_dmac_readl(struct bcm_enet_priv *priv, u32 off)
217+static inline u32 enet_dmac_readl(struct bcm_enet_priv *priv, u32 off, int chan)
218 {
219- return bcm_readl(bcm_enet_shared_base[1] + off);
220+ return bcm_readl(bcm_enet_shared_base[1] +
221+ (bcm63xx_enetdmacreg(off) + (chan * priv->dma_chan_width)));
222 }
223 
224 static inline void enet_dmac_writel(struct bcm_enet_priv *priv,
225- u32 val, u32 off)
226+ u32 val, u32 off, int chan)
227 {
228- bcm_writel(val, bcm_enet_shared_base[1] + off);
229+ bcm_writel(val, bcm_enet_shared_base[1] +
230+ (bcm63xx_enetdmacreg(off) + (chan * priv->dma_chan_width)));
231 }
232 
233-static inline u32 enet_dmas_readl(struct bcm_enet_priv *priv, u32 off)
234+static inline u32 enet_dmas_readl(struct bcm_enet_priv *priv, u32 off, int chan)
235 {
236- return bcm_readl(bcm_enet_shared_base[2] + off);
237+ return bcm_readl(bcm_enet_shared_base[2] + (off + (chan * priv->dma_chan_width)));
238 }
239 
240 static inline void enet_dmas_writel(struct bcm_enet_priv *priv,
241- u32 val, u32 off)
242+ u32 val, u32 off, int chan)
243 {
244- bcm_writel(val, bcm_enet_shared_base[2] + off);
245+ bcm_writel(val, bcm_enet_shared_base[2] + (off + (chan * priv->dma_chan_width)));
246 }
247 
248 /*
249@@ -270,7 +272,7 @@ static int bcm_enet_refill_rx(struct net
250         len_stat = priv->rx_skb_size << DMADESC_LENGTH_SHIFT;
251         len_stat |= DMADESC_OWNER_MASK;
252         if (priv->rx_dirty_desc == priv->rx_ring_size - 1) {
253- len_stat |= DMADESC_WRAP_MASK;
254+ len_stat |= (DMADESC_WRAP_MASK >> priv->dma_desc_shift);
255             priv->rx_dirty_desc = 0;
256         } else {
257             priv->rx_dirty_desc++;
258@@ -281,7 +283,10 @@ static int bcm_enet_refill_rx(struct net
259         priv->rx_desc_count++;
260 
261         /* tell dma engine we allocated one buffer */
262- enet_dma_writel(priv, 1, ENETDMA_BUFALLOC_REG(priv->rx_chan));
263+ if (!priv->dma_no_sram)
264+ enet_dma_writel(priv, 1, ENETDMA_BUFALLOC_REG(priv->rx_chan));
265+ else
266+ enet_dmac_writel(priv, 1, ENETDMAC_BUFALLOC, priv->rx_chan);
267     }
268 
269     /* If rx ring is still empty, set a timer to try allocating
270@@ -357,7 +362,8 @@ static int bcm_enet_receive_queue(struct
271 
272         /* if the packet does not have start of packet _and_
273          * end of packet flag set, then just recycle it */
274- if ((len_stat & DMADESC_ESOP_MASK) != DMADESC_ESOP_MASK) {
275+ if ((len_stat & (DMADESC_ESOP_MASK >> priv->dma_desc_shift)) !=
276+ (DMADESC_ESOP_MASK >> priv->dma_desc_shift)) {
277             dev->stats.rx_dropped++;
278             continue;
279         }
280@@ -418,8 +424,8 @@ static int bcm_enet_receive_queue(struct
281         bcm_enet_refill_rx(dev);
282 
283         /* kick rx dma */
284- enet_dmac_writel(priv, ENETDMAC_CHANCFG_EN_MASK,
285- ENETDMAC_CHANCFG_REG(priv->rx_chan));
286+ enet_dmac_writel(priv, priv->dma_chan_en_mask,
287+ ENETDMAC_CHANCFG, priv->rx_chan);
288     }
289 
290     return processed;
291@@ -494,10 +500,10 @@ static int bcm_enet_poll(struct napi_str
292     dev = priv->net_dev;
293 
294     /* ack interrupts */
295- enet_dmac_writel(priv, ENETDMAC_IR_PKTDONE_MASK,
296- ENETDMAC_IR_REG(priv->rx_chan));
297- enet_dmac_writel(priv, ENETDMAC_IR_PKTDONE_MASK,
298- ENETDMAC_IR_REG(priv->tx_chan));
299+ enet_dmac_writel(priv, priv->dma_chan_int_mask,
300+ ENETDMAC_IR, priv->rx_chan);
301+ enet_dmac_writel(priv, priv->dma_chan_int_mask,
302+ ENETDMAC_IR, priv->tx_chan);
303 
304     /* reclaim sent skb */
305     tx_work_done = bcm_enet_tx_reclaim(dev, 0);
306@@ -516,10 +522,10 @@ static int bcm_enet_poll(struct napi_str
307     napi_complete(napi);
308 
309     /* restore rx/tx interrupt */
310- enet_dmac_writel(priv, ENETDMAC_IR_PKTDONE_MASK,
311- ENETDMAC_IRMASK_REG(priv->rx_chan));
312- enet_dmac_writel(priv, ENETDMAC_IR_PKTDONE_MASK,
313- ENETDMAC_IRMASK_REG(priv->tx_chan));
314+ enet_dmac_writel(priv, priv->dma_chan_int_mask,
315+ ENETDMAC_IRMASK, priv->rx_chan);
316+ enet_dmac_writel(priv, priv->dma_chan_int_mask,
317+ ENETDMAC_IRMASK, priv->tx_chan);
318 
319     return rx_work_done;
320 }
321@@ -562,8 +568,8 @@ static irqreturn_t bcm_enet_isr_dma(int
322     priv = netdev_priv(dev);
323 
324     /* mask rx/tx interrupts */
325- enet_dmac_writel(priv, 0, ENETDMAC_IRMASK_REG(priv->rx_chan));
326- enet_dmac_writel(priv, 0, ENETDMAC_IRMASK_REG(priv->tx_chan));
327+ enet_dmac_writel(priv, 0, ENETDMAC_IRMASK, priv->rx_chan);
328+ enet_dmac_writel(priv, 0, ENETDMAC_IRMASK, priv->tx_chan);
329 
330     napi_schedule(&priv->napi);
331 
332@@ -624,14 +630,14 @@ static int bcm_enet_start_xmit(struct sk
333                        DMA_TO_DEVICE);
334 
335     len_stat = (skb->len << DMADESC_LENGTH_SHIFT) & DMADESC_LENGTH_MASK;
336- len_stat |= DMADESC_ESOP_MASK |
337+ len_stat |= (DMADESC_ESOP_MASK >> priv->dma_desc_shift) |
338         DMADESC_APPEND_CRC |
339         DMADESC_OWNER_MASK;
340 
341     priv->tx_curr_desc++;
342     if (priv->tx_curr_desc == priv->tx_ring_size) {
343         priv->tx_curr_desc = 0;
344- len_stat |= DMADESC_WRAP_MASK;
345+ len_stat |= (DMADESC_WRAP_MASK >> priv->dma_desc_shift);
346     }
347     priv->tx_desc_count--;
348 
349@@ -642,8 +648,8 @@ static int bcm_enet_start_xmit(struct sk
350     wmb();
351 
352     /* kick tx dma */
353- enet_dmac_writel(priv, ENETDMAC_CHANCFG_EN_MASK,
354- ENETDMAC_CHANCFG_REG(priv->tx_chan));
355+ enet_dmac_writel(priv, priv->dma_chan_en_mask,
356+ ENETDMAC_CHANCFG, priv->tx_chan);
357 
358     /* stop queue if no more desc available */
359     if (!priv->tx_desc_count)
360@@ -771,6 +777,9 @@ static void bcm_enet_set_flow(struct bcm
361         val &= ~ENET_RXCFG_ENFLOW_MASK;
362     enet_writel(priv, val, ENET_RXCFG_REG);
363 
364+ if (priv->dma_no_sram)
365+ return;
366+
367     /* tx flow control (pause frame generation) */
368     val = enet_dma_readl(priv, ENETDMA_CFG_REG);
369     if (tx_en)
370@@ -886,8 +895,8 @@ static int bcm_enet_open(struct net_devi
371 
372     /* mask all interrupts and request them */
373     enet_writel(priv, 0, ENET_IRMASK_REG);
374- enet_dmac_writel(priv, 0, ENETDMAC_IRMASK_REG(priv->rx_chan));
375- enet_dmac_writel(priv, 0, ENETDMAC_IRMASK_REG(priv->tx_chan));
376+ enet_dmac_writel(priv, 0, ENETDMAC_IRMASK, priv->rx_chan);
377+ enet_dmac_writel(priv, 0, ENETDMAC_IRMASK, priv->tx_chan);
378 
379     ret = request_irq(dev->irq, bcm_enet_isr_mac, 0, dev->name, dev);
380     if (ret)
381@@ -966,8 +975,12 @@ static int bcm_enet_open(struct net_devi
382     priv->rx_curr_desc = 0;
383 
384     /* initialize flow control buffer allocation */
385- enet_dma_writel(priv, ENETDMA_BUFALLOC_FORCE_MASK | 0,
386- ENETDMA_BUFALLOC_REG(priv->rx_chan));
387+ if (!priv->dma_no_sram)
388+ enet_dma_writel(priv, ENETDMA_BUFALLOC_FORCE_MASK | 0,
389+ ENETDMA_BUFALLOC_REG(priv->rx_chan));
390+ else
391+ enet_dmac_writel(priv, ENETDMA_BUFALLOC_FORCE_MASK | 0,
392+ ENETDMAC_BUFALLOC, priv->rx_chan);
393 
394     if (bcm_enet_refill_rx(dev)) {
395         dev_err(kdev, "cannot allocate rx skb queue\n");
396@@ -976,18 +989,30 @@ static int bcm_enet_open(struct net_devi
397     }
398 
399     /* write rx & tx ring addresses */
400- enet_dmas_writel(priv, priv->rx_desc_dma,
401- ENETDMAS_RSTART_REG(priv->rx_chan));
402- enet_dmas_writel(priv, priv->tx_desc_dma,
403- ENETDMAS_RSTART_REG(priv->tx_chan));
404+ if (!priv->dma_no_sram) {
405+ enet_dmas_writel(priv, priv->rx_desc_dma,
406+ ENETDMAS_RSTART_REG, priv->rx_chan);
407+ enet_dmas_writel(priv, priv->tx_desc_dma,
408+ ENETDMAS_RSTART_REG, priv->tx_chan);
409+ } else {
410+ enet_dmac_writel(priv, priv->rx_desc_dma,
411+ ENETDMAC_RSTART, priv->rx_chan);
412+ enet_dmac_writel(priv, priv->tx_desc_dma,
413+ ENETDMAC_RSTART, priv->tx_chan);
414+ }
415 
416     /* clear remaining state ram for rx & tx channel */
417- enet_dmas_writel(priv, 0, ENETDMAS_SRAM2_REG(priv->rx_chan));
418- enet_dmas_writel(priv, 0, ENETDMAS_SRAM2_REG(priv->tx_chan));
419- enet_dmas_writel(priv, 0, ENETDMAS_SRAM3_REG(priv->rx_chan));
420- enet_dmas_writel(priv, 0, ENETDMAS_SRAM3_REG(priv->tx_chan));
421- enet_dmas_writel(priv, 0, ENETDMAS_SRAM4_REG(priv->rx_chan));
422- enet_dmas_writel(priv, 0, ENETDMAS_SRAM4_REG(priv->tx_chan));
423+ if (!priv->dma_no_sram) {
424+ enet_dmas_writel(priv, 0, ENETDMAS_SRAM2_REG, priv->rx_chan);
425+ enet_dmas_writel(priv, 0, ENETDMAS_SRAM2_REG, priv->tx_chan);
426+ enet_dmas_writel(priv, 0, ENETDMAS_SRAM3_REG, priv->rx_chan);
427+ enet_dmas_writel(priv, 0, ENETDMAS_SRAM3_REG, priv->tx_chan);
428+ enet_dmas_writel(priv, 0, ENETDMAS_SRAM4_REG, priv->rx_chan);
429+ enet_dmas_writel(priv, 0, ENETDMAS_SRAM4_REG, priv->tx_chan);
430+ } else {
431+ enet_dmac_writel(priv, 0, ENETDMAC_FC, priv->rx_chan);
432+ enet_dmac_writel(priv, 0, ENETDMAC_FC, priv->tx_chan);
433+ }
434 
435     /* set max rx/tx length */
436     enet_writel(priv, priv->hw_mtu, ENET_RXMAXLEN_REG);
437@@ -995,18 +1020,24 @@ static int bcm_enet_open(struct net_devi
438 
439     /* set dma maximum burst len */
440     enet_dmac_writel(priv, priv->dma_maxburst,
441- ENETDMAC_MAXBURST_REG(priv->rx_chan));
442+ ENETDMAC_MAXBURST, priv->rx_chan);
443     enet_dmac_writel(priv, priv->dma_maxburst,
444- ENETDMAC_MAXBURST_REG(priv->tx_chan));
445+ ENETDMAC_MAXBURST, priv->tx_chan);
446 
447     /* set correct transmit fifo watermark */
448     enet_writel(priv, BCMENET_TX_FIFO_TRESH, ENET_TXWMARK_REG);
449 
450     /* set flow control low/high threshold to 1/3 / 2/3 */
451- val = priv->rx_ring_size / 3;
452- enet_dma_writel(priv, val, ENETDMA_FLOWCL_REG(priv->rx_chan));
453- val = (priv->rx_ring_size * 2) / 3;
454- enet_dma_writel(priv, val, ENETDMA_FLOWCH_REG(priv->rx_chan));
455+ if (!priv->dma_no_sram) {
456+ val = priv->rx_ring_size / 3;
457+ enet_dma_writel(priv, val, ENETDMA_FLOWCL_REG(priv->rx_chan));
458+ val = (priv->rx_ring_size * 2) / 3;
459+ enet_dma_writel(priv, val, ENETDMA_FLOWCH_REG(priv->rx_chan));
460+ } else {
461+ enet_dmac_writel(priv, 5, ENETDMAC_FC, priv->rx_chan);
462+ enet_dmac_writel(priv, priv->rx_ring_size, ENETDMAC_LEN, priv->rx_chan);
463+ enet_dmac_writel(priv, priv->tx_ring_size, ENETDMAC_LEN, priv->tx_chan);
464+ }
465 
466     /* all set, enable mac and interrupts, start dma engine and
467      * kick rx dma channel */
468@@ -1015,26 +1046,26 @@ static int bcm_enet_open(struct net_devi
469     val |= ENET_CTL_ENABLE_MASK;
470     enet_writel(priv, val, ENET_CTL_REG);
471     enet_dma_writel(priv, ENETDMA_CFG_EN_MASK, ENETDMA_CFG_REG);
472- enet_dmac_writel(priv, ENETDMAC_CHANCFG_EN_MASK,
473- ENETDMAC_CHANCFG_REG(priv->rx_chan));
474+ enet_dmac_writel(priv, priv->dma_chan_en_mask,
475+ ENETDMAC_CHANCFG, priv->rx_chan);
476 
477     /* watch "mib counters about to overflow" interrupt */
478     enet_writel(priv, ENET_IR_MIB, ENET_IR_REG);
479     enet_writel(priv, ENET_IR_MIB, ENET_IRMASK_REG);
480 
481     /* watch "packet transferred" interrupt in rx and tx */
482- enet_dmac_writel(priv, ENETDMAC_IR_PKTDONE_MASK,
483- ENETDMAC_IR_REG(priv->rx_chan));
484- enet_dmac_writel(priv, ENETDMAC_IR_PKTDONE_MASK,
485- ENETDMAC_IR_REG(priv->tx_chan));
486+ enet_dmac_writel(priv, priv->dma_chan_int_mask,
487+ ENETDMAC_IR, priv->rx_chan);
488+ enet_dmac_writel(priv, priv->dma_chan_int_mask,
489+ ENETDMAC_IR, priv->tx_chan);
490 
491     /* make sure we enable napi before rx interrupt */
492     napi_enable(&priv->napi);
493 
494- enet_dmac_writel(priv, ENETDMAC_IR_PKTDONE_MASK,
495- ENETDMAC_IRMASK_REG(priv->rx_chan));
496- enet_dmac_writel(priv, ENETDMAC_IR_PKTDONE_MASK,
497- ENETDMAC_IRMASK_REG(priv->tx_chan));
498+ enet_dmac_writel(priv, priv->dma_chan_int_mask,
499+ ENETDMAC_IRMASK, priv->rx_chan);
500+ enet_dmac_writel(priv, priv->dma_chan_int_mask,
501+ ENETDMAC_IRMASK, priv->tx_chan);
502 
503     if (priv->has_phy)
504         phy_start(priv->phydev);
505@@ -1111,13 +1142,13 @@ static void bcm_enet_disable_dma(struct
506 {
507     int limit;
508 
509- enet_dmac_writel(priv, 0, ENETDMAC_CHANCFG_REG(chan));
510+ enet_dmac_writel(priv, 0, ENETDMAC_CHANCFG, chan);
511 
512     limit = 1000;
513     do {
514         u32 val;
515 
516- val = enet_dmac_readl(priv, ENETDMAC_CHANCFG_REG(chan));
517+ val = enet_dmac_readl(priv, ENETDMAC_CHANCFG, chan);
518         if (!(val & ENETDMAC_CHANCFG_EN_MASK))
519             break;
520         udelay(1);
521@@ -1144,8 +1175,8 @@ static int bcm_enet_stop(struct net_devi
522 
523     /* mask all interrupts */
524     enet_writel(priv, 0, ENET_IRMASK_REG);
525- enet_dmac_writel(priv, 0, ENETDMAC_IRMASK_REG(priv->rx_chan));
526- enet_dmac_writel(priv, 0, ENETDMAC_IRMASK_REG(priv->tx_chan));
527+ enet_dmac_writel(priv, 0, ENETDMAC_IRMASK, priv->rx_chan);
528+ enet_dmac_writel(priv, 0, ENETDMAC_IRMASK, priv->tx_chan);
529 
530     /* make sure no mib update is scheduled */
531     cancel_work_sync(&priv->mib_update_task);
532@@ -1757,6 +1788,11 @@ static int __devinit bcm_enet_probe(stru
533         priv->pause_tx = pd->pause_tx;
534         priv->force_duplex_full = pd->force_duplex_full;
535         priv->force_speed_100 = pd->force_speed_100;
536+ priv->dma_chan_en_mask = pd->dma_chan_en_mask;
537+ priv->dma_chan_int_mask = pd->dma_chan_int_mask;
538+ priv->dma_chan_width = pd->dma_chan_width;
539+ priv->dma_no_sram = pd->dma_no_sram;
540+ priv->dma_desc_shift = pd->dma_desc_shift;
541     }
542 
543     if (priv->mac_id == 0 && priv->has_phy && !priv->use_external_mii) {
544@@ -2144,8 +2180,8 @@ static int bcm_enetsw_open(struct net_de
545     kdev = &priv->pdev->dev;
546 
547     /* mask all interrupts and request them */
548- enet_dmac_writel(priv, 0, ENETDMAC_IRMASK_REG(priv->rx_chan));
549- enet_dmac_writel(priv, 0, ENETDMAC_IRMASK_REG(priv->tx_chan));
550+ enet_dmac_writel(priv, 0, ENETDMAC_IRMASK, priv->rx_chan);
551+ enet_dmac_writel(priv, 0, ENETDMAC_IRMASK, priv->tx_chan);
552 
553     ret = request_irq(priv->irq_rx, bcm_enet_isr_dma,
554               IRQF_DISABLED, dev->name, dev);
555@@ -2269,23 +2305,23 @@ static int bcm_enetsw_open(struct net_de
556 
557     /* write rx & tx ring addresses */
558     enet_dmas_writel(priv, priv->rx_desc_dma,
559- ENETDMAS_RSTART_REG(priv->rx_chan));
560+ ENETDMAS_RSTART_REG, priv->rx_chan);
561     enet_dmas_writel(priv, priv->tx_desc_dma,
562- ENETDMAS_RSTART_REG(priv->tx_chan));
563+ ENETDMAS_RSTART_REG, priv->tx_chan);
564 
565     /* clear remaining state ram for rx & tx channel */
566- enet_dmas_writel(priv, 0, ENETDMAS_SRAM2_REG(priv->rx_chan));
567- enet_dmas_writel(priv, 0, ENETDMAS_SRAM2_REG(priv->tx_chan));
568- enet_dmas_writel(priv, 0, ENETDMAS_SRAM3_REG(priv->rx_chan));
569- enet_dmas_writel(priv, 0, ENETDMAS_SRAM3_REG(priv->tx_chan));
570- enet_dmas_writel(priv, 0, ENETDMAS_SRAM4_REG(priv->rx_chan));
571- enet_dmas_writel(priv, 0, ENETDMAS_SRAM4_REG(priv->tx_chan));
572+ enet_dmas_writel(priv, 0, ENETDMAS_SRAM2_REG, priv->rx_chan);
573+ enet_dmas_writel(priv, 0, ENETDMAS_SRAM2_REG, priv->tx_chan);
574+ enet_dmas_writel(priv, 0, ENETDMAS_SRAM3_REG, priv->rx_chan);
575+ enet_dmas_writel(priv, 0, ENETDMAS_SRAM3_REG, priv->tx_chan);
576+ enet_dmas_writel(priv, 0, ENETDMAS_SRAM4_REG, priv->rx_chan);
577+ enet_dmas_writel(priv, 0, ENETDMAS_SRAM4_REG, priv->tx_chan);
578 
579     /* set dma maximum burst len */
580     enet_dmac_writel(priv, priv->dma_maxburst,
581- ENETDMAC_MAXBURST_REG(priv->rx_chan));
582+ ENETDMAC_MAXBURST, priv->rx_chan);
583     enet_dmac_writel(priv, priv->dma_maxburst,
584- ENETDMAC_MAXBURST_REG(priv->tx_chan));
585+ ENETDMAC_MAXBURST, priv->tx_chan);
586 
587     /* set flow control low/high threshold to 1/3 / 2/3 */
588     val = priv->rx_ring_size / 3;
589@@ -2298,21 +2334,21 @@ static int bcm_enetsw_open(struct net_de
590     wmb();
591     enet_dma_writel(priv, ENETDMA_CFG_EN_MASK, ENETDMA_CFG_REG);
592     enet_dmac_writel(priv, ENETDMAC_CHANCFG_EN_MASK,
593- ENETDMAC_CHANCFG_REG(priv->rx_chan));
594+ ENETDMAC_CHANCFG, priv->rx_chan);
595 
596     /* watch "packet transferred" interrupt in rx and tx */
597     enet_dmac_writel(priv, ENETDMAC_IR_PKTDONE_MASK,
598- ENETDMAC_IR_REG(priv->rx_chan));
599+ ENETDMAC_IR, priv->rx_chan);
600     enet_dmac_writel(priv, ENETDMAC_IR_PKTDONE_MASK,
601- ENETDMAC_IR_REG(priv->tx_chan));
602+ ENETDMAC_IR, priv->tx_chan);
603 
604     /* make sure we enable napi before rx interrupt */
605     napi_enable(&priv->napi);
606 
607     enet_dmac_writel(priv, ENETDMAC_IR_PKTDONE_MASK,
608- ENETDMAC_IRMASK_REG(priv->rx_chan));
609+ ENETDMAC_IRMASK, priv->rx_chan);
610     enet_dmac_writel(priv, ENETDMAC_IR_PKTDONE_MASK,
611- ENETDMAC_IRMASK_REG(priv->tx_chan));
612+ ENETDMAC_IRMASK, priv->tx_chan);
613 
614     netif_carrier_on(dev);
615     netif_start_queue(dev);
616@@ -2419,8 +2455,8 @@ static int bcm_enetsw_stop(struct net_de
617     del_timer_sync(&priv->rx_timeout);
618 
619     /* mask all interrupts */
620- enet_dmac_writel(priv, 0, ENETDMAC_IRMASK_REG(priv->rx_chan));
621- enet_dmac_writel(priv, 0, ENETDMAC_IRMASK_REG(priv->tx_chan));
622+ enet_dmac_writel(priv, 0, ENETDMAC_IRMASK, priv->rx_chan);
623+ enet_dmac_writel(priv, 0, ENETDMAC_IRMASK, priv->tx_chan);
624 
625     /* disable dma & mac */
626     bcm_enet_disable_dma(priv, priv->tx_chan);
627@@ -2757,6 +2793,9 @@ static int __devinit bcm_enetsw_probe(st
628         memcpy(priv->used_ports, pd->used_ports,
629                sizeof (pd->used_ports));
630         priv->num_ports = pd->num_ports;
631+ priv->dma_chan_en_mask = pd->dma_chan_en_mask;
632+ priv->dma_chan_int_mask = pd->dma_chan_int_mask;
633+ priv->dma_chan_width = pd->dma_chan_width;
634     }
635 
636     ret = compute_hw_mtu(priv, dev->mtu);
637--- a/drivers/net/ethernet/broadcom/bcm63xx_enet.h
638+++ b/drivers/net/ethernet/broadcom/bcm63xx_enet.h
639@@ -367,6 +367,21 @@ struct bcm_enet_priv {
640     /* used to poll switch port state */
641     struct timer_list swphy_poll;
642     spinlock_t enetsw_mdio_lock;
643+
644+ /* dma channel enable mask */
645+ u32 dma_chan_en_mask;
646+
647+ /* dma channel interrupt mask */
648+ u32 dma_chan_int_mask;
649+
650+ /* dma engine has *no* internal SRAM */
651+ unsigned int dma_no_sram;
652+
653+ /* dma channel width */
654+ unsigned int dma_chan_width;
655+
656+ /* dma descriptor shift value */
657+ unsigned int dma_desc_shift;
658 };
659 
660 static inline int bcm_enet_port_is_rgmii(int portid)
661--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
662+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
663@@ -173,6 +173,7 @@ enum bcm63xx_regs_set {
664 #define BCM_6368_RSET_SPI_SIZE 1804
665 #define RSET_ENET_SIZE 2048
666 #define RSET_ENETDMA_SIZE 256
667+#define RSET_6345_ENETDMA_SIZE 64
668 #define RSET_ENETDMAC_SIZE(chans) (16 * (chans))
669 #define RSET_ENETDMAS_SIZE(chans) (16 * (chans))
670 #define RSET_ENETSW_SIZE 65536
671@@ -299,7 +300,7 @@ enum bcm63xx_regs_set {
672 #define BCM_6345_USBDMA_BASE (0xfffe2800)
673 #define BCM_6345_ENET0_BASE (0xfffe1800)
674 #define BCM_6345_ENETDMA_BASE (0xfffe2800)
675-#define BCM_6345_ENETDMAC_BASE (0xfffe2900)
676+#define BCM_6345_ENETDMAC_BASE (0xfffe2840)
677 #define BCM_6345_ENETDMAS_BASE (0xfffe2a00)
678 #define BCM_6345_ENETSW_BASE (0xdeadbeef)
679 #define BCM_6345_PCMCIA_BASE (0xfffe2028)
680--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_enet.h
681+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_enet.h
682@@ -4,6 +4,8 @@
683 #include <linux/if_ether.h>
684 #include <linux/init.h>
685 
686+#include <bcm63xx_regs.h>
687+
688 /*
689  * on board ethernet platform data
690  */
691@@ -37,6 +39,21 @@ struct bcm63xx_enet_platform_data {
692                       int phy_id, int reg),
693               void (*mii_write)(struct net_device *dev,
694                         int phy_id, int reg, int val));
695+
696+ /* DMA channel enable mask */
697+ u32 dma_chan_en_mask;
698+
699+ /* DMA channel interrupt mask */
700+ u32 dma_chan_int_mask;
701+
702+ /* Set to one if DMA engine has *no* SRAM */
703+ unsigned int dma_no_sram;
704+
705+ /* DMA channel register width */
706+ unsigned int dma_chan_width;
707+
708+ /* DMA descriptor shift */
709+ unsigned int dma_desc_shift;
710 };
711 
712 /*
713@@ -64,6 +81,15 @@ struct bcm63xx_enetsw_platform_data {
714     char mac_addr[ETH_ALEN];
715     int num_ports;
716     struct bcm63xx_enetsw_port used_ports[ENETSW_MAX_PORT];
717+
718+ /* DMA channel enable mask */
719+ u32 dma_chan_en_mask;
720+
721+ /* DMA channel interrupt mask */
722+ u32 dma_chan_int_mask;
723+
724+ /* DMA channel register width */
725+ unsigned int dma_chan_width;
726 };
727 
728 int __init bcm63xx_enet_register(int unit,
729@@ -72,4 +98,66 @@ int __init bcm63xx_enet_register(int uni
730 int __init
731 bcm63xx_enetsw_register(const struct bcm63xx_enetsw_platform_data *pd);
732 
733+enum bcm63xx_regs_enetdmac {
734+ ENETDMAC_CHANCFG,
735+ ENETDMAC_IR,
736+ ENETDMAC_IRMASK,
737+ ENETDMAC_MAXBURST,
738+ ENETDMAC_BUFALLOC,
739+ ENETDMAC_RSTART,
740+ ENETDMAC_FC,
741+ ENETDMAC_LEN,
742+};
743+
744+static inline unsigned long bcm63xx_enetdmacreg(enum bcm63xx_regs_enetdmac reg)
745+{
746+#ifdef BCMCPU_RUNTIME_DETECT
747+ extern const unsigned long *bcm63xx_regs_enetdmac;
748+
749+ return bcm63xx_regs_enetdmac[reg];
750+#else
751+#ifdef CONFIG_BCM63XX_CPU_6345
752+ switch (reg) {
753+ case ENETDMAC_CHANCFG:
754+ return ENETDMA_6345_CHANCFG_REG;
755+ case ENETDMAC_IR:
756+ return ENETDMA_6345_IR_REG;
757+ case ENETDMAC_IRMASK:
758+ return ENETDMA_6345_IRMASK_REG;
759+ case ENETDMAC_MAXBURST:
760+ return ENETDMA_6345_MAXBURST_REG;
761+ case ENETDMAC_BUFALLOC:
762+ return ENETDMA_6345_BUFALLOC_REG;
763+ case ENETDMAC_RSTART:
764+ return ENETDMA_6345_RSTART_REG;
765+ case ENETDMAC_FC:
766+ return ENETDMA_6345_FC_REG;
767+ case ENETDMAC_LEN:
768+ return ENETDMA_6345_LEN_REG;
769+ }
770+#endif
771+#if defined(CONFIG_BCM6XX_CPU_6338) || defined(CONFIG_BCM63XX_CPU_6348) \
772+ defined(CONFIG_BCM63XX_CPU_6358) || defined(CONFIG_BCM63XX_CPU_6362) \
773+ defined(CONFIG_BCM63XX_CPU_6368)
774+ switch (reg) {
775+ case ENETDMAC_CHANCFG:
776+ return ENETDMAC_CHANCFG_REG;
777+ case ENETDMAC_IR:
778+ return ENETDMAC_IR_REG;
779+ case ENETDMAC_IRMASK:
780+ return ENETDMAC_IRMASK_REG;
781+ case ENETDMAC_MAXBURST:
782+ return ENETDMAC_MAXBURST_REG;
783+ case ENETDMAC_BUFALLOC:
784+ case ENETDMAC_RSTART:
785+ case ENETDMAC_FC:
786+ case ENETDMAC_LEN:
787+ return 0;
788+ }
789+#endif
790+#endif
791+ return 0;
792+}
793+
794+
795 #endif /* ! BCM63XX_DEV_ENET_H_ */
796

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