| 1 | --- a/arch/mips/bcm63xx/irq.c |
| 2 | +++ b/arch/mips/bcm63xx/irq.c |
| 3 | @@ -56,8 +56,8 @@ static void __internal_irq_unmask_64(uns |
| 4 | #define is_ext_irq_cascaded 0 |
| 5 | #define ext_irq_start 0 |
| 6 | #define ext_irq_end 0 |
| 7 | -#define ext_irq_count 0 |
| 8 | -#define ext_irq_cfg_reg1 0 |
| 9 | +#define ext_irq_count 4 |
| 10 | +#define ext_irq_cfg_reg1 PERF_EXTIRQ_CFG_REG_6345 |
| 11 | #define ext_irq_cfg_reg2 0 |
| 12 | #endif |
| 13 | #ifdef CONFIG_BCM63XX_CPU_6348 |
| 14 | @@ -143,11 +143,15 @@ static void bcm63xx_init_irq(void) |
| 15 | irq_stat_addr += PERF_IRQSTAT_6338_REG; |
| 16 | irq_mask_addr += PERF_IRQMASK_6338_REG; |
| 17 | irq_bits = 32; |
| 18 | + ext_irq_count = 4; |
| 19 | + ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6338; |
| 20 | break; |
| 21 | case BCM6345_CPU_ID: |
| 22 | irq_stat_addr += PERF_IRQSTAT_6345_REG; |
| 23 | irq_mask_addr += PERF_IRQMASK_6345_REG; |
| 24 | irq_bits = 32; |
| 25 | + ext_irq_count = 4; |
| 26 | + ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6345; |
| 27 | break; |
| 28 | case BCM6348_CPU_ID: |
| 29 | irq_stat_addr += PERF_IRQSTAT_6348_REG; |
| 30 | @@ -434,7 +438,8 @@ static int bcm63xx_external_irq_set_type |
| 31 | reg = bcm_perf_readl(regaddr); |
| 32 | irq %= 4; |
| 33 | |
| 34 | - if (BCMCPU_IS_6348()) { |
| 35 | + switch (bcm63xx_get_cpu_id()) { |
| 36 | + case BCM6348_CPU_ID: |
| 37 | if (levelsense) |
| 38 | reg |= EXTIRQ_CFG_LEVELSENSE_6348(irq); |
| 39 | else |
| 40 | @@ -447,9 +452,12 @@ static int bcm63xx_external_irq_set_type |
| 41 | reg |= EXTIRQ_CFG_BOTHEDGE_6348(irq); |
| 42 | else |
| 43 | reg &= ~EXTIRQ_CFG_BOTHEDGE_6348(irq); |
| 44 | - } |
| 45 | + break; |
| 46 | |
| 47 | - if (BCMCPU_IS_6338() || BCMCPU_IS_6358() || BCMCPU_IS_6368()) { |
| 48 | + case BCM6338_CPU_ID: |
| 49 | + case BCM6345_CPU_ID: |
| 50 | + case BCM6358_CPU_ID: |
| 51 | + case BCM6368_CPU_ID: |
| 52 | if (levelsense) |
| 53 | reg |= EXTIRQ_CFG_LEVELSENSE(irq); |
| 54 | else |
| 55 | @@ -462,6 +470,9 @@ static int bcm63xx_external_irq_set_type |
| 56 | reg |= EXTIRQ_CFG_BOTHEDGE(irq); |
| 57 | else |
| 58 | reg &= ~EXTIRQ_CFG_BOTHEDGE(irq); |
| 59 | + break; |
| 60 | + default: |
| 61 | + BUG(); |
| 62 | } |
| 63 | |
| 64 | bcm_perf_writel(reg, regaddr); |
| 65 | --- a/arch/mips/bcm63xx/setup.c |
| 66 | +++ b/arch/mips/bcm63xx/setup.c |
| 67 | @@ -74,6 +74,9 @@ void bcm63xx_machine_reboot(void) |
| 68 | case BCM6338_CPU_ID: |
| 69 | perf_regs[0] = PERF_EXTIRQ_CFG_REG_6338; |
| 70 | break; |
| 71 | + case BCM6345_CPU_ID: |
| 72 | + perf_regs[0] = PERF_EXTIRQ_CFG_REG_6345; |
| 73 | + break; |
| 74 | case BCM6348_CPU_ID: |
| 75 | perf_regs[0] = PERF_EXTIRQ_CFG_REG_6348; |
| 76 | break; |
| 77 | @@ -83,6 +86,9 @@ void bcm63xx_machine_reboot(void) |
| 78 | } |
| 79 | |
| 80 | for (i = 0; i < 2; i++) { |
| 81 | + if (!perf_regs[i]) |
| 82 | + break; |
| 83 | + |
| 84 | reg = bcm_perf_readl(perf_regs[i]); |
| 85 | if (BCMCPU_IS_6348()) { |
| 86 | reg &= ~EXTIRQ_CFG_MASK_ALL_6348; |
| 87 | --- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h |
| 88 | +++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h |
| 89 | @@ -161,6 +161,7 @@ |
| 90 | /* External Interrupt Configuration register */ |
| 91 | #define PERF_EXTIRQ_CFG_REG_6328 0x18 |
| 92 | #define PERF_EXTIRQ_CFG_REG_6338 0x14 |
| 93 | +#define PERF_EXTIRQ_CFG_REG_6345 0x14 |
| 94 | #define PERF_EXTIRQ_CFG_REG_6348 0x14 |
| 95 | #define PERF_EXTIRQ_CFG_REG_6358 0x14 |
| 96 | #define PERF_EXTIRQ_CFG_REG_6368 0x18 |
| 97 | |
