| 1 | /* |
| 2 | * Copyright (C) 2012 Gateworks Corporation |
| 3 | * Chris Lang <clang@gateworks.com> |
| 4 | * |
| 5 | * This program is free software; you can redistribute it and/or modify |
| 6 | * it under the terms of the GNU General Public License version 2 as |
| 7 | * published by the Free Software Foundation. |
| 8 | */ |
| 9 | #include <linux/linkage.h> |
| 10 | #include <asm/assembler.h> |
| 11 | #include <asm/asm-offsets.h> |
| 12 | |
| 13 | #define D_CACHE_LINE_SIZE 32 |
| 14 | |
| 15 | .text |
| 16 | |
| 17 | /* |
| 18 | * R8 - DMA Start Address |
| 19 | * R9 - DMA Length |
| 20 | * R10 - DMA Direction |
| 21 | * R11 - DMA type |
| 22 | * R12 - fiq_buffer Address |
| 23 | * R13 - DMA type Address |
| 24 | */ |
| 25 | |
| 26 | .global cns3xxx_fiq_end |
| 27 | ENTRY(cns3xxx_fiq_start) |
| 28 | mov r8, #0 |
| 29 | str r8, [r13] |
| 30 | |
| 31 | ldr r9, [r12] |
| 32 | ldr r8, [r9] |
| 33 | add r8, r8, #1 |
| 34 | str r8, [r9] |
| 35 | |
| 36 | ldmib r12, {r8, r9, r10} |
| 37 | and r11, r10, #0x3000000 |
| 38 | and r10, r10, #0xff |
| 39 | |
| 40 | teq r11, #0x1000000 |
| 41 | beq cns3xxx_dma_map_area |
| 42 | teq r11, #0x2000000 |
| 43 | beq cns3xxx_dma_unmap_area |
| 44 | b cns3xxx_dma_flush_range |
| 45 | |
| 46 | cns3xxx_fiq_exit: |
| 47 | mov r8, #0 |
| 48 | str r8, [r12, #12] |
| 49 | mcr p15, 0, r8, c7, c10, 4 @ drain write buffer |
| 50 | subs pc, lr, #4 |
| 51 | |
| 52 | cns3xxx_dma_map_area: |
| 53 | add r9, r9, r8 |
| 54 | teq r10, #DMA_FROM_DEVICE |
| 55 | beq cns3xxx_dma_inv_range |
| 56 | b cns3xxx_dma_clean_range |
| 57 | |
| 58 | cns3xxx_dma_unmap_area: |
| 59 | add r9, r9, r8 |
| 60 | teq r10, #DMA_TO_DEVICE |
| 61 | bne cns3xxx_dma_inv_range |
| 62 | b cns3xxx_fiq_exit |
| 63 | |
| 64 | cns3xxx_dma_flush_range: |
| 65 | bic r8, r8, #D_CACHE_LINE_SIZE - 1 |
| 66 | 1: |
| 67 | mcr p15, 0, r8, c7, c14, 1 @ clean & invalidate D line |
| 68 | add r8, r8, #D_CACHE_LINE_SIZE |
| 69 | cmp r8, r9 |
| 70 | blo 1b |
| 71 | b cns3xxx_fiq_exit |
| 72 | |
| 73 | cns3xxx_dma_clean_range: |
| 74 | bic r8, r8, #D_CACHE_LINE_SIZE - 1 |
| 75 | 1: |
| 76 | mcr p15, 0, r8, c7, c10, 1 @ clean D line |
| 77 | add r8, r8, #D_CACHE_LINE_SIZE |
| 78 | cmp r8, r9 |
| 79 | blo 1b |
| 80 | b cns3xxx_fiq_exit |
| 81 | |
| 82 | cns3xxx_dma_inv_range: |
| 83 | tst r8, #D_CACHE_LINE_SIZE - 1 |
| 84 | bic r8, r8, #D_CACHE_LINE_SIZE - 1 |
| 85 | mcrne p15, 0, r8, c7, c10, 1 @ clean D line |
| 86 | tst r9, #D_CACHE_LINE_SIZE - 1 |
| 87 | bic r9, r9, #D_CACHE_LINE_SIZE - 1 |
| 88 | mcrne p15, 0, r9, c7, c14, 1 @ clean & invalidate D line |
| 89 | 1: |
| 90 | mcr p15, 0, r8, c7, c6, 1 @ invalidate D line |
| 91 | add r8, r8, #D_CACHE_LINE_SIZE |
| 92 | cmp r8, r9 |
| 93 | blo 1b |
| 94 | b cns3xxx_fiq_exit |
| 95 | |
| 96 | cns3xxx_fiq_end: |
| 97 | |
