Root/target/linux/cns3xxx/files/arch/arm/mach-cns3xxx/laguna.c

1/*
2 * Gateworks Corporation Laguna Platform
3 *
4 * Copyright 2000 Deep Blue Solutions Ltd
5 * Copyright 2008 ARM Limited
6 * Copyright 2008 Cavium Networks
7 * Scott Shu
8 * Copyright 2010 MontaVista Software, LLC.
9 * Anton Vorontsov <avorontsov@mvista.com>
10 * Copyright 2011 Gateworks Corporation
11 * Chris Lang <clang@gateworks.com>
12 * Copyright 2012 Gateworks Corporation
13 * Tim Harvey <tharvey@gateworks.com>
14 *
15 * This file is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License, Version 2, as
17 * published by the Free Software Foundation.
18 */
19
20#include <linux/init.h>
21#include <linux/kernel.h>
22#include <linux/compiler.h>
23#include <linux/io.h>
24#include <linux/gpio.h>
25#include <linux/dma-mapping.h>
26#include <linux/serial_core.h>
27#include <linux/serial_8250.h>
28#include <linux/platform_device.h>
29#include <linux/mtd/mtd.h>
30#include <linux/mtd/physmap.h>
31#include <linux/mtd/partitions.h>
32#include <linux/leds.h>
33#include <linux/i2c.h>
34#include <linux/i2c/at24.h>
35#include <linux/i2c/pca953x.h>
36#include <linux/spi/spi.h>
37#include <linux/spi/flash.h>
38#include <linux/if_ether.h>
39#include <linux/pps-gpio.h>
40#include <asm/setup.h>
41#include <asm/mach-types.h>
42#include <asm/mach/arch.h>
43#include <asm/mach/map.h>
44#include <asm/mach/time.h>
45#include <mach/cns3xxx.h>
46#include <mach/irqs.h>
47#include <mach/platform.h>
48#include <mach/pm.h>
49#include <mach/gpio.h>
50#include <asm/hardware/gic.h>
51#include "core.h"
52#include "devices.h"
53
54#define ARRAY_AND_SIZE(x) (x), ARRAY_SIZE(x)
55
56// Config 1 Bitmap
57#define ETH0_LOAD BIT(0)
58#define ETH1_LOAD BIT(1)
59#define ETH2_LOAD BIT(2)
60#define SATA0_LOAD BIT(3)
61#define SATA1_LOAD BIT(4)
62#define PCM_LOAD BIT(5)
63#define I2S_LOAD BIT(6)
64#define SPI0_LOAD BIT(7)
65#define SPI1_LOAD BIT(8)
66#define PCIE0_LOAD BIT(9)
67#define PCIE1_LOAD BIT(10)
68#define USB0_LOAD BIT(11)
69#define USB1_LOAD BIT(12)
70#define USB1_ROUTE BIT(13)
71#define SD_LOAD BIT(14)
72#define UART0_LOAD BIT(15)
73#define UART1_LOAD BIT(16)
74#define UART2_LOAD BIT(17)
75#define MPCI0_LOAD BIT(18)
76#define MPCI1_LOAD BIT(19)
77#define MPCI2_LOAD BIT(20)
78#define MPCI3_LOAD BIT(21)
79#define FP_BUT_LOAD BIT(22)
80#define FP_BUT_HEADER_LOAD BIT(23)
81#define FP_LED_LOAD BIT(24)
82#define FP_LED_HEADER_LOAD BIT(25)
83#define FP_TAMPER_LOAD BIT(26)
84#define HEADER_33V_LOAD BIT(27)
85#define SATA_POWER_LOAD BIT(28)
86#define FP_POWER_LOAD BIT(29)
87#define GPIO_HEADER_LOAD BIT(30)
88#define GSP_BAT_LOAD BIT(31)
89
90// Config 2 Bitmap
91#define FAN_LOAD BIT(0)
92#define SPI_FLASH_LOAD BIT(1)
93#define NOR_FLASH_LOAD BIT(2)
94#define GPS_LOAD BIT(3)
95#define SUPPLY_5V_LOAD BIT(6)
96#define SUPPLY_33V_LOAD BIT(7)
97
98struct laguna_board_info {
99    char model[16];
100    u32 config_bitmap;
101    u32 config2_bitmap;
102    u8 nor_flash_size;
103    u8 spi_flash_size;
104};
105
106static struct laguna_board_info laguna_info __initdata;
107
108/*
109 * NOR Flash
110 */
111static struct mtd_partition laguna_nor_partitions[] = {
112    {
113        .name = "uboot",
114        .size = SZ_256K,
115        .offset = 0,
116        .mask_flags = MTD_WRITEABLE,
117    }, {
118        .name = "params",
119        .size = SZ_128K,
120        .offset = SZ_256K,
121    }, {
122        .name = "kernel",
123        .size = SZ_2M,
124        .offset = SZ_256K + SZ_128K,
125    }, {
126        .name = "rootfs",
127        .size = SZ_16M - SZ_256K - SZ_128K - SZ_2M,
128        .offset = SZ_256K + SZ_128K + SZ_2M,
129    },
130};
131
132static struct physmap_flash_data laguna_nor_pdata = {
133    .width = 2,
134    .parts = laguna_nor_partitions,
135    .nr_parts = ARRAY_SIZE(laguna_nor_partitions),
136};
137
138static struct resource laguna_nor_res = {
139    .start = CNS3XXX_FLASH_BASE,
140    .end = CNS3XXX_FLASH_BASE + SZ_128M - 1,
141    .flags = IORESOURCE_MEM | IORESOURCE_MEM_32BIT,
142};
143
144static struct platform_device laguna_nor_pdev = {
145    .name = "physmap-flash",
146    .id = 0,
147    .resource = &laguna_nor_res,
148    .num_resources = 1,
149    .dev = {
150        .platform_data = &laguna_nor_pdata,
151    },
152};
153
154/*
155 * SPI
156 */
157static struct mtd_partition laguna_spi_partitions[] = {
158    {
159        .name = "uboot",
160        .size = SZ_256K,
161        .offset = 0,
162        .mask_flags = MTD_WRITEABLE,
163    }, {
164        .name = "params",
165        .size = SZ_256K,
166        .offset = SZ_256K,
167    }, {
168        .name = "kernel",
169        .size = SZ_1M + SZ_512K,
170        .offset = SZ_512K,
171    }, {
172        .name = "rootfs",
173        .size = SZ_16M - SZ_2M,
174        .offset = SZ_2M,
175    },
176};
177
178static struct flash_platform_data laguna_spi_pdata = {
179    .parts = laguna_spi_partitions,
180    .nr_parts = ARRAY_SIZE(laguna_spi_partitions),
181};
182
183static struct spi_board_info __initdata laguna_spi_devices[] = {
184    {
185        .modalias = "m25p80",
186        .platform_data = &laguna_spi_pdata,
187        .max_speed_hz = 50000000,
188        .bus_num = 1,
189        .chip_select = 0,
190    },
191};
192
193static struct platform_device laguna_spi_controller = {
194    .name = "cns3xxx_spi",
195};
196
197/*
198 * LED's
199 */
200static struct gpio_led laguna_gpio_leds[] = {
201    {
202        .name = "user1", /* Green Led */
203        .gpio = 115,
204        .active_low = 1,
205    },{
206        .name = "user2", /* Red Led */
207        .gpio = 114,
208        .active_low = 1,
209    },{
210        .name = "pwr1", /* Green Led */
211        .gpio = 116,
212        .active_low = 1,
213    },{
214        .name = "pwr2", /* Yellow Led */
215        .gpio = 117,
216        .active_low = 1,
217    },{
218        .name = "txd1", /* Green Led */
219        .gpio = 118,
220        .active_low = 1,
221    },{
222        .name = "txd2", /* Yellow Led */
223        .gpio = 119,
224        .active_low = 1,
225    },{
226        .name = "rxd1", /* Green Led */
227        .gpio = 120,
228        .active_low = 1,
229    },{
230        .name = "rxd2", /* Yellow Led */
231        .gpio = 121,
232        .active_low = 1,
233    },{
234        .name = "ser1", /* Green Led */
235        .gpio = 122,
236        .active_low = 1,
237    },{
238        .name = "ser2", /* Yellow Led */
239        .gpio = 123,
240        .active_low = 1,
241    },{
242        .name = "enet1", /* Green Led */
243        .gpio = 124,
244        .active_low = 1,
245    },{
246        .name = "enet2", /* Yellow Led */
247        .gpio = 125,
248        .active_low = 1,
249    },{
250        .name = "sig1_1", /* Green Led */
251        .gpio = 126,
252        .active_low = 1,
253    },{
254        .name = "sig1_2", /* Yellow Led */
255        .gpio = 127,
256        .active_low = 1,
257    },{
258        .name = "sig2_1", /* Green Led */
259        .gpio = 128,
260        .active_low = 1,
261    },{
262        .name = "sig2_2", /* Yellow Led */
263        .gpio = 129,
264        .active_low = 1,
265    },{
266        .name = "sig3_1", /* Green Led */
267        .gpio = 130,
268        .active_low = 1,
269    },{
270        .name = "sig3_2", /* Yellow Led */
271        .gpio = 131,
272        .active_low = 1,
273    },{
274        .name = "net1", /*Green Led */
275        .gpio = 109,
276        .active_low = 1,
277    },{
278        .name = "net2", /* Red Led */
279        .gpio = 110,
280        .active_low = 1,
281    },{
282        .name = "mod1", /* Green Led */
283        .gpio = 111,
284        .active_low = 1,
285    },{
286        .name = "mod2", /* Red Led */
287        .gpio = 112,
288        .active_low = 1,
289    },
290};
291
292static struct gpio_led_platform_data laguna_gpio_leds_data = {
293    .num_leds = 22,
294    .leds = laguna_gpio_leds,
295};
296
297static struct platform_device laguna_gpio_leds_device = {
298    .name = "leds-gpio",
299    .id = -1,
300    .dev.platform_data = &laguna_gpio_leds_data,
301};
302
303/*
304 * Ethernet
305 */
306static struct cns3xxx_plat_info laguna_net_data = {
307    .ports = 0,
308    .phy = {
309        0,
310        1,
311        2,
312    },
313};
314
315static struct platform_device laguna_net_device = {
316    .name = "cns3xxx_eth",
317    .id = 0,
318    .dev.platform_data = &laguna_net_data,
319};
320
321/*
322 * UART
323 */
324static void __init laguna_early_serial_setup(void)
325{
326#ifdef CONFIG_SERIAL_8250_CONSOLE
327    static struct uart_port laguna_serial_port = {
328        .membase = (void __iomem *)CNS3XXX_UART0_BASE_VIRT,
329        .mapbase = CNS3XXX_UART0_BASE,
330        .irq = IRQ_CNS3XXX_UART0,
331        .iotype = UPIO_MEM,
332        .flags = UPF_BOOT_AUTOCONF | UPF_FIXED_TYPE,
333        .regshift = 2,
334        .uartclk = 24000000,
335        .line = 0,
336        .type = PORT_16550A,
337        .fifosize = 16,
338    };
339
340    early_serial_setup(&laguna_serial_port);
341#endif
342}
343
344static struct resource laguna_uart_resources[] = {
345    {
346        .start = CNS3XXX_UART0_BASE,
347        .end = CNS3XXX_UART0_BASE + SZ_4K - 1,
348        .flags = IORESOURCE_MEM
349    },{
350        .start = CNS3XXX_UART2_BASE,
351        .end = CNS3XXX_UART2_BASE + SZ_4K - 1,
352        .flags = IORESOURCE_MEM
353    },{
354        .start = CNS3XXX_UART2_BASE,
355        .end = CNS3XXX_UART2_BASE + SZ_4K - 1,
356        .flags = IORESOURCE_MEM
357    },
358};
359
360static struct plat_serial8250_port laguna_uart_data[] = {
361    {
362        .membase = (char*) (CNS3XXX_UART0_BASE_VIRT),
363        .mapbase = (CNS3XXX_UART0_BASE),
364        .irq = IRQ_CNS3XXX_UART0,
365        .iotype = UPIO_MEM,
366        .flags = UPF_BOOT_AUTOCONF | UPF_FIXED_TYPE | UPF_NO_TXEN_TEST,
367        .regshift = 2,
368        .uartclk = 24000000,
369        .type = PORT_16550A,
370    },{
371        .membase = (char*) (CNS3XXX_UART1_BASE_VIRT),
372        .mapbase = (CNS3XXX_UART1_BASE),
373        .irq = IRQ_CNS3XXX_UART1,
374        .iotype = UPIO_MEM,
375        .flags = UPF_BOOT_AUTOCONF | UPF_FIXED_TYPE | UPF_NO_TXEN_TEST,
376        .regshift = 2,
377        .uartclk = 24000000,
378        .type = PORT_16550A,
379    },{
380        .membase = (char*) (CNS3XXX_UART2_BASE_VIRT),
381        .mapbase = (CNS3XXX_UART2_BASE),
382        .irq = IRQ_CNS3XXX_UART2,
383        .iotype = UPIO_MEM,
384        .flags = UPF_BOOT_AUTOCONF | UPF_FIXED_TYPE | UPF_NO_TXEN_TEST,
385        .regshift = 2,
386        .uartclk = 24000000,
387        .type = PORT_16550A,
388    },
389    { },
390};
391
392static struct platform_device laguna_uart = {
393    .name = "serial8250",
394    .id = PLAT8250_DEV_PLATFORM,
395    .dev.platform_data = laguna_uart_data,
396    .num_resources = 3,
397    .resource = laguna_uart_resources
398};
399
400/*
401 * USB
402 */
403static struct resource cns3xxx_usb_ehci_resources[] = {
404    [0] = {
405        .start = CNS3XXX_USB_BASE,
406        .end = CNS3XXX_USB_BASE + SZ_16M - 1,
407        .flags = IORESOURCE_MEM,
408    },
409    [1] = {
410        .start = IRQ_CNS3XXX_USB_EHCI,
411        .flags = IORESOURCE_IRQ,
412    },
413};
414
415static u64 cns3xxx_usb_ehci_dma_mask = DMA_BIT_MASK(32);
416
417static struct platform_device cns3xxx_usb_ehci_device = {
418    .name = "cns3xxx-ehci",
419    .num_resources = ARRAY_SIZE(cns3xxx_usb_ehci_resources),
420    .resource = cns3xxx_usb_ehci_resources,
421    .dev = {
422        .dma_mask = &cns3xxx_usb_ehci_dma_mask,
423        .coherent_dma_mask = DMA_BIT_MASK(32),
424    },
425};
426
427static struct resource cns3xxx_usb_ohci_resources[] = {
428    [0] = {
429        .start = CNS3XXX_USB_OHCI_BASE,
430        .end = CNS3XXX_USB_OHCI_BASE + SZ_16M - 1,
431        .flags = IORESOURCE_MEM,
432    },
433    [1] = {
434        .start = IRQ_CNS3XXX_USB_OHCI,
435        .flags = IORESOURCE_IRQ,
436    },
437};
438
439static u64 cns3xxx_usb_ohci_dma_mask = DMA_BIT_MASK(32);
440
441static struct platform_device cns3xxx_usb_ohci_device = {
442    .name = "cns3xxx-ohci",
443    .num_resources = ARRAY_SIZE(cns3xxx_usb_ohci_resources),
444    .resource = cns3xxx_usb_ohci_resources,
445    .dev = {
446        .dma_mask = &cns3xxx_usb_ohci_dma_mask,
447        .coherent_dma_mask = DMA_BIT_MASK(32),
448    },
449};
450
451static struct resource cns3xxx_usb_otg_resources[] = {
452    [0] = {
453        .start = CNS3XXX_USBOTG_BASE,
454        .end = CNS3XXX_USBOTG_BASE + SZ_16M - 1,
455        .flags = IORESOURCE_MEM,
456    },
457    [1] = {
458        .start = IRQ_CNS3XXX_USB_OTG,
459        .flags = IORESOURCE_IRQ,
460    },
461};
462
463static u64 cns3xxx_usb_otg_dma_mask = DMA_BIT_MASK(32);
464
465static struct platform_device cns3xxx_usb_otg_device = {
466    .name = "dwc_otg",
467    .num_resources = ARRAY_SIZE(cns3xxx_usb_otg_resources),
468    .resource = cns3xxx_usb_otg_resources,
469    .dev = {
470        .dma_mask = &cns3xxx_usb_otg_dma_mask,
471        .coherent_dma_mask = DMA_BIT_MASK(32),
472    },
473};
474
475/*
476 * I2C
477 */
478static struct resource laguna_i2c_resource[] = {
479    {
480        .start = CNS3XXX_SSP_BASE + 0x20,
481        .end = 0x7100003f,
482        .flags = IORESOURCE_MEM,
483    },{
484        .start = IRQ_CNS3XXX_I2C,
485        .flags = IORESOURCE_IRQ,
486    },
487};
488
489static struct platform_device laguna_i2c_controller = {
490    .name = "cns3xxx-i2c",
491    .num_resources = 2,
492    .resource = laguna_i2c_resource,
493};
494
495static struct memory_accessor *at24_mem_acc;
496
497static void at24_setup(struct memory_accessor *mem_acc, void *context)
498{
499    char buf[16];
500
501    at24_mem_acc = mem_acc;
502
503    /* Read MAC addresses */
504    if (at24_mem_acc->read(at24_mem_acc, buf, 0x100, 6) == 6)
505        memcpy(&laguna_net_data.hwaddr[0], buf, ETH_ALEN);
506    if (at24_mem_acc->read(at24_mem_acc, buf, 0x106, 6) == 6)
507        memcpy(&laguna_net_data.hwaddr[1], buf, ETH_ALEN);
508    if (at24_mem_acc->read(at24_mem_acc, buf, 0x10C, 6) == 6)
509        memcpy(&laguna_net_data.hwaddr[2], buf, ETH_ALEN);
510    if (at24_mem_acc->read(at24_mem_acc, buf, 0x112, 6) == 6)
511        memcpy(&laguna_net_data.hwaddr[3], buf, ETH_ALEN);
512
513    /* Read out Model Information */
514    if (at24_mem_acc->read(at24_mem_acc, buf, 0x130, 16) == 16)
515        memcpy(&laguna_info.model, buf, 16);
516    if (at24_mem_acc->read(at24_mem_acc, buf, 0x140, 1) == 1)
517        memcpy(&laguna_info.nor_flash_size, buf, 1);
518    if (at24_mem_acc->read(at24_mem_acc, buf, 0x141, 1) == 1)
519        memcpy(&laguna_info.spi_flash_size, buf, 1);
520    if (at24_mem_acc->read(at24_mem_acc, buf, 0x142, 4) == 4)
521        memcpy(&laguna_info.config_bitmap, buf, 4);
522    if (at24_mem_acc->read(at24_mem_acc, buf, 0x146, 4) == 4)
523        memcpy(&laguna_info.config2_bitmap, buf, 4);
524};
525
526static struct at24_platform_data laguna_eeprom_info = {
527    .byte_len = 1024,
528    .page_size = 16,
529    .flags = AT24_FLAG_READONLY,
530    .setup = at24_setup,
531};
532
533static struct pca953x_platform_data laguna_pca_data = {
534     .gpio_base = 100,
535    .irq_base = -1,
536};
537
538static struct pca953x_platform_data laguna_pca2_data = {
539     .gpio_base = 116,
540    .irq_base = -1,
541};
542
543static struct i2c_board_info __initdata laguna_i2c_devices[] = {
544    {
545        I2C_BOARD_INFO("pca9555", 0x23),
546        .platform_data = &laguna_pca_data,
547    },{
548        I2C_BOARD_INFO("pca9555", 0x27),
549        .platform_data = &laguna_pca2_data,
550    },{
551        I2C_BOARD_INFO("gsp", 0x29),
552    },{
553        I2C_BOARD_INFO ("24c08",0x50),
554        .platform_data = &laguna_eeprom_info,
555    },{
556        I2C_BOARD_INFO("ds1672", 0x68),
557    },
558};
559
560/*
561 * Watchdog
562 */
563
564static struct resource laguna_watchdog_resources[] = {
565    [0] = {
566        .start = CNS3XXX_TC11MP_TWD_BASE + 0x100, // CPU0 watchdog
567        .end = CNS3XXX_TC11MP_TWD_BASE + SZ_4K - 1,
568        .flags = IORESOURCE_MEM,
569    },
570    [1] = {
571        .start = IRQ_LOCALWDOG,
572        .end = IRQ_LOCALWDOG,
573        .flags = IORESOURCE_IRQ,
574    }
575};
576
577static struct platform_device laguna_watchdog = {
578    .name = "mpcore_wdt",
579    .id = -1,
580    .num_resources = ARRAY_SIZE(laguna_watchdog_resources),
581    .resource = laguna_watchdog_resources,
582};
583
584/*
585 * GPS PPS
586 */
587static struct pps_gpio_platform_data laguna_pps_data = {
588    .gpio_pin = 0,
589    .gpio_label = "GPS_PPS",
590    .assert_falling_edge = 0,
591    .capture_clear = 0,
592};
593
594static struct platform_device laguna_pps_device = {
595    .name = "pps-gpio",
596    .id = -1,
597    .dev.platform_data = &laguna_pps_data,
598};
599
600/*
601 * GPIO
602 */
603
604static struct gpio laguna_gpio_gw2391[] = {
605    { 0, GPIOF_IN , "*GPS_PPS" },
606    { 1, GPIOF_IN , "*GSC_IRQ#" },
607    { 2, GPIOF_IN , "*USB_FAULT#" },
608    { 5, GPIOF_OUT_INIT_LOW , "*USB0_PCI_SEL" },
609    { 6, GPIOF_OUT_INIT_HIGH, "*USB_VBUS_EN" },
610    { 7, GPIOF_OUT_INIT_LOW , "*USB1_PCI_SEL" },
611    { 8, GPIOF_OUT_INIT_HIGH, "*PERST#" },
612    { 9, GPIOF_OUT_INIT_LOW , "*FP_SER_EN#" },
613    { 100, GPIOF_IN , "*USER_PB#" },
614    { 103, GPIOF_OUT_INIT_HIGH, "*V5_EN" },
615    { 108, GPIOF_IN , "DIO0" },
616    { 109, GPIOF_IN , "DIO1" },
617    { 110, GPIOF_IN , "DIO2" },
618    { 111, GPIOF_IN , "DIO3" },
619    { 112, GPIOF_IN , "DIO4" },
620};
621
622static struct gpio laguna_gpio_gw2388[] = {
623    { 0, GPIOF_IN , "*GPS_PPS" },
624    { 1, GPIOF_IN , "*GSC_IRQ#" },
625    { 3, GPIOF_IN , "*USB_FAULT#" },
626    { 6, GPIOF_OUT_INIT_HIGH, "*USB_VBUS_EN" },
627    { 7, GPIOF_OUT_INIT_LOW , "*GSM_SEL0" },
628    { 8, GPIOF_OUT_INIT_LOW , "*GSM_SEL1" },
629    { 9, GPIOF_OUT_INIT_LOW , "*FP_SER_EN" },
630    { 100, GPIOF_OUT_INIT_HIGH, "*USER_PB#" },
631    { 108, GPIOF_IN , "DIO0" },
632    { 109, GPIOF_IN , "DIO1" },
633    { 110, GPIOF_IN , "DIO2" },
634    { 111, GPIOF_IN , "DIO3" },
635    { 112, GPIOF_IN , "DIO4" },
636};
637
638static struct gpio laguna_gpio_gw2387[] = {
639    { 0, GPIOF_IN , "*GPS_PPS" },
640    { 1, GPIOF_IN , "*GSC_IRQ#" },
641    { 2, GPIOF_IN , "*USB_FAULT#" },
642    { 5, GPIOF_OUT_INIT_LOW , "*USB_PCI_SEL" },
643    { 6, GPIOF_OUT_INIT_HIGH, "*USB_VBUS_EN" },
644    { 7, GPIOF_OUT_INIT_LOW , "*GSM_SEL0" },
645    { 8, GPIOF_OUT_INIT_LOW , "*GSM_SEL1" },
646    { 9, GPIOF_OUT_INIT_LOW , "*FP_SER_EN" },
647    { 100, GPIOF_IN , "*USER_PB#" },
648    { 103, GPIOF_OUT_INIT_HIGH, "*V5_EN" },
649    { 108, GPIOF_IN , "DIO0" },
650    { 109, GPIOF_IN , "DIO1" },
651    { 110, GPIOF_IN , "DIO2" },
652    { 111, GPIOF_IN , "DIO3" },
653    { 112, GPIOF_IN , "DIO4" },
654    { 113, GPIOF_IN , "DIO5" },
655};
656
657static struct gpio laguna_gpio_gw2384[] = {
658    { 0, GPIOF_IN , "*GSC_IRQ#" },
659    { 1, GPIOF_OUT_INIT_HIGH, "*USB_HST_VBUS_EN" },
660    { 2, GPIOF_IN , "*USB_HST_FAULT#" },
661    { 5, GPIOF_IN , "*USB_OTG_FAULT#" },
662    { 6, GPIOF_OUT_INIT_LOW , "*USB_HST_PCI_SEL" },
663    { 7, GPIOF_OUT_INIT_LOW , "*GSM_SEL0" },
664    { 8, GPIOF_OUT_INIT_LOW , "*GSM_SEL1" },
665    { 9, GPIOF_OUT_INIT_LOW , "*FP_SER_EN" },
666    { 12, GPIOF_OUT_INIT_LOW , "J10_DIOLED0" },
667    { 13, GPIOF_OUT_INIT_HIGH, "*I2CMUX_RST#" },
668    { 14, GPIOF_OUT_INIT_LOW , "J10_DIOLED1" },
669    { 15, GPIOF_OUT_INIT_LOW , "J10_DIOLED2" },
670    { 100, GPIOF_IN , "*USER_PB#" },
671    { 103, GPIOF_OUT_INIT_HIGH, "V5_EN" },
672    { 108, GPIOF_IN , "J9_DIOGSC0" },
673};
674
675static struct gpio laguna_gpio_gw2383[] = {
676    { 0, GPIOF_IN , "*GPS_PPS" },
677    { 1, GPIOF_IN , "*GSC_IRQ#" },
678    { 2, GPIOF_OUT_INIT_HIGH, "*PCIE_RST#" },
679    { 3, GPIOF_IN , "GPIO0" },
680    { 8, GPIOF_IN , "GPIO1" },
681    { 100, GPIOF_IN , "DIO0" },
682    { 101, GPIOF_IN , "DIO1" },
683};
684
685static struct gpio laguna_gpio_gw2382[] = {
686    { 0, GPIOF_IN , "*GPS_PPS" },
687    { 1, GPIOF_IN , "*GSC_IRQ#" },
688    { 2, GPIOF_OUT_INIT_HIGH, "*PCIE_RST#" },
689    { 3, GPIOF_IN , "GPIO0" },
690    { 4, GPIOF_IN , "GPIO1" },
691    { 9, GPIOF_OUT_INIT_HIGH, "*USB_VBUS_EN" },
692    { 10, GPIOF_OUT_INIT_HIGH, "*USB_PCI_SEL#" },
693    { 100, GPIOF_IN , "DIO0" },
694    { 101, GPIOF_IN , "DIO1" },
695};
696
697static struct gpio laguna_gpio_gw2380[] = {
698    { 0, GPIOF_IN , "*GPS_PPS" },
699    { 1, GPIOF_IN , "*GSC_IRQ#" },
700    { 3, GPIOF_IN , "GPIO0" },
701    { 8, GPIOF_IN , "GPIO1" },
702    { 100, GPIOF_IN , "DIO0" },
703    { 101, GPIOF_IN , "DIO1" },
704    { 102, GPIOF_IN , "DIO2" },
705    { 103, GPIOF_IN , "DIO3" },
706};
707
708/*
709 * Initialization
710 */
711static void __init laguna_init(void)
712{
713    platform_device_register(&laguna_watchdog);
714
715    platform_device_register(&laguna_i2c_controller);
716
717    i2c_register_board_info(0, ARRAY_AND_SIZE(laguna_i2c_devices));
718
719    pm_power_off = cns3xxx_power_off;
720}
721
722static struct map_desc laguna_io_desc[] __initdata = {
723    {
724        .virtual = CNS3XXX_UART0_BASE_VIRT,
725        .pfn = __phys_to_pfn(CNS3XXX_UART0_BASE),
726        .length = SZ_4K,
727        .type = MT_DEVICE,
728    },{
729        .virtual = CNS3XXX_UART1_BASE_VIRT,
730        .pfn = __phys_to_pfn(CNS3XXX_UART1_BASE),
731        .length = SZ_4K,
732        .type = MT_DEVICE,
733    },{
734        .virtual = CNS3XXX_UART2_BASE_VIRT,
735        .pfn = __phys_to_pfn(CNS3XXX_UART2_BASE),
736        .length = SZ_4K,
737        .type = MT_DEVICE,
738    },
739};
740
741static void __init laguna_map_io(void)
742{
743    cns3xxx_common_init();
744    cns3xxx_pcie_iotable_init();
745    iotable_init(ARRAY_AND_SIZE(laguna_io_desc));
746    laguna_early_serial_setup();
747}
748
749static int laguna_register_gpio(struct gpio *array, size_t num)
750{
751    int i, err, ret;
752
753    ret = 0;
754    for (i = 0; i < num; i++, array++) {
755        const char *label = array->label;
756        if (label[0] == '*')
757            label++;
758        err = gpio_request_one(array->gpio, array->flags, label);
759        if (err)
760            ret = err;
761        else {
762            err = gpio_export(array->gpio, array->label[0] != '*');
763        }
764    }
765    return ret;
766}
767
768static int __init laguna_pcie_init(void)
769{
770    if (!machine_is_gw2388())
771        return 0;
772
773    return cns3xxx_pcie_init();
774}
775subsys_initcall(laguna_pcie_init);
776
777static int __init laguna_model_setup(void)
778{
779    u32 __iomem *mem;
780    u32 reg;
781
782    if (!machine_is_gw2388())
783        return 0;
784
785    printk("Running on Gateworks Laguna %s\n", laguna_info.model);
786    cns3xxx_gpio_init( 0, 32, CNS3XXX_GPIOA_BASE_VIRT, IRQ_CNS3XXX_GPIOA,
787        NR_IRQS_CNS3XXX);
788    cns3xxx_gpio_init(32, 32, CNS3XXX_GPIOB_BASE_VIRT, IRQ_CNS3XXX_GPIOB,
789        NR_IRQS_CNS3XXX + 32);
790
791    if (strncmp(laguna_info.model, "GW", 2) == 0) {
792        if (laguna_info.config_bitmap & ETH0_LOAD)
793            laguna_net_data.ports |= BIT(0);
794        if (laguna_info.config_bitmap & ETH1_LOAD)
795            laguna_net_data.ports |= BIT(1);
796        if (laguna_info.config_bitmap & ETH2_LOAD)
797            laguna_net_data.ports |= BIT(2);
798        if (laguna_net_data.ports)
799            platform_device_register(&laguna_net_device);
800
801        if ((laguna_info.config_bitmap & SATA0_LOAD) ||
802            (laguna_info.config_bitmap & SATA1_LOAD))
803            cns3xxx_ahci_init();
804
805        if (laguna_info.config_bitmap & (USB0_LOAD)) {
806            cns3xxx_pwr_power_up(1 << PM_PLL_HM_PD_CTRL_REG_OFFSET_PLL_USB);
807
808            /* DRVVBUS pins share with GPIOA */
809            mem = (void __iomem *)(CNS3XXX_MISC_BASE_VIRT + 0x0014);
810            reg = __raw_readl(mem);
811            reg |= 0x8;
812            __raw_writel(reg, mem);
813
814            /* Enable OTG */
815            mem = (void __iomem *)(CNS3XXX_MISC_BASE_VIRT + 0x0808);
816            reg = __raw_readl(mem);
817            reg &= ~(1 << 10);
818            __raw_writel(reg, mem);
819
820            platform_device_register(&cns3xxx_usb_otg_device);
821        }
822
823        if (laguna_info.config_bitmap & (USB1_LOAD)) {
824            platform_device_register(&cns3xxx_usb_ehci_device);
825            platform_device_register(&cns3xxx_usb_ohci_device);
826        }
827
828        if (laguna_info.config_bitmap & (SD_LOAD))
829            cns3xxx_sdhci_init();
830
831        if (laguna_info.config_bitmap & (UART0_LOAD))
832            laguna_uart.num_resources = 1;
833        if (laguna_info.config_bitmap & (UART1_LOAD))
834            laguna_uart.num_resources = 2;
835        if (laguna_info.config_bitmap & (UART2_LOAD))
836            laguna_uart.num_resources = 3;
837        platform_device_register(&laguna_uart);
838
839        if (laguna_info.config2_bitmap & (NOR_FLASH_LOAD)) {
840            switch (laguna_info.nor_flash_size) {
841                case 1:
842                    laguna_nor_partitions[3].size = SZ_8M - SZ_256K - SZ_128K - SZ_2M;
843                    laguna_nor_res.end = CNS3XXX_FLASH_BASE + SZ_8M - 1;
844                break;
845                case 2:
846                    laguna_nor_partitions[3].size = SZ_16M - SZ_256K - SZ_128K - SZ_2M;
847                    laguna_nor_res.end = CNS3XXX_FLASH_BASE + SZ_16M - 1;
848                break;
849                case 3:
850                    laguna_nor_partitions[3].size = SZ_32M - SZ_256K - SZ_128K - SZ_2M;
851                    laguna_nor_res.end = CNS3XXX_FLASH_BASE + SZ_32M - 1;
852                break;
853                case 4:
854                    laguna_nor_partitions[3].size = SZ_64M - SZ_256K - SZ_128K - SZ_2M;
855                    laguna_nor_res.end = CNS3XXX_FLASH_BASE + SZ_64M - 1;
856                break;
857                case 5:
858                    laguna_nor_partitions[3].size = SZ_128M - SZ_256K - SZ_128K - SZ_2M;
859                    laguna_nor_res.end = CNS3XXX_FLASH_BASE + SZ_128M - 1;
860                break;
861            }
862            platform_device_register(&laguna_nor_pdev);
863        }
864
865        if (laguna_info.config2_bitmap & (SPI_FLASH_LOAD)) {
866            switch (laguna_info.spi_flash_size) {
867                case 1:
868                    laguna_spi_partitions[3].size = SZ_4M - SZ_2M;
869                break;
870                case 2:
871                    laguna_spi_partitions[3].size = SZ_8M - SZ_2M;
872                break;
873                case 3:
874                    laguna_spi_partitions[3].size = SZ_16M - SZ_2M;
875                break;
876                case 4:
877                    laguna_spi_partitions[3].size = SZ_32M - SZ_2M;
878                break;
879                case 5:
880                    laguna_spi_partitions[3].size = SZ_64M - SZ_2M;
881                break;
882            }
883            spi_register_board_info(ARRAY_AND_SIZE(laguna_spi_devices));
884        }
885
886        if ((laguna_info.config_bitmap & SPI0_LOAD) ||
887            (laguna_info.config_bitmap & SPI1_LOAD))
888            platform_device_register(&laguna_spi_controller);
889
890        if (laguna_info.config2_bitmap & GPS_LOAD)
891            platform_device_register(&laguna_pps_device);
892
893        /*
894         * Do any model specific setup not known by the bitmap by matching
895         * the first 6 characters of the model name
896         */
897
898        if ( (strncmp(laguna_info.model, "GW2388", 6) == 0)
899          || (strncmp(laguna_info.model, "GW2389", 6) == 0) )
900        {
901            // configure GPIO's
902            laguna_register_gpio(ARRAY_AND_SIZE(laguna_gpio_gw2388));
903            // configure LED's
904            laguna_gpio_leds_data.num_leds = 2;
905        } else if (strncmp(laguna_info.model, "GW2387", 6) == 0) {
906            // configure GPIO's
907            laguna_register_gpio(ARRAY_AND_SIZE(laguna_gpio_gw2387));
908            // configure LED's
909            laguna_gpio_leds_data.num_leds = 2;
910        } else if (strncmp(laguna_info.model, "GW2384", 6) == 0) {
911            // configure GPIO's
912            laguna_register_gpio(ARRAY_AND_SIZE(laguna_gpio_gw2384));
913            // configure LED's
914            laguna_gpio_leds_data.num_leds = 1;
915        } else if (strncmp(laguna_info.model, "GW2383", 6) == 0) {
916            // configure GPIO's
917            laguna_register_gpio(ARRAY_AND_SIZE(laguna_gpio_gw2383));
918            // configure LED's
919            laguna_gpio_leds[0].gpio = 107;
920            laguna_gpio_leds_data.num_leds = 1;
921        } else if (strncmp(laguna_info.model, "GW2382", 6) == 0) {
922            // configure GPIO's
923            laguna_register_gpio(ARRAY_AND_SIZE(laguna_gpio_gw2382));
924            // configure LED's
925            laguna_gpio_leds[0].gpio = 107;
926            laguna_gpio_leds_data.num_leds = 1;
927        } else if (strncmp(laguna_info.model, "GW2380", 6) == 0) {
928            // configure GPIO's
929            laguna_register_gpio(ARRAY_AND_SIZE(laguna_gpio_gw2380));
930            // configure LED's
931            laguna_gpio_leds[0].gpio = 107;
932            laguna_gpio_leds[1].gpio = 106;
933            laguna_gpio_leds_data.num_leds = 2;
934        } else if (strncmp(laguna_info.model, "GW2391", 6) == 0) {
935            // configure GPIO's
936            laguna_register_gpio(ARRAY_AND_SIZE(laguna_gpio_gw2391));
937            // configure LED's
938            laguna_gpio_leds_data.num_leds = 2;
939        }
940        platform_device_register(&laguna_gpio_leds_device);
941    } else {
942        // Do some defaults here, not sure what yet
943    }
944    return 0;
945}
946late_initcall(laguna_model_setup);
947
948MACHINE_START(GW2388, "Gateworks Corporation Laguna Platform")
949    .atag_offset = 0x100,
950    .map_io = laguna_map_io,
951    .init_irq = cns3xxx_init_irq,
952    .timer = &cns3xxx_timer,
953    .handle_irq = gic_handle_irq,
954    .init_machine = laguna_init,
955    .restart = cns3xxx_restart,
956MACHINE_END
957

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