| 1 | /* |
| 2 | * Cavium CNS3xxx I2C Host Controller |
| 3 | * |
| 4 | * Copyright 2010 Cavium Network |
| 5 | * Copyright 2012 Gateworks Corporation |
| 6 | * Chris Lang <clang@gateworks.com> |
| 7 | * Tim Harvey <tharvey@gateworks.com> |
| 8 | * |
| 9 | * This file is free software; you can redistribute it and/or modify |
| 10 | * it under the terms of the GNU General Public License, Version 2, as |
| 11 | * published by the Free Software Foundation. |
| 12 | */ |
| 13 | |
| 14 | #include <linux/kernel.h> |
| 15 | #include <linux/module.h> |
| 16 | #include <linux/init.h> |
| 17 | #include <linux/platform_device.h> |
| 18 | #include <asm/io.h> |
| 19 | #include <linux/wait.h> |
| 20 | #include <linux/interrupt.h> |
| 21 | #include <linux/delay.h> |
| 22 | #include <linux/i2c.h> |
| 23 | #include <linux/slab.h> |
| 24 | #include <mach/pm.h> |
| 25 | #include <mach/cns3xxx.h> |
| 26 | |
| 27 | /* |
| 28 | * We need the memory map |
| 29 | */ |
| 30 | |
| 31 | |
| 32 | #define MISC_MEM_MAP_VALUE(reg_offset) (*((uint32_t volatile *)(CNS3XXX_MISC_BASE_VIRT + reg_offset))) |
| 33 | #define MISC_IOCDB_CTRL MISC_MEM_MAP_VALUE(0x020) |
| 34 | |
| 35 | #define I2C_MEM_MAP_ADDR(x) (CNS3XXX_SSP_BASE_VIRT + x) |
| 36 | #define I2C_MEM_MAP_VALUE(x) (*((unsigned int volatile*)I2C_MEM_MAP_ADDR(x))) |
| 37 | |
| 38 | #define I2C_CONTROLLER_REG I2C_MEM_MAP_VALUE(0x20) |
| 39 | #define I2C_TIME_OUT_REG I2C_MEM_MAP_VALUE(0x24) |
| 40 | #define I2C_SLAVE_ADDRESS_REG I2C_MEM_MAP_VALUE(0x28) |
| 41 | #define I2C_WRITE_DATA_REG I2C_MEM_MAP_VALUE(0x2C) |
| 42 | #define I2C_READ_DATA_REG I2C_MEM_MAP_VALUE(0x30) |
| 43 | #define I2C_INTERRUPT_STATUS_REG I2C_MEM_MAP_VALUE(0x34) |
| 44 | #define I2C_INTERRUPT_ENABLE_REG I2C_MEM_MAP_VALUE(0x38) |
| 45 | #define I2C_TWI_OUT_DLY_REG I2C_MEM_MAP_VALUE(0x3C) |
| 46 | |
| 47 | #define I2C_BUS_ERROR_FLAG (0x1) |
| 48 | #define I2C_ACTION_DONE_FLAG (0x2) |
| 49 | |
| 50 | #define CNS3xxx_I2C_ENABLE() (I2C_CONTROLLER_REG) |= ((unsigned int)0x1 << 31) |
| 51 | #define CNS3xxx_I2C_DISABLE() (I2C_CONTROLLER_REG) &= ~((unsigned int)0x1 << 31) |
| 52 | #define CNS3xxx_I2C_ENABLE_INTR() (I2C_INTERRUPT_ENABLE_REG) |= 0x03 |
| 53 | #define CNS3xxx_I2C_DISABLE_INTR() (I2C_INTERRUPT_ENABLE_REG) &= 0xfc |
| 54 | |
| 55 | #define TWI_TIMEOUT (10*HZ) |
| 56 | #define I2C_100KHZ 100000 |
| 57 | #define I2C_200KHZ 200000 |
| 58 | #define I2C_300KHZ 300000 |
| 59 | #define I2C_400KHZ 400000 |
| 60 | |
| 61 | #define CNS3xxx_I2C_CLK I2C_100KHZ |
| 62 | |
| 63 | #define STATE_DONE 1 |
| 64 | #define STATE_ERROR 2 |
| 65 | |
| 66 | struct cns3xxx_i2c { |
| 67 | struct device *dev; |
| 68 | void __iomem *base; /* virtual */ |
| 69 | wait_queue_head_t wait; |
| 70 | struct i2c_adapter adap; |
| 71 | struct i2c_msg *msg; |
| 72 | u8 state; /* see STATE_ */ |
| 73 | u8 error; /* see TWI_STATUS register */ |
| 74 | int rd_wr_len; |
| 75 | u8 *buf; |
| 76 | }; |
| 77 | |
| 78 | static u32 cns3xxx_i2c_func(struct i2c_adapter *adap) |
| 79 | { |
| 80 | return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; |
| 81 | } |
| 82 | |
| 83 | static int |
| 84 | cns3xxx_i2c_xfer_msg(struct i2c_adapter *adap, struct i2c_msg *msg) |
| 85 | { |
| 86 | struct cns3xxx_i2c *i2c = i2c_get_adapdata(adap); |
| 87 | int i, j; |
| 88 | u8 buf[1] = { 0 }; |
| 89 | |
| 90 | if (msg->len == 0) { |
| 91 | /* |
| 92 | * We are probably doing a probe for a device here, |
| 93 | * so set the length to one, and data to 0 |
| 94 | */ |
| 95 | msg->len = 1; |
| 96 | i2c->buf = buf; |
| 97 | } else { |
| 98 | i2c->buf = msg->buf; |
| 99 | } |
| 100 | |
| 101 | if (msg->flags & I2C_M_TEN) { |
| 102 | printk |
| 103 | ("%s:%d: Presently the driver does not handle extended addressing\n", |
| 104 | __FUNCTION__, __LINE__); |
| 105 | return -EINVAL; |
| 106 | } |
| 107 | i2c->msg = msg; |
| 108 | |
| 109 | for (i = 0; i < msg->len; i++) { |
| 110 | if (msg->len - i >= 4) |
| 111 | i2c->rd_wr_len = 3; |
| 112 | else |
| 113 | i2c->rd_wr_len = msg->len - i - 1; |
| 114 | |
| 115 | // Set Data Width and TWI_EN |
| 116 | I2C_CONTROLLER_REG = 0x80000000 | (i2c->rd_wr_len << 2) | (i2c->rd_wr_len); |
| 117 | |
| 118 | // Clear Write Reg |
| 119 | I2C_WRITE_DATA_REG = 0; |
| 120 | |
| 121 | // Set the slave address |
| 122 | I2C_SLAVE_ADDRESS_REG = (msg->addr << 1); |
| 123 | |
| 124 | // Are we Writing |
| 125 | if (!(msg->flags & I2C_M_RD)) { |
| 126 | I2C_CONTROLLER_REG |= (1 << 4); |
| 127 | if (i != 0) { |
| 128 | /* |
| 129 | * We need to set the address in the first byte. |
| 130 | * The base address is going to be in buf[0] and then |
| 131 | * it needs to be incremented by i - 1. |
| 132 | */ |
| 133 | i2c->buf--; |
| 134 | *i2c->buf = buf[0] + i - 1; |
| 135 | |
| 136 | if (i2c->rd_wr_len < 3) { |
| 137 | i += i2c->rd_wr_len; |
| 138 | i2c->rd_wr_len++; |
| 139 | I2C_CONTROLLER_REG = 0x80000000 | (1 << 4) | (i2c->rd_wr_len << 2) | (i2c->rd_wr_len); |
| 140 | } else { |
| 141 | i += i2c->rd_wr_len - 1; |
| 142 | } |
| 143 | } else { |
| 144 | i += i2c->rd_wr_len; |
| 145 | buf[0] = *i2c->buf; |
| 146 | } |
| 147 | for (j = 0; j <= i2c->rd_wr_len; j++) { |
| 148 | I2C_WRITE_DATA_REG |= ((*i2c->buf++) << (8 * j)); |
| 149 | } |
| 150 | } else { |
| 151 | i += i2c->rd_wr_len; |
| 152 | } |
| 153 | |
| 154 | // Start the Transfer |
| 155 | i2c->state = 0; // Clear out the State |
| 156 | i2c->error = 0; |
| 157 | I2C_CONTROLLER_REG |= (1 << 6); |
| 158 | |
| 159 | if (wait_event_timeout(i2c->wait, (i2c->state == STATE_ERROR) || |
| 160 | (i2c->state == STATE_DONE), TWI_TIMEOUT)) { |
| 161 | if (i2c->state == STATE_ERROR) { |
| 162 | dev_dbg(i2c->dev, "controller error: 0x%2x", i2c->error); |
| 163 | return -EAGAIN; // try again |
| 164 | } |
| 165 | } else { |
| 166 | dev_err(i2c->dev, "controller timed out " |
| 167 | "waiting for start condition to finish\n"); |
| 168 | return -ETIMEDOUT; |
| 169 | } |
| 170 | } |
| 171 | return 0; |
| 172 | } |
| 173 | |
| 174 | static int |
| 175 | cns3xxx_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num) |
| 176 | { |
| 177 | int i; |
| 178 | int ret; |
| 179 | for (i = 0; i < num; i++) |
| 180 | { |
| 181 | ret = cns3xxx_i2c_xfer_msg(adap, &msgs[i]); |
| 182 | if (ret < 0) { |
| 183 | return ret; |
| 184 | } |
| 185 | } |
| 186 | return num; |
| 187 | } |
| 188 | |
| 189 | |
| 190 | static struct i2c_algorithm cns3xxx_i2c_algo = { |
| 191 | .master_xfer = cns3xxx_i2c_xfer, |
| 192 | .functionality = cns3xxx_i2c_func, |
| 193 | }; |
| 194 | |
| 195 | static struct i2c_adapter cns3xxx_i2c_adapter = { |
| 196 | .owner = THIS_MODULE, |
| 197 | .algo = &cns3xxx_i2c_algo, |
| 198 | .algo_data = NULL, |
| 199 | .nr = 0, |
| 200 | .name = "CNS3xxx I2C 0", |
| 201 | .retries = 5, |
| 202 | }; |
| 203 | |
| 204 | static void cns3xxx_i2c_adapter_init(struct cns3xxx_i2c *i2c) |
| 205 | { |
| 206 | cns3xxx_pwr_clk_en(1 << PM_CLK_GATE_REG_OFFSET_SPI_PCM_I2C); |
| 207 | cns3xxx_pwr_power_up(1 << PM_CLK_GATE_REG_OFFSET_SPI_PCM_I2C); |
| 208 | cns3xxx_pwr_soft_rst(1 << PM_CLK_GATE_REG_OFFSET_SPI_PCM_I2C); |
| 209 | |
| 210 | /* Disable the I2C */ |
| 211 | I2C_CONTROLLER_REG = 0; /* Disabled the I2C */ |
| 212 | |
| 213 | //enable SCL and SDA which share pin with GPIOB_PIN_EN(0x18) |
| 214 | //GPIOB[12]: SCL |
| 215 | //GPIOB[13]: SDA |
| 216 | (*(u32*)(CNS3XXX_MISC_BASE_VIRT+0x18)) |= ((1<<12)|(1<<13)); |
| 217 | |
| 218 | MISC_IOCDB_CTRL &= ~0x300; |
| 219 | MISC_IOCDB_CTRL |= 0x300; //21mA... |
| 220 | |
| 221 | /* Check the Reg Dump when testing */ |
| 222 | I2C_TIME_OUT_REG = |
| 223 | ((((((cns3xxx_cpu_clock()*(1000000/8)) / (2 * CNS3xxx_I2C_CLK)) - |
| 224 | 1) & 0x3FF) << 8) | (1 << 7) | 0x7F); |
| 225 | I2C_TWI_OUT_DLY_REG |= 0x3; |
| 226 | |
| 227 | /* Enable The Interrupt */ |
| 228 | CNS3xxx_I2C_ENABLE_INTR(); |
| 229 | |
| 230 | /* Clear Interrupt Status (0x2 | 0x1) */ |
| 231 | I2C_INTERRUPT_STATUS_REG |= (I2C_ACTION_DONE_FLAG | I2C_BUS_ERROR_FLAG); |
| 232 | |
| 233 | /* Enable the I2C Controller */ |
| 234 | CNS3xxx_I2C_ENABLE(); |
| 235 | } |
| 236 | |
| 237 | static irqreturn_t cns3xxx_i2c_isr(int irq, void *dev_id) |
| 238 | { |
| 239 | struct cns3xxx_i2c *i2c = dev_id; |
| 240 | int i; |
| 241 | uint32_t stat = I2C_INTERRUPT_STATUS_REG; |
| 242 | |
| 243 | /* Clear Interrupt */ |
| 244 | I2C_INTERRUPT_STATUS_REG |= 0x1; |
| 245 | |
| 246 | if (stat & I2C_BUS_ERROR_FLAG) { |
| 247 | i2c->state = STATE_ERROR; |
| 248 | i2c->error = (I2C_INTERRUPT_STATUS_REG & 0xff00)>>8; |
| 249 | } else { |
| 250 | if (i2c->msg->flags & I2C_M_RD) { |
| 251 | for (i = 0; i <= i2c->rd_wr_len; i++) |
| 252 | { |
| 253 | *i2c->buf++ = ((I2C_READ_DATA_REG >> (8 * i)) & 0xff); |
| 254 | } |
| 255 | } |
| 256 | i2c->state = STATE_DONE; |
| 257 | } |
| 258 | wake_up(&i2c->wait); |
| 259 | return IRQ_HANDLED; |
| 260 | } |
| 261 | |
| 262 | static int __devinit cns3xxx_i2c_probe(struct platform_device *pdev) |
| 263 | { |
| 264 | struct cns3xxx_i2c *i2c; |
| 265 | struct resource *res, *res2; |
| 266 | int ret; |
| 267 | |
| 268 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
| 269 | if (!res) { |
| 270 | printk("%s: IORESOURCE_MEM not defined \n", __FUNCTION__); |
| 271 | return -ENODEV; |
| 272 | } |
| 273 | |
| 274 | res2 = platform_get_resource(pdev, IORESOURCE_IRQ, 0); |
| 275 | if (!res2) { |
| 276 | printk("%s: IORESOURCE_IRQ not defined \n", __FUNCTION__); |
| 277 | return -ENODEV; |
| 278 | } |
| 279 | |
| 280 | i2c = kzalloc(sizeof(*i2c), GFP_KERNEL); |
| 281 | if (!i2c) |
| 282 | return -ENOMEM; |
| 283 | |
| 284 | if (!request_mem_region(res->start, res->end - res->start + 1, |
| 285 | pdev->name)) { |
| 286 | dev_err(&pdev->dev, "Memory region busy\n"); |
| 287 | ret = -EBUSY; |
| 288 | goto request_mem_failed; |
| 289 | } |
| 290 | |
| 291 | i2c->dev = &pdev->dev; |
| 292 | i2c->base = ioremap(res->start, res->end - res->start + 1); |
| 293 | if (!i2c->base) { |
| 294 | dev_err(&pdev->dev, "Unable to map registers\n"); |
| 295 | ret = -EIO; |
| 296 | goto map_failed; |
| 297 | } |
| 298 | |
| 299 | cns3xxx_i2c_adapter_init(i2c); |
| 300 | |
| 301 | init_waitqueue_head(&i2c->wait); |
| 302 | ret = request_irq(res2->start, cns3xxx_i2c_isr, 0, pdev->name, i2c); |
| 303 | if (ret) { |
| 304 | dev_err(&pdev->dev, "Cannot claim IRQ\n"); |
| 305 | goto request_irq_failed; |
| 306 | } |
| 307 | |
| 308 | platform_set_drvdata(pdev, i2c); |
| 309 | i2c->adap = cns3xxx_i2c_adapter; |
| 310 | i2c_set_adapdata(&i2c->adap, i2c); |
| 311 | i2c->adap.dev.parent = &pdev->dev; |
| 312 | |
| 313 | /* add i2c adapter to i2c tree */ |
| 314 | ret = i2c_add_numbered_adapter(&i2c->adap); |
| 315 | if (ret) { |
| 316 | dev_err(&pdev->dev, "Failed to add adapter\n"); |
| 317 | goto add_adapter_failed; |
| 318 | } |
| 319 | |
| 320 | return 0; |
| 321 | |
| 322 | add_adapter_failed: |
| 323 | free_irq(res2->start, i2c); |
| 324 | request_irq_failed: |
| 325 | iounmap(i2c->base); |
| 326 | map_failed: |
| 327 | release_mem_region(res->start, res->end - res->start + 1); |
| 328 | request_mem_failed: |
| 329 | kfree(i2c); |
| 330 | |
| 331 | return ret; |
| 332 | } |
| 333 | |
| 334 | static int __devexit cns3xxx_i2c_remove(struct platform_device *pdev) |
| 335 | { |
| 336 | struct cns3xxx_i2c *i2c = platform_get_drvdata(pdev); |
| 337 | struct resource *res; |
| 338 | |
| 339 | /* disable i2c logic */ |
| 340 | CNS3xxx_I2C_DISABLE_INTR(); |
| 341 | CNS3xxx_I2C_DISABLE(); |
| 342 | /* remove adapter & data */ |
| 343 | i2c_del_adapter(&i2c->adap); |
| 344 | platform_set_drvdata(pdev, NULL); |
| 345 | |
| 346 | res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); |
| 347 | if (res) |
| 348 | free_irq(res->start, i2c); |
| 349 | |
| 350 | iounmap(i2c->base); |
| 351 | |
| 352 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
| 353 | if (res) |
| 354 | release_mem_region(res->start, res->end - res->start + 1); |
| 355 | |
| 356 | kfree(i2c); |
| 357 | |
| 358 | return 0; |
| 359 | } |
| 360 | |
| 361 | #ifdef CONFIG_PM |
| 362 | #warning "CONFIG_PM defined: suspend and resume not implemented" |
| 363 | #define cns3xxx_i2c_suspend NULL |
| 364 | #define cns3xxx_i2c_resume NULL |
| 365 | #else |
| 366 | #define cns3xxx_i2c_suspend NULL |
| 367 | #define cns3xxx_i2c_resume NULL |
| 368 | #endif |
| 369 | |
| 370 | static struct platform_driver cns3xxx_i2c_driver = { |
| 371 | .probe = cns3xxx_i2c_probe, |
| 372 | .remove = cns3xxx_i2c_remove, |
| 373 | .suspend = cns3xxx_i2c_suspend, |
| 374 | .resume = cns3xxx_i2c_resume, |
| 375 | .driver = { |
| 376 | .owner = THIS_MODULE, |
| 377 | .name = "cns3xxx-i2c", |
| 378 | }, |
| 379 | }; |
| 380 | |
| 381 | static int __init cns3xxx_i2c_init(void) |
| 382 | { |
| 383 | return platform_driver_register(&cns3xxx_i2c_driver); |
| 384 | } |
| 385 | |
| 386 | static void __exit cns3xxx_i2c_exit(void) |
| 387 | { |
| 388 | platform_driver_unregister(&cns3xxx_i2c_driver); |
| 389 | } |
| 390 | |
| 391 | module_init(cns3xxx_i2c_init); |
| 392 | module_exit(cns3xxx_i2c_exit); |
| 393 | |
| 394 | MODULE_AUTHOR("Cavium Networks"); |
| 395 | MODULE_DESCRIPTION("Cavium CNS3XXX I2C Controller"); |
| 396 | MODULE_LICENSE("GPL"); |
| 397 | |
