Root/target/linux/cns3xxx/files/drivers/usb/dwc/otg_cil.h

1/* ==========================================================================
2 * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_cil.h $
3 * $Revision: #91 $
4 * $Date: 2008/09/19 $
5 * $Change: 1099526 $
6 *
7 * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
8 * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
9 * otherwise expressly agreed to in writing between Synopsys and you.
10 *
11 * The Software IS NOT an item of Licensed Software or Licensed Product under
12 * any End User Software License Agreement or Agreement for Licensed Product
13 * with Synopsys or any supplement thereto. You are permitted to use and
14 * redistribute this Software in source and binary forms, with or without
15 * modification, provided that redistributions of source code must retain this
16 * notice. You may not view, use, disclose, copy or distribute this file or
17 * any information contained herein except pursuant to this license grant from
18 * Synopsys. If you do not agree with this notice, including the disclaimer
19 * below, then you are not authorized to use the Software.
20 *
21 * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
25 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
26 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
27 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
28 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
29 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
30 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
31 * DAMAGE.
32 * ========================================================================== */
33
34#if !defined(__DWC_CIL_H__)
35#define __DWC_CIL_H__
36
37#include <linux/workqueue.h>
38#include <linux/version.h>
39#include <asm/param.h>
40//#include <asm/arch/regs-irq.h>
41
42#include "otg_plat.h"
43#include "otg_regs.h"
44#ifdef DEBUG
45#include "linux/timer.h"
46#endif
47
48/**
49 * @file
50 * This file contains the interface to the Core Interface Layer.
51 */
52
53
54/** Macros defined for DWC OTG HW Release verison */
55#define OTG_CORE_REV_2_00 0x4F542000
56#define OTG_CORE_REV_2_60a 0x4F54260A
57#define OTG_CORE_REV_2_71a 0x4F54271A
58#define OTG_CORE_REV_2_72a 0x4F54272A
59
60/**
61*/
62typedef struct iso_pkt_info
63{
64    uint32_t offset;
65    uint32_t length;
66    int32_t status;
67} iso_pkt_info_t;
68/**
69 * The <code>dwc_ep</code> structure represents the state of a single
70 * endpoint when acting in device mode. It contains the data items
71 * needed for an endpoint to be activated and transfer packets.
72 */
73typedef struct dwc_ep
74{
75    /** EP number used for register address lookup */
76    uint8_t num;
77    /** EP direction 0 = OUT */
78    unsigned is_in : 1;
79    /** EP active. */
80    unsigned active : 1;
81
82    /** Periodic Tx FIFO # for IN EPs For INTR EP set to 0 to use non-periodic Tx FIFO
83        If dedicated Tx FIFOs are enabled for all IN Eps - Tx FIFO # FOR IN EPs*/
84    unsigned tx_fifo_num : 4;
85    /** EP type: 0 - Control, 1 - ISOC, 2 - BULK, 3 - INTR */
86    unsigned type : 2;
87#define DWC_OTG_EP_TYPE_CONTROL 0
88#define DWC_OTG_EP_TYPE_ISOC 1
89#define DWC_OTG_EP_TYPE_BULK 2
90#define DWC_OTG_EP_TYPE_INTR 3
91
92    /** DATA start PID for INTR and BULK EP */
93    unsigned data_pid_start : 1;
94    /** Frame (even/odd) for ISOC EP */
95    unsigned even_odd_frame : 1;
96    /** Max Packet bytes */
97    unsigned maxpacket : 11;
98
99    /** Max Transfer size */
100    unsigned maxxfer : 16;
101
102    /** @name Transfer state */
103    /** @{ */
104
105    /**
106     * Pointer to the beginning of the transfer buffer -- do not modify
107     * during transfer.
108     */
109
110    uint32_t dma_addr;
111
112    uint32_t dma_desc_addr;
113    dwc_otg_dma_desc_t* desc_addr;
114
115
116    uint8_t *start_xfer_buff;
117    /** pointer to the transfer buffer */
118    uint8_t *xfer_buff;
119    /** Number of bytes to transfer */
120    unsigned xfer_len : 19;
121    /** Number of bytes transferred. */
122    unsigned xfer_count : 19;
123    /** Sent ZLP */
124    unsigned sent_zlp : 1;
125    /** Total len for control transfer */
126    unsigned total_len : 19;
127
128    /** stall clear flag */
129    unsigned stall_clear_flag : 1;
130
131    /** Allocated DMA Desc count */
132    uint32_t desc_cnt;
133
134    uint32_t aligned_dma_addr;
135    uint32_t aligned_buf_size;
136    uint8_t *aligned_buf;
137
138
139#ifdef DWC_EN_ISOC
140    /**
141     * Variables specific for ISOC EPs
142     *
143     */
144    /** DMA addresses of ISOC buffers */
145    uint32_t dma_addr0;
146    uint32_t dma_addr1;
147
148    uint32_t iso_dma_desc_addr;
149    dwc_otg_dma_desc_t* iso_desc_addr;
150
151    /** pointer to the transfer buffers */
152    uint8_t *xfer_buff0;
153    uint8_t *xfer_buff1;
154
155    /** number of ISOC Buffer is processing */
156    uint32_t proc_buf_num;
157    /** Interval of ISOC Buffer processing */
158    uint32_t buf_proc_intrvl;
159    /** Data size for regular frame */
160    uint32_t data_per_frame;
161
162    /* todo - pattern data support is to be implemented in the future */
163    /** Data size for pattern frame */
164    uint32_t data_pattern_frame;
165    /** Frame number of pattern data */
166    uint32_t sync_frame;
167
168    /** bInterval */
169    uint32_t bInterval;
170    /** ISO Packet number per frame */
171    uint32_t pkt_per_frm;
172    /** Next frame num for which will be setup DMA Desc */
173    uint32_t next_frame;
174    /** Number of packets per buffer processing */
175    uint32_t pkt_cnt;
176    /** Info for all isoc packets */
177    iso_pkt_info_t *pkt_info;
178    /** current pkt number */
179    uint32_t cur_pkt;
180    /** current pkt number */
181    uint8_t *cur_pkt_addr;
182    /** current pkt number */
183    uint32_t cur_pkt_dma_addr;
184#endif //DWC_EN_ISOC
185/** @} */
186} dwc_ep_t;
187
188/*
189 * Reasons for halting a host channel.
190 */
191typedef enum dwc_otg_halt_status
192{
193    DWC_OTG_HC_XFER_NO_HALT_STATUS,
194    DWC_OTG_HC_XFER_COMPLETE,
195    DWC_OTG_HC_XFER_URB_COMPLETE,
196    DWC_OTG_HC_XFER_ACK,
197    DWC_OTG_HC_XFER_NAK,
198    DWC_OTG_HC_XFER_NYET,
199    DWC_OTG_HC_XFER_STALL,
200    DWC_OTG_HC_XFER_XACT_ERR,
201    DWC_OTG_HC_XFER_FRAME_OVERRUN,
202    DWC_OTG_HC_XFER_BABBLE_ERR,
203    DWC_OTG_HC_XFER_DATA_TOGGLE_ERR,
204    DWC_OTG_HC_XFER_AHB_ERR,
205    DWC_OTG_HC_XFER_PERIODIC_INCOMPLETE,
206    DWC_OTG_HC_XFER_URB_DEQUEUE
207} dwc_otg_halt_status_e;
208
209/**
210 * Host channel descriptor. This structure represents the state of a single
211 * host channel when acting in host mode. It contains the data items needed to
212 * transfer packets to an endpoint via a host channel.
213 */
214typedef struct dwc_hc
215{
216    /** Host channel number used for register address lookup */
217    uint8_t hc_num;
218
219    /** Device to access */
220    unsigned dev_addr : 7;
221
222    /** EP to access */
223    unsigned ep_num : 4;
224
225    /** EP direction. 0: OUT, 1: IN */
226    unsigned ep_is_in : 1;
227
228    /**
229     * EP speed.
230     * One of the following values:
231     * - DWC_OTG_EP_SPEED_LOW
232     * - DWC_OTG_EP_SPEED_FULL
233     * - DWC_OTG_EP_SPEED_HIGH
234     */
235    unsigned speed : 2;
236#define DWC_OTG_EP_SPEED_LOW 0
237#define DWC_OTG_EP_SPEED_FULL 1
238#define DWC_OTG_EP_SPEED_HIGH 2
239
240    /**
241     * Endpoint type.
242     * One of the following values:
243     * - DWC_OTG_EP_TYPE_CONTROL: 0
244     * - DWC_OTG_EP_TYPE_ISOC: 1
245     * - DWC_OTG_EP_TYPE_BULK: 2
246     * - DWC_OTG_EP_TYPE_INTR: 3
247     */
248    unsigned ep_type : 2;
249
250    /** Max packet size in bytes */
251    unsigned max_packet : 11;
252
253    /**
254     * PID for initial transaction.
255     * 0: DATA0,<br>
256     * 1: DATA2,<br>
257     * 2: DATA1,<br>
258     * 3: MDATA (non-Control EP),
259     * SETUP (Control EP)
260     */
261    unsigned data_pid_start : 2;
262#define DWC_OTG_HC_PID_DATA0 0
263#define DWC_OTG_HC_PID_DATA2 1
264#define DWC_OTG_HC_PID_DATA1 2
265#define DWC_OTG_HC_PID_MDATA 3
266#define DWC_OTG_HC_PID_SETUP 3
267
268    /** Number of periodic transactions per (micro)frame */
269    unsigned multi_count: 2;
270
271    /** @name Transfer State */
272    /** @{ */
273
274    /** Pointer to the current transfer buffer position. */
275    uint8_t *xfer_buff;
276    /** Total number of bytes to transfer. */
277    uint32_t xfer_len;
278    /** Number of bytes transferred so far. */
279    uint32_t xfer_count;
280    /** Packet count at start of transfer.*/
281    uint16_t start_pkt_count;
282
283    /**
284     * Flag to indicate whether the transfer has been started. Set to 1 if
285     * it has been started, 0 otherwise.
286     */
287    uint8_t xfer_started;
288
289    /**
290     * Set to 1 to indicate that a PING request should be issued on this
291     * channel. If 0, process normally.
292     */
293    uint8_t do_ping;
294
295    /**
296     * Set to 1 to indicate that the error count for this transaction is
297     * non-zero. Set to 0 if the error count is 0.
298     */
299    uint8_t error_state;
300
301    /**
302     * Set to 1 to indicate that this channel should be halted the next
303     * time a request is queued for the channel. This is necessary in
304     * slave mode if no request queue space is available when an attempt
305     * is made to halt the channel.
306     */
307    uint8_t halt_on_queue;
308
309    /**
310     * Set to 1 if the host channel has been halted, but the core is not
311     * finished flushing queued requests. Otherwise 0.
312     */
313    uint8_t halt_pending;
314
315    /**
316     * Reason for halting the host channel.
317     */
318    dwc_otg_halt_status_e halt_status;
319
320    /*
321     * Split settings for the host channel
322     */
323    uint8_t do_split; /**< Enable split for the channel */
324    uint8_t complete_split; /**< Enable complete split */
325    uint8_t hub_addr; /**< Address of high speed hub */
326
327    uint8_t port_addr; /**< Port of the low/full speed device */
328    /** Split transaction position
329     * One of the following values:
330     * - DWC_HCSPLIT_XACTPOS_MID
331     * - DWC_HCSPLIT_XACTPOS_BEGIN
332     * - DWC_HCSPLIT_XACTPOS_END
333     * - DWC_HCSPLIT_XACTPOS_ALL */
334    uint8_t xact_pos;
335
336    /** Set when the host channel does a short read. */
337    uint8_t short_read;
338
339    /**
340     * Number of requests issued for this channel since it was assigned to
341     * the current transfer (not counting PINGs).
342     */
343    uint8_t requests;
344
345    /**
346     * Queue Head for the transfer being processed by this channel.
347     */
348    struct dwc_otg_qh *qh;
349
350    /** @} */
351
352    /** Entry in list of host channels. */
353    struct list_head hc_list_entry;
354} dwc_hc_t;
355
356/**
357 * The following parameters may be specified when starting the module. These
358 * parameters define how the DWC_otg controller should be configured.
359 * Parameter values are passed to the CIL initialization function
360 * dwc_otg_cil_init.
361 */
362typedef struct dwc_otg_core_params
363{
364    int32_t opt;
365#define dwc_param_opt_default 1
366
367    /**
368     * Specifies the OTG capabilities. The driver will automatically
369     * detect the value for this parameter if none is specified.
370     * 0 - HNP and SRP capable (default)
371     * 1 - SRP Only capable
372     * 2 - No HNP/SRP capable
373     */
374    int32_t otg_cap;
375#define DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE 0
376#define DWC_OTG_CAP_PARAM_SRP_ONLY_CAPABLE 1
377#define DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE 2
378//#define dwc_param_otg_cap_default DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE
379#define dwc_param_otg_cap_default DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE
380
381    /**
382     * Specifies whether to use slave or DMA mode for accessing the data
383     * FIFOs. The driver will automatically detect the value for this
384     * parameter if none is specified.
385     * 0 - Slave
386     * 1 - DMA (default, if available)
387     */
388    int32_t dma_enable;
389#define dwc_param_dma_enable_default 1
390
391    /**
392     * When DMA mode is enabled specifies whether to use address DMA or DMA Descritor mode for accessing the data
393     * FIFOs in device mode. The driver will automatically detect the value for this
394     * parameter if none is specified.
395     * 0 - address DMA
396     * 1 - DMA Descriptor(default, if available)
397     */
398    int32_t dma_desc_enable;
399#define dwc_param_dma_desc_enable_default 0
400    /** The DMA Burst size (applicable only for External DMA
401     * Mode). 1, 4, 8 16, 32, 64, 128, 256 (default 32)
402     */
403    int32_t dma_burst_size; /* Translate this to GAHBCFG values */
404//#define dwc_param_dma_burst_size_default 32
405#define dwc_param_dma_burst_size_default 1
406
407    /**
408     * Specifies the maximum speed of operation in host and device mode.
409     * The actual speed depends on the speed of the attached device and
410     * the value of phy_type. The actual speed depends on the speed of the
411     * attached device.
412     * 0 - High Speed (default)
413     * 1 - Full Speed
414     */
415    int32_t speed;
416#define dwc_param_speed_default 0
417#define DWC_SPEED_PARAM_HIGH 0
418#define DWC_SPEED_PARAM_FULL 1
419
420    /** Specifies whether low power mode is supported when attached
421     * to a Full Speed or Low Speed device in host mode.
422     * 0 - Don't support low power mode (default)
423     * 1 - Support low power mode
424     */
425    int32_t host_support_fs_ls_low_power;
426#define dwc_param_host_support_fs_ls_low_power_default 0
427
428    /** Specifies the PHY clock rate in low power mode when connected to a
429     * Low Speed device in host mode. This parameter is applicable only if
430     * HOST_SUPPORT_FS_LS_LOW_POWER is enabled. If PHY_TYPE is set to FS
431     * then defaults to 6 MHZ otherwise 48 MHZ.
432     *
433     * 0 - 48 MHz
434     * 1 - 6 MHz
435     */
436    int32_t host_ls_low_power_phy_clk;
437#define dwc_param_host_ls_low_power_phy_clk_default 0
438#define DWC_HOST_LS_LOW_POWER_PHY_CLK_PARAM_48MHZ 0
439#define DWC_HOST_LS_LOW_POWER_PHY_CLK_PARAM_6MHZ 1
440
441    /**
442     * 0 - Use cC FIFO size parameters
443     * 1 - Allow dynamic FIFO sizing (default)
444     */
445    int32_t enable_dynamic_fifo;
446#define dwc_param_enable_dynamic_fifo_default 1
447
448    /** Total number of 4-byte words in the data FIFO memory. This
449     * memory includes the Rx FIFO, non-periodic Tx FIFO, and periodic
450     * Tx FIFOs.
451     * 32 to 32768 (default 8192)
452     * Note: The total FIFO memory depth in the FPGA configuration is 8192.
453     */
454    int32_t data_fifo_size;
455#define dwc_param_data_fifo_size_default 8192
456
457    /** Number of 4-byte words in the Rx FIFO in device mode when dynamic
458     * FIFO sizing is enabled.
459     * 16 to 32768 (default 1064)
460     */
461    int32_t dev_rx_fifo_size;
462//#define dwc_param_dev_rx_fifo_size_default 1064
463#define dwc_param_dev_rx_fifo_size_default 0x100
464
465    /**
466     * Specifies whether dedicated transmit FIFOs are
467     * enabled for non periodic IN endpoints in device mode
468     * 0 - No
469     * 1 - Yes
470     */
471     int32_t en_multiple_tx_fifo;
472#define dwc_param_en_multiple_tx_fifo_default 1
473
474    /** Number of 4-byte words in each of the Tx FIFOs in device
475     * mode when dynamic FIFO sizing is enabled.
476     * 4 to 768 (default 256)
477     */
478    uint32_t dev_tx_fifo_size[MAX_TX_FIFOS];
479//#define dwc_param_dev_tx_fifo_size_default 256
480#define dwc_param_dev_tx_fifo_size_default 0x80
481
482    /** Number of 4-byte words in the non-periodic Tx FIFO in device mode
483     * when dynamic FIFO sizing is enabled.
484     * 16 to 32768 (default 1024)
485     */
486    int32_t dev_nperio_tx_fifo_size;
487//#define dwc_param_dev_nperio_tx_fifo_size_default 1024
488#define dwc_param_dev_nperio_tx_fifo_size_default 0x80
489
490    /** Number of 4-byte words in each of the periodic Tx FIFOs in device
491     * mode when dynamic FIFO sizing is enabled.
492     * 4 to 768 (default 256)
493     */
494    uint32_t dev_perio_tx_fifo_size[MAX_PERIO_FIFOS];
495//#define dwc_param_dev_perio_tx_fifo_size_default 256
496#define dwc_param_dev_perio_tx_fifo_size_default 0x80
497
498    /** Number of 4-byte words in the Rx FIFO in host mode when dynamic
499     * FIFO sizing is enabled.
500     * 16 to 32768 (default 1024)
501     */
502    int32_t host_rx_fifo_size;
503//#define dwc_param_host_rx_fifo_size_default 1024
504#define dwc_param_host_rx_fifo_size_default 0x292
505
506    /** Number of 4-byte words in the non-periodic Tx FIFO in host mode
507     * when Dynamic FIFO sizing is enabled in the core.
508     * 16 to 32768 (default 1024)
509     */
510    int32_t host_nperio_tx_fifo_size;
511//#define dwc_param_host_nperio_tx_fifo_size_default 1024
512//#define dwc_param_host_nperio_tx_fifo_size_default 0x292
513#define dwc_param_host_nperio_tx_fifo_size_default 0x80
514
515    /** Number of 4-byte words in the host periodic Tx FIFO when dynamic
516     * FIFO sizing is enabled.
517     * 16 to 32768 (default 1024)
518     */
519    int32_t host_perio_tx_fifo_size;
520//#define dwc_param_host_perio_tx_fifo_size_default 1024
521#define dwc_param_host_perio_tx_fifo_size_default 0x292
522
523    /** The maximum transfer size supported in bytes.
524     * 2047 to 65,535 (default 65,535)
525     */
526    int32_t max_transfer_size;
527#define dwc_param_max_transfer_size_default 65535
528
529    /** The maximum number of packets in a transfer.
530     * 15 to 511 (default 511)
531     */
532    int32_t max_packet_count;
533#define dwc_param_max_packet_count_default 511
534
535    /** The number of host channel registers to use.
536     * 1 to 16 (default 12)
537     * Note: The FPGA configuration supports a maximum of 12 host channels.
538     */
539    int32_t host_channels;
540//#define dwc_param_host_channels_default 12
541#define dwc_param_host_channels_default 16
542
543    /** The number of endpoints in addition to EP0 available for device
544     * mode operations.
545     * 1 to 15 (default 6 IN and OUT)
546     * Note: The FPGA configuration supports a maximum of 6 IN and OUT
547     * endpoints in addition to EP0.
548     */
549    int32_t dev_endpoints;
550//#define dwc_param_dev_endpoints_default 6
551#define dwc_param_dev_endpoints_default 8
552
553        /**
554         * Specifies the type of PHY interface to use. By default, the driver
555         * will automatically detect the phy_type.
556         *
557         * 0 - Full Speed PHY
558         * 1 - UTMI+ (default)
559         * 2 - ULPI
560         */
561    int32_t phy_type;
562#define DWC_PHY_TYPE_PARAM_FS 0
563#define DWC_PHY_TYPE_PARAM_UTMI 1
564#define DWC_PHY_TYPE_PARAM_ULPI 2
565#define dwc_param_phy_type_default DWC_PHY_TYPE_PARAM_UTMI
566
567    /**
568     * Specifies the UTMI+ Data Width. This parameter is
569     * applicable for a PHY_TYPE of UTMI+ or ULPI. (For a ULPI
570     * PHY_TYPE, this parameter indicates the data width between
571     * the MAC and the ULPI Wrapper.) Also, this parameter is
572     * applicable only if the OTG_HSPHY_WIDTH cC parameter was set
573     * to "8 and 16 bits", meaning that the core has been
574     * configured to work at either data path width.
575     *
576     * 8 or 16 bits (default 16)
577     */
578    int32_t phy_utmi_width;
579#define dwc_param_phy_utmi_width_default 16
580
581    /**
582     * Specifies whether the ULPI operates at double or single
583     * data rate. This parameter is only applicable if PHY_TYPE is
584     * ULPI.
585     *
586     * 0 - single data rate ULPI interface with 8 bit wide data
587     * bus (default)
588     * 1 - double data rate ULPI interface with 4 bit wide data
589     * bus
590     */
591    int32_t phy_ulpi_ddr;
592#define dwc_param_phy_ulpi_ddr_default 0
593
594    /**
595     * Specifies whether to use the internal or external supply to
596     * drive the vbus with a ULPI phy.
597     */
598    int32_t phy_ulpi_ext_vbus;
599#define DWC_PHY_ULPI_INTERNAL_VBUS 0
600#define DWC_PHY_ULPI_EXTERNAL_VBUS 1
601#define dwc_param_phy_ulpi_ext_vbus_default DWC_PHY_ULPI_INTERNAL_VBUS
602
603    /**
604     * Specifies whether to use the I2Cinterface for full speed PHY. This
605     * parameter is only applicable if PHY_TYPE is FS.
606     * 0 - No (default)
607     * 1 - Yes
608     */
609    int32_t i2c_enable;
610#define dwc_param_i2c_enable_default 0
611
612    int32_t ulpi_fs_ls;
613#define dwc_param_ulpi_fs_ls_default 0
614
615    int32_t ts_dline;
616#define dwc_param_ts_dline_default 0
617
618    /** Thresholding enable flag-
619     * bit 0 - enable non-ISO Tx thresholding
620     * bit 1 - enable ISO Tx thresholding
621     * bit 2 - enable Rx thresholding
622     */
623    uint32_t thr_ctl;
624#define dwc_param_thr_ctl_default 0
625
626    /** Thresholding length for Tx
627     * FIFOs in 32 bit DWORDs
628     */
629    uint32_t tx_thr_length;
630#define dwc_param_tx_thr_length_default 64
631
632    /** Thresholding length for Rx
633     * FIFOs in 32 bit DWORDs
634     */
635    uint32_t rx_thr_length;
636#define dwc_param_rx_thr_length_default 64
637
638    /** Per Transfer Interrupt
639     * mode enable flag
640     * 1 - Enabled
641     * 0 - Disabled
642     */
643    uint32_t pti_enable;
644#define dwc_param_pti_enable_default 0
645
646    /** Molti Processor Interrupt
647     * mode enable flag
648     * 1 - Enabled
649     * 0 - Disabled
650     */
651    uint32_t mpi_enable;
652#define dwc_param_mpi_enable_default 0
653
654} dwc_otg_core_params_t;
655
656#ifdef DEBUG
657struct dwc_otg_core_if;
658typedef struct hc_xfer_info
659{
660    struct dwc_otg_core_if *core_if;
661    dwc_hc_t *hc;
662} hc_xfer_info_t;
663#endif
664
665/**
666 * The <code>dwc_otg_core_if</code> structure contains information needed to manage
667 * the DWC_otg controller acting in either host or device mode. It
668 * represents the programming view of the controller as a whole.
669 */
670typedef struct dwc_otg_core_if
671{
672    /** Parameters that define how the core should be configured.*/
673    dwc_otg_core_params_t *core_params;
674
675    /** Core Global registers starting at offset 000h. */
676    dwc_otg_core_global_regs_t *core_global_regs;
677
678    /** Device-specific information */
679    dwc_otg_dev_if_t *dev_if;
680    /** Host-specific information */
681    dwc_otg_host_if_t *host_if;
682
683    /** Value from SNPSID register */
684    uint32_t snpsid;
685
686    /*
687     * Set to 1 if the core PHY interface bits in USBCFG have been
688     * initialized.
689     */
690    uint8_t phy_init_done;
691
692    /*
693     * SRP Success flag, set by srp success interrupt in FS I2C mode
694     */
695    uint8_t srp_success;
696    uint8_t srp_timer_started;
697
698    /* Common configuration information */
699    /** Power and Clock Gating Control Register */
700    volatile uint32_t *pcgcctl;
701#define DWC_OTG_PCGCCTL_OFFSET 0xE00
702
703    /** Push/pop addresses for endpoints or host channels.*/
704    uint32_t *data_fifo[MAX_EPS_CHANNELS];
705#define DWC_OTG_DATA_FIFO_OFFSET 0x1000
706#define DWC_OTG_DATA_FIFO_SIZE 0x1000
707
708    /** Total RAM for FIFOs (Bytes) */
709    uint16_t total_fifo_size;
710    /** Size of Rx FIFO (Bytes) */
711    uint16_t rx_fifo_size;
712    /** Size of Non-periodic Tx FIFO (Bytes) */
713    uint16_t nperio_tx_fifo_size;
714
715
716    /** 1 if DMA is enabled, 0 otherwise. */
717    uint8_t dma_enable;
718
719    /** 1 if Descriptor DMA mode is enabled, 0 otherwise. */
720    uint8_t dma_desc_enable;
721
722    /** 1 if PTI Enhancement mode is enabled, 0 otherwise. */
723    uint8_t pti_enh_enable;
724
725    /** 1 if MPI Enhancement mode is enabled, 0 otherwise. */
726    uint8_t multiproc_int_enable;
727
728    /** 1 if dedicated Tx FIFOs are enabled, 0 otherwise. */
729    uint8_t en_multiple_tx_fifo;
730
731    /** Set to 1 if multiple packets of a high-bandwidth transfer is in
732     * process of being queued */
733    uint8_t queuing_high_bandwidth;
734
735    /** Hardware Configuration -- stored here for convenience.*/
736    hwcfg1_data_t hwcfg1;
737    hwcfg2_data_t hwcfg2;
738    hwcfg3_data_t hwcfg3;
739    hwcfg4_data_t hwcfg4;
740
741    /** Host and Device Configuration -- stored here for convenience.*/
742    hcfg_data_t hcfg;
743    dcfg_data_t dcfg;
744
745    /** The operational State, during transations
746     * (a_host>>a_peripherial and b_device=>b_host) this may not
747     * match the core but allows the software to determine
748     * transitions.
749     */
750    uint8_t op_state;
751
752    /**
753     * Set to 1 if the HCD needs to be restarted on a session request
754     * interrupt. This is required if no connector ID status change has
755     * occurred since the HCD was last disconnected.
756     */
757    uint8_t restart_hcd_on_session_req;
758
759    /** HCD callbacks */
760    /** A-Device is a_host */
761#define A_HOST (1)
762    /** A-Device is a_suspend */
763#define A_SUSPEND (2)
764    /** A-Device is a_peripherial */
765#define A_PERIPHERAL (3)
766    /** B-Device is operating as a Peripheral. */
767#define B_PERIPHERAL (4)
768    /** B-Device is operating as a Host. */
769#define B_HOST (5)
770
771    /** HCD callbacks */
772    struct dwc_otg_cil_callbacks *hcd_cb;
773    /** PCD callbacks */
774    struct dwc_otg_cil_callbacks *pcd_cb;
775
776    /** Device mode Periodic Tx FIFO Mask */
777    uint32_t p_tx_msk;
778    /** Device mode Periodic Tx FIFO Mask */
779    uint32_t tx_msk;
780
781    /** Workqueue object used for handling several interrupts */
782    struct workqueue_struct *wq_otg;
783
784    /** Work object used for handling "Connector ID Status Change" Interrupt */
785    struct work_struct w_conn_id;
786
787    /** Work object used for handling "Wakeup Detected" Interrupt */
788    struct delayed_work w_wkp;
789
790#ifdef DEBUG
791    uint32_t start_hcchar_val[MAX_EPS_CHANNELS];
792
793    hc_xfer_info_t hc_xfer_info[MAX_EPS_CHANNELS];
794    struct timer_list hc_xfer_timer[MAX_EPS_CHANNELS];
795
796    uint32_t hfnum_7_samples;
797    uint64_t hfnum_7_frrem_accum;
798    uint32_t hfnum_0_samples;
799    uint64_t hfnum_0_frrem_accum;
800    uint32_t hfnum_other_samples;
801    uint64_t hfnum_other_frrem_accum;
802#endif
803
804
805} dwc_otg_core_if_t;
806
807/*We must clear S3C24XX_EINTPEND external interrupt register
808 * because after clearing in this register trigerred IRQ from
809 * H/W core in kernel interrupt can be occured again before OTG
810 * handlers clear all IRQ sources of Core registers because of
811 * timing latencies and Low Level IRQ Type.
812 */
813
814#ifdef CONFIG_MACH_IPMATE
815#define S3C2410X_CLEAR_EINTPEND() \
816do { \
817    if (!dwc_otg_read_core_intr(core_if)) { \
818    __raw_writel(1UL << 11,S3C24XX_EINTPEND); \
819    } \
820} while (0)
821#else
822#define S3C2410X_CLEAR_EINTPEND() do { } while (0)
823#endif
824
825/*
826 * The following functions are functions for works
827 * using during handling some interrupts
828 */
829extern void w_conn_id_status_change(struct work_struct *p);
830extern void w_wakeup_detected(struct work_struct *p);
831
832
833/*
834 * The following functions support initialization of the CIL driver component
835 * and the DWC_otg controller.
836 */
837extern dwc_otg_core_if_t *dwc_otg_cil_init(const uint32_t *_reg_base_addr,
838                       dwc_otg_core_params_t *_core_params);
839extern void dwc_otg_cil_remove(dwc_otg_core_if_t *_core_if);
840extern void dwc_otg_core_init(dwc_otg_core_if_t *_core_if);
841extern void dwc_otg_core_host_init(dwc_otg_core_if_t *_core_if);
842extern void dwc_otg_core_dev_init(dwc_otg_core_if_t *_core_if);
843extern void dwc_otg_enable_global_interrupts( dwc_otg_core_if_t *_core_if );
844extern void dwc_otg_disable_global_interrupts( dwc_otg_core_if_t *_core_if );
845
846/** @name Device CIL Functions
847 * The following functions support managing the DWC_otg controller in device
848 * mode.
849 */
850/**@{*/
851extern void dwc_otg_wakeup(dwc_otg_core_if_t *_core_if);
852extern void dwc_otg_read_setup_packet (dwc_otg_core_if_t *_core_if, uint32_t *_dest);
853extern uint32_t dwc_otg_get_frame_number(dwc_otg_core_if_t *_core_if);
854extern void dwc_otg_ep0_activate(dwc_otg_core_if_t *_core_if, dwc_ep_t *_ep);
855extern void dwc_otg_ep_activate(dwc_otg_core_if_t *_core_if, dwc_ep_t *_ep);
856extern void dwc_otg_ep_deactivate(dwc_otg_core_if_t *_core_if, dwc_ep_t *_ep);
857extern void dwc_otg_ep_start_transfer(dwc_otg_core_if_t *_core_if, dwc_ep_t *_ep);
858extern void dwc_otg_ep_start_zl_transfer(dwc_otg_core_if_t *_core_if, dwc_ep_t *_ep);
859extern void dwc_otg_ep0_start_transfer(dwc_otg_core_if_t *_core_if, dwc_ep_t *_ep);
860extern void dwc_otg_ep0_continue_transfer(dwc_otg_core_if_t *_core_if, dwc_ep_t *_ep);
861extern void dwc_otg_ep_write_packet(dwc_otg_core_if_t *_core_if, dwc_ep_t *_ep, int _dma);
862extern void dwc_otg_ep_set_stall(dwc_otg_core_if_t *_core_if, dwc_ep_t *_ep);
863extern void dwc_otg_ep_clear_stall(dwc_otg_core_if_t *_core_if, dwc_ep_t *_ep);
864extern void dwc_otg_enable_device_interrupts(dwc_otg_core_if_t *_core_if);
865extern void dwc_otg_dump_dev_registers(dwc_otg_core_if_t *_core_if);
866extern void dwc_otg_dump_spram(dwc_otg_core_if_t *_core_if);
867#ifdef DWC_EN_ISOC
868extern void dwc_otg_iso_ep_start_frm_transfer(dwc_otg_core_if_t *core_if, dwc_ep_t *ep);
869extern void dwc_otg_iso_ep_start_buf_transfer(dwc_otg_core_if_t *core_if, dwc_ep_t *ep);
870#endif //DWC_EN_ISOC
871/**@}*/
872
873/** @name Host CIL Functions
874 * The following functions support managing the DWC_otg controller in host
875 * mode.
876 */
877/**@{*/
878extern void dwc_otg_hc_init(dwc_otg_core_if_t *_core_if, dwc_hc_t *_hc);
879extern void dwc_otg_hc_halt(dwc_otg_core_if_t *_core_if,
880                dwc_hc_t *_hc,
881                dwc_otg_halt_status_e _halt_status);
882extern void dwc_otg_hc_cleanup(dwc_otg_core_if_t *_core_if, dwc_hc_t *_hc);
883extern void dwc_otg_hc_start_transfer(dwc_otg_core_if_t *_core_if, dwc_hc_t *_hc);
884extern int dwc_otg_hc_continue_transfer(dwc_otg_core_if_t *_core_if, dwc_hc_t *_hc);
885extern void dwc_otg_hc_do_ping(dwc_otg_core_if_t *_core_if, dwc_hc_t *_hc);
886extern void dwc_otg_hc_write_packet(dwc_otg_core_if_t *_core_if, dwc_hc_t *_hc);
887extern void dwc_otg_enable_host_interrupts(dwc_otg_core_if_t *_core_if);
888extern void dwc_otg_disable_host_interrupts(dwc_otg_core_if_t *_core_if);
889
890/**
891 * This function Reads HPRT0 in preparation to modify. It keeps the
892 * WC bits 0 so that if they are read as 1, they won't clear when you
893 * write it back
894 */
895static inline uint32_t dwc_otg_read_hprt0(dwc_otg_core_if_t *_core_if)
896{
897    hprt0_data_t hprt0;
898    hprt0.d32 = dwc_read_reg32(_core_if->host_if->hprt0);
899    hprt0.b.prtena = 0;
900    hprt0.b.prtconndet = 0;
901    hprt0.b.prtenchng = 0;
902    hprt0.b.prtovrcurrchng = 0;
903    return hprt0.d32;
904}
905
906extern void dwc_otg_dump_host_registers(dwc_otg_core_if_t *_core_if);
907/**@}*/
908
909/** @name Common CIL Functions
910 * The following functions support managing the DWC_otg controller in either
911 * device or host mode.
912 */
913/**@{*/
914
915extern void dwc_otg_read_packet(dwc_otg_core_if_t *core_if,
916                uint8_t *dest,
917                uint16_t bytes);
918
919extern void dwc_otg_dump_global_registers(dwc_otg_core_if_t *_core_if);
920
921extern void dwc_otg_flush_tx_fifo( dwc_otg_core_if_t *_core_if,
922                                   const int _num );
923extern void dwc_otg_flush_rx_fifo( dwc_otg_core_if_t *_core_if );
924extern void dwc_otg_core_reset( dwc_otg_core_if_t *_core_if );
925
926extern dwc_otg_dma_desc_t* dwc_otg_ep_alloc_desc_chain(uint32_t * dma_desc_addr, uint32_t count);
927extern void dwc_otg_ep_free_desc_chain(dwc_otg_dma_desc_t* desc_addr, uint32_t dma_desc_addr, uint32_t count);
928
929/**
930 * This function returns the Core Interrupt register.
931 */
932static inline uint32_t dwc_otg_read_core_intr(dwc_otg_core_if_t *_core_if)
933{
934    return (dwc_read_reg32(&_core_if->core_global_regs->gintsts) &
935        dwc_read_reg32(&_core_if->core_global_regs->gintmsk));
936}
937
938/**
939 * This function returns the OTG Interrupt register.
940 */
941static inline uint32_t dwc_otg_read_otg_intr (dwc_otg_core_if_t *_core_if)
942{
943    return (dwc_read_reg32 (&_core_if->core_global_regs->gotgint));
944}
945
946/**
947 * This function reads the Device All Endpoints Interrupt register and
948 * returns the IN endpoint interrupt bits.
949 */
950static inline uint32_t dwc_otg_read_dev_all_in_ep_intr(dwc_otg_core_if_t *core_if)
951{
952    uint32_t v;
953
954    if(core_if->multiproc_int_enable) {
955        v = dwc_read_reg32(&core_if->dev_if->dev_global_regs->deachint) &
956                dwc_read_reg32(&core_if->dev_if->dev_global_regs->deachintmsk);
957    } else {
958        v = dwc_read_reg32(&core_if->dev_if->dev_global_regs->daint) &
959                dwc_read_reg32(&core_if->dev_if->dev_global_regs->daintmsk);
960    }
961    return (v & 0xffff);
962
963}
964
965/**
966 * This function reads the Device All Endpoints Interrupt register and
967 * returns the OUT endpoint interrupt bits.
968 */
969static inline uint32_t dwc_otg_read_dev_all_out_ep_intr(dwc_otg_core_if_t *core_if)
970{
971    uint32_t v;
972
973    if(core_if->multiproc_int_enable) {
974        v = dwc_read_reg32(&core_if->dev_if->dev_global_regs->deachint) &
975                dwc_read_reg32(&core_if->dev_if->dev_global_regs->deachintmsk);
976    } else {
977        v = dwc_read_reg32(&core_if->dev_if->dev_global_regs->daint) &
978                dwc_read_reg32(&core_if->dev_if->dev_global_regs->daintmsk);
979    }
980
981    return ((v & 0xffff0000) >> 16);
982}
983
984/**
985 * This function returns the Device IN EP Interrupt register
986 */
987static inline uint32_t dwc_otg_read_dev_in_ep_intr(dwc_otg_core_if_t *core_if,
988                            dwc_ep_t *ep)
989{
990    dwc_otg_dev_if_t *dev_if = core_if->dev_if;
991    uint32_t v, msk, emp;
992
993    if(core_if->multiproc_int_enable) {
994        msk = dwc_read_reg32(&dev_if->dev_global_regs->diepeachintmsk[ep->num]);
995        emp = dwc_read_reg32(&dev_if->dev_global_regs->dtknqr4_fifoemptymsk);
996        msk |= ((emp >> ep->num) & 0x1) << 7;
997        v = dwc_read_reg32(&dev_if->in_ep_regs[ep->num]->diepint) & msk;
998    } else {
999        msk = dwc_read_reg32(&dev_if->dev_global_regs->diepmsk);
1000        emp = dwc_read_reg32(&dev_if->dev_global_regs->dtknqr4_fifoemptymsk);
1001        msk |= ((emp >> ep->num) & 0x1) << 7;
1002        v = dwc_read_reg32(&dev_if->in_ep_regs[ep->num]->diepint) & msk;
1003    }
1004
1005
1006    return v;
1007}
1008/**
1009 * This function returns the Device OUT EP Interrupt register
1010 */
1011static inline uint32_t dwc_otg_read_dev_out_ep_intr(dwc_otg_core_if_t *_core_if,
1012                            dwc_ep_t *_ep)
1013{
1014    dwc_otg_dev_if_t *dev_if = _core_if->dev_if;
1015    uint32_t v;
1016    doepmsk_data_t msk = { .d32 = 0 };
1017
1018    if(_core_if->multiproc_int_enable) {
1019        msk.d32 = dwc_read_reg32(&dev_if->dev_global_regs->doepeachintmsk[_ep->num]);
1020        if(_core_if->pti_enh_enable) {
1021            msk.b.pktdrpsts = 1;
1022        }
1023        v = dwc_read_reg32( &dev_if->out_ep_regs[_ep->num]->doepint) & msk.d32;
1024    } else {
1025        msk.d32 = dwc_read_reg32(&dev_if->dev_global_regs->doepmsk);
1026        if(_core_if->pti_enh_enable) {
1027            msk.b.pktdrpsts = 1;
1028        }
1029        v = dwc_read_reg32( &dev_if->out_ep_regs[_ep->num]->doepint) & msk.d32;
1030    }
1031    return v;
1032}
1033
1034/**
1035 * This function returns the Host All Channel Interrupt register
1036 */
1037static inline uint32_t dwc_otg_read_host_all_channels_intr (dwc_otg_core_if_t *_core_if)
1038{
1039    return (dwc_read_reg32 (&_core_if->host_if->host_global_regs->haint));
1040}
1041
1042static inline uint32_t dwc_otg_read_host_channel_intr (dwc_otg_core_if_t *_core_if, dwc_hc_t *_hc)
1043{
1044    return (dwc_read_reg32 (&_core_if->host_if->hc_regs[_hc->hc_num]->hcint));
1045}
1046
1047
1048/**
1049 * This function returns the mode of the operation, host or device.
1050 *
1051 * @return 0 - Device Mode, 1 - Host Mode
1052 */
1053static inline uint32_t dwc_otg_mode(dwc_otg_core_if_t *_core_if)
1054{
1055    return (dwc_read_reg32( &_core_if->core_global_regs->gintsts ) & 0x1);
1056}
1057
1058static inline uint8_t dwc_otg_is_device_mode(dwc_otg_core_if_t *_core_if)
1059{
1060    return (dwc_otg_mode(_core_if) != DWC_HOST_MODE);
1061}
1062static inline uint8_t dwc_otg_is_host_mode(dwc_otg_core_if_t *_core_if)
1063{
1064    return (dwc_otg_mode(_core_if) == DWC_HOST_MODE);
1065}
1066
1067extern int32_t dwc_otg_handle_common_intr( dwc_otg_core_if_t *_core_if );
1068
1069
1070/**@}*/
1071
1072/**
1073 * DWC_otg CIL callback structure. This structure allows the HCD and
1074 * PCD to register functions used for starting and stopping the PCD
1075 * and HCD for role change on for a DRD.
1076 */
1077typedef struct dwc_otg_cil_callbacks
1078{
1079    /** Start function for role change */
1080    int (*start) (void *_p);
1081    /** Stop Function for role change */
1082    int (*stop) (void *_p);
1083    /** Disconnect Function for role change */
1084    int (*disconnect) (void *_p);
1085    /** Resume/Remote wakeup Function */
1086    int (*resume_wakeup) (void *_p);
1087    /** Suspend function */
1088    int (*suspend) (void *_p);
1089    /** Session Start (SRP) */
1090    int (*session_start) (void *_p);
1091    /** Pointer passed to start() and stop() */
1092    void *p;
1093} dwc_otg_cil_callbacks_t;
1094
1095extern void dwc_otg_cil_register_pcd_callbacks( dwc_otg_core_if_t *_core_if,
1096                        dwc_otg_cil_callbacks_t *_cb,
1097                        void *_p);
1098extern void dwc_otg_cil_register_hcd_callbacks( dwc_otg_core_if_t *_core_if,
1099                        dwc_otg_cil_callbacks_t *_cb,
1100                        void *_p);
1101#ifndef warn
1102#define warn printk
1103#endif
1104
1105#endif
1106
1107

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