Root/target/linux/cns3xxx/files/drivers/usb/dwc/otg_driver.c

1/* ==========================================================================
2 * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_driver.c $
3 * $Revision: #63 $
4 * $Date: 2008/09/24 $
5 * $Change: 1101777 $
6 *
7 * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
8 * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
9 * otherwise expressly agreed to in writing between Synopsys and you.
10 *
11 * The Software IS NOT an item of Licensed Software or Licensed Product under
12 * any End User Software License Agreement or Agreement for Licensed Product
13 * with Synopsys or any supplement thereto. You are permitted to use and
14 * redistribute this Software in source and binary forms, with or without
15 * modification, provided that redistributions of source code must retain this
16 * notice. You may not view, use, disclose, copy or distribute this file or
17 * any information contained herein except pursuant to this license grant from
18 * Synopsys. If you do not agree with this notice, including the disclaimer
19 * below, then you are not authorized to use the Software.
20 *
21 * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
25 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
26 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
27 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
28 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
29 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
30 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
31 * DAMAGE.
32 * ========================================================================== */
33
34/** @file
35 * The dwc_otg_driver module provides the initialization and cleanup entry
36 * points for the DWC_otg driver. This module will be dynamically installed
37 * after Linux is booted using the insmod command. When the module is
38 * installed, the dwc_otg_driver_init function is called. When the module is
39 * removed (using rmmod), the dwc_otg_driver_cleanup function is called.
40 *
41 * This module also defines a data structure for the dwc_otg_driver, which is
42 * used in conjunction with the standard ARM lm_device structure. These
43 * structures allow the OTG driver to comply with the standard Linux driver
44 * model in which devices and drivers are registered with a bus driver. This
45 * has the benefit that Linux can expose attributes of the driver and device
46 * in its special sysfs file system. Users can then read or write files in
47 * this file system to perform diagnostics on the driver components or the
48 * device.
49 */
50
51#include <linux/kernel.h>
52#include <linux/module.h>
53#include <linux/moduleparam.h>
54#include <linux/init.h>
55#include <linux/device.h>
56#include <linux/errno.h>
57#include <linux/types.h>
58#include <linux/stat.h> /* permission constants */
59#include <linux/version.h>
60#include <linux/platform_device.h>
61#include <linux/io.h>
62#include <linux/irq.h>
63#include <asm/io.h>
64
65#include <asm/sizes.h>
66#include <mach/pm.h>
67
68#include "otg_plat.h"
69#include "otg_attr.h"
70#include "otg_driver.h"
71#include "otg_cil.h"
72#include "otg_pcd.h"
73#include "otg_hcd.h"
74
75#define DWC_DRIVER_VERSION "2.72a 24-JUN-2008"
76#define DWC_DRIVER_DESC "HS OTG USB Controller driver"
77
78static const char dwc_driver_name[] = "dwc_otg";
79
80/*-------------------------------------------------------------------------*/
81/* Encapsulate the module parameter settings */
82
83static dwc_otg_core_params_t dwc_otg_module_params = {
84    .opt = -1,
85    .otg_cap = -1,
86    .dma_enable = -1,
87    .dma_desc_enable = -1,
88    .dma_burst_size = -1,
89    .speed = -1,
90    .host_support_fs_ls_low_power = -1,
91    .host_ls_low_power_phy_clk = -1,
92    .enable_dynamic_fifo = -1,
93    .data_fifo_size = -1,
94    .dev_rx_fifo_size = -1,
95    .dev_nperio_tx_fifo_size = -1,
96    .dev_perio_tx_fifo_size = {
97        /* dev_perio_tx_fifo_size_1 */
98        -1,
99        -1,
100        -1,
101        -1,
102        -1,
103        -1,
104        -1,
105        -1,
106        -1,
107        -1,
108        -1,
109        -1,
110        -1,
111        -1,
112        -1
113        /* 15 */
114    },
115    .host_rx_fifo_size = -1,
116    .host_nperio_tx_fifo_size = -1,
117    .host_perio_tx_fifo_size = -1,
118    .max_transfer_size = -1,
119    .max_packet_count = -1,
120    .host_channels = -1,
121    .dev_endpoints = -1,
122    .phy_type = -1,
123    .phy_utmi_width = -1,
124    .phy_ulpi_ddr = -1,
125    .phy_ulpi_ext_vbus = -1,
126    .i2c_enable = -1,
127    .ulpi_fs_ls = -1,
128    .ts_dline = -1,
129    .en_multiple_tx_fifo = -1,
130    .dev_tx_fifo_size = {
131        /* dev_tx_fifo_size */
132        -1,
133        -1,
134        -1,
135        -1,
136        -1,
137        -1,
138        -1,
139        -1,
140        -1,
141        -1,
142        -1,
143        -1,
144        -1,
145        -1,
146        -1
147        /* 15 */
148    },
149    .thr_ctl = -1,
150    .tx_thr_length = -1,
151    .rx_thr_length = -1,
152    .pti_enable = -1,
153    .mpi_enable = -1,
154};
155
156/**
157 * Global Debug Level Mask.
158 */
159uint32_t g_dbg_lvl = 0; /* OFF */
160
161/**
162 * This function is called during module intialization to verify that
163 * the module parameters are in a valid state.
164 */
165static int check_parameters(dwc_otg_core_if_t *core_if)
166{
167    int i;
168    int retval = 0;
169
170/* Checks if the parameter is outside of its valid range of values */
171#define DWC_OTG_PARAM_TEST(_param_, _low_, _high_) \
172        ((dwc_otg_module_params._param_ < (_low_)) || \
173        (dwc_otg_module_params._param_ > (_high_)))
174
175/* If the parameter has been set by the user, check that the parameter value is
176 * within the value range of values. If not, report a module error. */
177#define DWC_OTG_PARAM_ERR(_param_, _low_, _high_, _string_) \
178        do { \
179            if (dwc_otg_module_params._param_ != -1) { \
180                if (DWC_OTG_PARAM_TEST(_param_, (_low_), (_high_))) { \
181                    DWC_ERROR("`%d' invalid for parameter `%s'\n", \
182                          dwc_otg_module_params._param_, _string_); \
183                    dwc_otg_module_params._param_ = dwc_param_##_param_##_default; \
184                    retval++; \
185                } \
186            } \
187        } while (0)
188
189    DWC_OTG_PARAM_ERR(opt,0,1,"opt");
190    DWC_OTG_PARAM_ERR(otg_cap,0,2,"otg_cap");
191    DWC_OTG_PARAM_ERR(dma_enable,0,1,"dma_enable");
192    DWC_OTG_PARAM_ERR(dma_desc_enable,0,1,"dma_desc_enable");
193    DWC_OTG_PARAM_ERR(speed,0,1,"speed");
194    DWC_OTG_PARAM_ERR(host_support_fs_ls_low_power,0,1,"host_support_fs_ls_low_power");
195    DWC_OTG_PARAM_ERR(host_ls_low_power_phy_clk,0,1,"host_ls_low_power_phy_clk");
196    DWC_OTG_PARAM_ERR(enable_dynamic_fifo,0,1,"enable_dynamic_fifo");
197    DWC_OTG_PARAM_ERR(data_fifo_size,32,32768,"data_fifo_size");
198    DWC_OTG_PARAM_ERR(dev_rx_fifo_size,16,32768,"dev_rx_fifo_size");
199    DWC_OTG_PARAM_ERR(dev_nperio_tx_fifo_size,16,32768,"dev_nperio_tx_fifo_size");
200    DWC_OTG_PARAM_ERR(host_rx_fifo_size,16,32768,"host_rx_fifo_size");
201    DWC_OTG_PARAM_ERR(host_nperio_tx_fifo_size,16,32768,"host_nperio_tx_fifo_size");
202    DWC_OTG_PARAM_ERR(host_perio_tx_fifo_size,16,32768,"host_perio_tx_fifo_size");
203    DWC_OTG_PARAM_ERR(max_transfer_size,2047,524288,"max_transfer_size");
204    DWC_OTG_PARAM_ERR(max_packet_count,15,511,"max_packet_count");
205    DWC_OTG_PARAM_ERR(host_channels,1,16,"host_channels");
206    DWC_OTG_PARAM_ERR(dev_endpoints,1,15,"dev_endpoints");
207    DWC_OTG_PARAM_ERR(phy_type,0,2,"phy_type");
208    DWC_OTG_PARAM_ERR(phy_ulpi_ddr,0,1,"phy_ulpi_ddr");
209    DWC_OTG_PARAM_ERR(phy_ulpi_ext_vbus,0,1,"phy_ulpi_ext_vbus");
210    DWC_OTG_PARAM_ERR(i2c_enable,0,1,"i2c_enable");
211    DWC_OTG_PARAM_ERR(ulpi_fs_ls,0,1,"ulpi_fs_ls");
212    DWC_OTG_PARAM_ERR(ts_dline,0,1,"ts_dline");
213
214    if (dwc_otg_module_params.dma_burst_size != -1) {
215        if (DWC_OTG_PARAM_TEST(dma_burst_size,1,1) &&
216            DWC_OTG_PARAM_TEST(dma_burst_size,4,4) &&
217            DWC_OTG_PARAM_TEST(dma_burst_size,8,8) &&
218            DWC_OTG_PARAM_TEST(dma_burst_size,16,16) &&
219            DWC_OTG_PARAM_TEST(dma_burst_size,32,32) &&
220            DWC_OTG_PARAM_TEST(dma_burst_size,64,64) &&
221            DWC_OTG_PARAM_TEST(dma_burst_size,128,128) &&
222            DWC_OTG_PARAM_TEST(dma_burst_size,256,256)) {
223            DWC_ERROR("`%d' invalid for parameter `dma_burst_size'\n",
224                  dwc_otg_module_params.dma_burst_size);
225            dwc_otg_module_params.dma_burst_size = 32;
226            retval++;
227        }
228
229        {
230            uint8_t brst_sz = 0;
231            while(dwc_otg_module_params.dma_burst_size > 1) {
232                brst_sz ++;
233                dwc_otg_module_params.dma_burst_size >>= 1;
234            }
235            dwc_otg_module_params.dma_burst_size = brst_sz;
236        }
237    }
238
239    if (dwc_otg_module_params.phy_utmi_width != -1) {
240        if (DWC_OTG_PARAM_TEST(phy_utmi_width, 8, 8) &&
241            DWC_OTG_PARAM_TEST(phy_utmi_width, 16, 16)) {
242            DWC_ERROR("`%d' invalid for parameter `phy_utmi_width'\n",
243                  dwc_otg_module_params.phy_utmi_width);
244            dwc_otg_module_params.phy_utmi_width = 16;
245            retval++;
246        }
247    }
248
249    for (i = 0; i < 15; i++) {
250        /** @todo should be like above */
251        //DWC_OTG_PARAM_ERR(dev_perio_tx_fifo_size[i], 4, 768, "dev_perio_tx_fifo_size");
252        if (dwc_otg_module_params.dev_perio_tx_fifo_size[i] != -1) {
253            if (DWC_OTG_PARAM_TEST(dev_perio_tx_fifo_size[i], 4, 768)) {
254                DWC_ERROR("`%d' invalid for parameter `%s_%d'\n",
255                      dwc_otg_module_params.dev_perio_tx_fifo_size[i], "dev_perio_tx_fifo_size", i);
256                dwc_otg_module_params.dev_perio_tx_fifo_size[i] = dwc_param_dev_perio_tx_fifo_size_default;
257                retval++;
258            }
259        }
260    }
261
262    DWC_OTG_PARAM_ERR(en_multiple_tx_fifo, 0, 1, "en_multiple_tx_fifo");
263
264    for (i = 0; i < 15; i++) {
265        /** @todo should be like above */
266        //DWC_OTG_PARAM_ERR(dev_tx_fifo_size[i], 4, 768, "dev_tx_fifo_size");
267        if (dwc_otg_module_params.dev_tx_fifo_size[i] != -1) {
268            if (DWC_OTG_PARAM_TEST(dev_tx_fifo_size[i], 4, 768)) {
269                DWC_ERROR("`%d' invalid for parameter `%s_%d'\n",
270                      dwc_otg_module_params.dev_tx_fifo_size[i], "dev_tx_fifo_size", i);
271                dwc_otg_module_params.dev_tx_fifo_size[i] = dwc_param_dev_tx_fifo_size_default;
272                retval++;
273            }
274        }
275    }
276
277    DWC_OTG_PARAM_ERR(thr_ctl, 0, 7, "thr_ctl");
278    DWC_OTG_PARAM_ERR(tx_thr_length, 8, 128, "tx_thr_length");
279    DWC_OTG_PARAM_ERR(rx_thr_length, 8, 128, "rx_thr_length");
280
281    DWC_OTG_PARAM_ERR(pti_enable,0,1,"pti_enable");
282    DWC_OTG_PARAM_ERR(mpi_enable,0,1,"mpi_enable");
283
284    /* At this point, all module parameters that have been set by the user
285     * are valid, and those that have not are left unset. Now set their
286     * default values and/or check the parameters against the hardware
287     * configurations of the OTG core. */
288
289/* This sets the parameter to the default value if it has not been set by the
290 * user */
291#define DWC_OTG_PARAM_SET_DEFAULT(_param_) \
292    ({ \
293        int changed = 1; \
294        if (dwc_otg_module_params._param_ == -1) { \
295            changed = 0; \
296            dwc_otg_module_params._param_ = dwc_param_##_param_##_default; \
297        } \
298        changed; \
299    })
300
301/* This checks the macro agains the hardware configuration to see if it is
302 * valid. It is possible that the default value could be invalid. In this
303 * case, it will report a module error if the user touched the parameter.
304 * Otherwise it will adjust the value without any error. */
305#define DWC_OTG_PARAM_CHECK_VALID(_param_, _str_, _is_valid_, _set_valid_) \
306    ({ \
307        int changed = DWC_OTG_PARAM_SET_DEFAULT(_param_); \
308        int error = 0; \
309        if (!(_is_valid_)) { \
310            if (changed) { \
311                DWC_ERROR("`%d' invalid for parameter `%s'. Check HW configuration.\n", dwc_otg_module_params._param_, _str_); \
312                error = 1; \
313            } \
314            dwc_otg_module_params._param_ = (_set_valid_); \
315        } \
316        error; \
317    })
318
319    /* OTG Cap */
320    retval += DWC_OTG_PARAM_CHECK_VALID(otg_cap, "otg_cap",
321                ({
322                    int valid;
323                    valid = 1;
324                    switch (dwc_otg_module_params.otg_cap) {
325                    case DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE:
326                        if (core_if->hwcfg2.b.op_mode != DWC_HWCFG2_OP_MODE_HNP_SRP_CAPABLE_OTG)
327                            valid = 0;
328                        break;
329                    case DWC_OTG_CAP_PARAM_SRP_ONLY_CAPABLE:
330                        if ((core_if->hwcfg2.b.op_mode != DWC_HWCFG2_OP_MODE_HNP_SRP_CAPABLE_OTG) &&
331                            (core_if->hwcfg2.b.op_mode != DWC_HWCFG2_OP_MODE_SRP_ONLY_CAPABLE_OTG) &&
332                            (core_if->hwcfg2.b.op_mode != DWC_HWCFG2_OP_MODE_SRP_CAPABLE_DEVICE) &&
333                            (core_if->hwcfg2.b.op_mode != DWC_HWCFG2_OP_MODE_SRP_CAPABLE_HOST)) {
334                            valid = 0;
335                        }
336                        break;
337                    case DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE:
338                        /* always valid */
339                        break;
340                    }
341                    valid;
342                }),
343                (((core_if->hwcfg2.b.op_mode == DWC_HWCFG2_OP_MODE_HNP_SRP_CAPABLE_OTG) ||
344                  (core_if->hwcfg2.b.op_mode == DWC_HWCFG2_OP_MODE_SRP_ONLY_CAPABLE_OTG) ||
345                  (core_if->hwcfg2.b.op_mode == DWC_HWCFG2_OP_MODE_SRP_CAPABLE_DEVICE) ||
346                  (core_if->hwcfg2.b.op_mode == DWC_HWCFG2_OP_MODE_SRP_CAPABLE_HOST)) ?
347                 DWC_OTG_CAP_PARAM_SRP_ONLY_CAPABLE :
348                 DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE));
349
350    retval += DWC_OTG_PARAM_CHECK_VALID(dma_enable, "dma_enable",
351                ((dwc_otg_module_params.dma_enable == 1) && (core_if->hwcfg2.b.architecture == 0)) ? 0 : 1,
352                0);
353
354    retval += DWC_OTG_PARAM_CHECK_VALID(dma_desc_enable, "dma_desc_enable",
355                ((dwc_otg_module_params.dma_desc_enable == 1) &&
356                 ((dwc_otg_module_params.dma_enable == 0) || (core_if->hwcfg4.b.desc_dma == 0))) ? 0 : 1,
357                0);
358
359    retval += DWC_OTG_PARAM_CHECK_VALID(opt, "opt", 1, 0);
360
361    DWC_OTG_PARAM_SET_DEFAULT(dma_burst_size);
362
363    retval += DWC_OTG_PARAM_CHECK_VALID(host_support_fs_ls_low_power,
364                "host_support_fs_ls_low_power",
365                1, 0);
366
367    retval += DWC_OTG_PARAM_CHECK_VALID(enable_dynamic_fifo,
368                    "enable_dynamic_fifo",
369                    ((dwc_otg_module_params.enable_dynamic_fifo == 0) ||
370                    (core_if->hwcfg2.b.dynamic_fifo == 1)), 0);
371
372    retval += DWC_OTG_PARAM_CHECK_VALID(data_fifo_size,
373                    "data_fifo_size",
374                    (dwc_otg_module_params.data_fifo_size <= core_if->hwcfg3.b.dfifo_depth),
375                    core_if->hwcfg3.b.dfifo_depth);
376
377    retval += DWC_OTG_PARAM_CHECK_VALID(dev_rx_fifo_size,
378                    "dev_rx_fifo_size",
379                    (dwc_otg_module_params.dev_rx_fifo_size <= dwc_read_reg32(&core_if->core_global_regs->grxfsiz)),
380                    dwc_read_reg32(&core_if->core_global_regs->grxfsiz));
381
382    retval += DWC_OTG_PARAM_CHECK_VALID(dev_nperio_tx_fifo_size,
383                    "dev_nperio_tx_fifo_size",
384                    (dwc_otg_module_params.dev_nperio_tx_fifo_size <= (dwc_read_reg32(&core_if->core_global_regs->gnptxfsiz) >> 16)),
385                    (dwc_read_reg32(&core_if->core_global_regs->gnptxfsiz) >> 16));
386
387    retval += DWC_OTG_PARAM_CHECK_VALID(host_rx_fifo_size,
388                    "host_rx_fifo_size",
389                    (dwc_otg_module_params.host_rx_fifo_size <= dwc_read_reg32(&core_if->core_global_regs->grxfsiz)),
390                    dwc_read_reg32(&core_if->core_global_regs->grxfsiz));
391
392    retval += DWC_OTG_PARAM_CHECK_VALID(host_nperio_tx_fifo_size,
393                    "host_nperio_tx_fifo_size",
394                    (dwc_otg_module_params.host_nperio_tx_fifo_size <= (dwc_read_reg32(&core_if->core_global_regs->gnptxfsiz) >> 16)),
395                    (dwc_read_reg32(&core_if->core_global_regs->gnptxfsiz) >> 16));
396
397    retval += DWC_OTG_PARAM_CHECK_VALID(host_perio_tx_fifo_size,
398                    "host_perio_tx_fifo_size",
399                    (dwc_otg_module_params.host_perio_tx_fifo_size <= ((dwc_read_reg32(&core_if->core_global_regs->hptxfsiz) >> 16))),
400                    ((dwc_read_reg32(&core_if->core_global_regs->hptxfsiz) >> 16)));
401
402    retval += DWC_OTG_PARAM_CHECK_VALID(max_transfer_size,
403                    "max_transfer_size",
404                    (dwc_otg_module_params.max_transfer_size < (1 << (core_if->hwcfg3.b.xfer_size_cntr_width + 11))),
405                    ((1 << (core_if->hwcfg3.b.xfer_size_cntr_width + 11)) - 1));
406
407    retval += DWC_OTG_PARAM_CHECK_VALID(max_packet_count,
408                    "max_packet_count",
409                    (dwc_otg_module_params.max_packet_count < (1 << (core_if->hwcfg3.b.packet_size_cntr_width + 4))),
410                    ((1 << (core_if->hwcfg3.b.packet_size_cntr_width + 4)) - 1));
411
412    retval += DWC_OTG_PARAM_CHECK_VALID(host_channels,
413                    "host_channels",
414                    (dwc_otg_module_params.host_channels <= (core_if->hwcfg2.b.num_host_chan + 1)),
415                    (core_if->hwcfg2.b.num_host_chan + 1));
416
417    retval += DWC_OTG_PARAM_CHECK_VALID(dev_endpoints,
418                    "dev_endpoints",
419                    (dwc_otg_module_params.dev_endpoints <= (core_if->hwcfg2.b.num_dev_ep)),
420                    core_if->hwcfg2.b.num_dev_ep);
421
422/*
423 * Define the following to disable the FS PHY Hardware checking. This is for
424 * internal testing only.
425 *
426 * #define NO_FS_PHY_HW_CHECKS
427 */
428
429#ifdef NO_FS_PHY_HW_CHECKS
430    retval += DWC_OTG_PARAM_CHECK_VALID(phy_type,
431                "phy_type", 1, 0);
432#else
433    retval += DWC_OTG_PARAM_CHECK_VALID(phy_type,
434                "phy_type",
435                ({
436                    int valid = 0;
437                    if ((dwc_otg_module_params.phy_type == DWC_PHY_TYPE_PARAM_UTMI) &&
438                    ((core_if->hwcfg2.b.hs_phy_type == 1) ||
439                     (core_if->hwcfg2.b.hs_phy_type == 3))) {
440                        valid = 1;
441                    }
442                    else if ((dwc_otg_module_params.phy_type == DWC_PHY_TYPE_PARAM_ULPI) &&
443                         ((core_if->hwcfg2.b.hs_phy_type == 2) ||
444                          (core_if->hwcfg2.b.hs_phy_type == 3))) {
445                        valid = 1;
446                    }
447                    else if ((dwc_otg_module_params.phy_type == DWC_PHY_TYPE_PARAM_FS) &&
448                         (core_if->hwcfg2.b.fs_phy_type == 1)) {
449                        valid = 1;
450                    }
451                    valid;
452                }),
453                ({
454                    int set = DWC_PHY_TYPE_PARAM_FS;
455                    if (core_if->hwcfg2.b.hs_phy_type) {
456                        if ((core_if->hwcfg2.b.hs_phy_type == 3) ||
457                        (core_if->hwcfg2.b.hs_phy_type == 1)) {
458                            set = DWC_PHY_TYPE_PARAM_UTMI;
459                        }
460                        else {
461                            set = DWC_PHY_TYPE_PARAM_ULPI;
462                        }
463                    }
464                    set;
465                }));
466#endif
467
468    retval += DWC_OTG_PARAM_CHECK_VALID(speed, "speed",
469                (dwc_otg_module_params.speed == 0) && (dwc_otg_module_params.phy_type == DWC_PHY_TYPE_PARAM_FS) ? 0 : 1,
470                dwc_otg_module_params.phy_type == DWC_PHY_TYPE_PARAM_FS ? 1 : 0);
471
472    retval += DWC_OTG_PARAM_CHECK_VALID(host_ls_low_power_phy_clk,
473                "host_ls_low_power_phy_clk",
474                ((dwc_otg_module_params.host_ls_low_power_phy_clk == DWC_HOST_LS_LOW_POWER_PHY_CLK_PARAM_48MHZ) && (dwc_otg_module_params.phy_type == DWC_PHY_TYPE_PARAM_FS) ? 0 : 1),
475                ((dwc_otg_module_params.phy_type == DWC_PHY_TYPE_PARAM_FS) ? DWC_HOST_LS_LOW_POWER_PHY_CLK_PARAM_6MHZ : DWC_HOST_LS_LOW_POWER_PHY_CLK_PARAM_48MHZ));
476
477    DWC_OTG_PARAM_SET_DEFAULT(phy_ulpi_ddr);
478    DWC_OTG_PARAM_SET_DEFAULT(phy_ulpi_ext_vbus);
479    DWC_OTG_PARAM_SET_DEFAULT(phy_utmi_width);
480    DWC_OTG_PARAM_SET_DEFAULT(ulpi_fs_ls);
481    DWC_OTG_PARAM_SET_DEFAULT(ts_dline);
482
483#ifdef NO_FS_PHY_HW_CHECKS
484    retval += DWC_OTG_PARAM_CHECK_VALID(i2c_enable, "i2c_enable", 1, 0);
485#else
486    retval += DWC_OTG_PARAM_CHECK_VALID(i2c_enable,
487                "i2c_enable",
488                (dwc_otg_module_params.i2c_enable == 1) && (core_if->hwcfg3.b.i2c == 0) ? 0 : 1,
489                0);
490#endif
491
492    for (i = 0; i < 15; i++) {
493        int changed = 1;
494        int error = 0;
495
496        if (dwc_otg_module_params.dev_perio_tx_fifo_size[i] == -1) {
497            changed = 0;
498            dwc_otg_module_params.dev_perio_tx_fifo_size[i] = dwc_param_dev_perio_tx_fifo_size_default;
499        }
500        if (!(dwc_otg_module_params.dev_perio_tx_fifo_size[i] <= (dwc_read_reg32(&core_if->core_global_regs->dptxfsiz_dieptxf[i])))) {
501            if (changed) {
502                DWC_ERROR("`%d' invalid for parameter `dev_perio_fifo_size_%d'. Check HW configuration.\n", dwc_otg_module_params.dev_perio_tx_fifo_size[i], i);
503                error = 1;
504            }
505            dwc_otg_module_params.dev_perio_tx_fifo_size[i] = dwc_read_reg32(&core_if->core_global_regs->dptxfsiz_dieptxf[i]);
506        }
507        retval += error;
508    }
509
510    retval += DWC_OTG_PARAM_CHECK_VALID(en_multiple_tx_fifo, "en_multiple_tx_fifo",
511                        ((dwc_otg_module_params.en_multiple_tx_fifo == 1) && (core_if->hwcfg4.b.ded_fifo_en == 0)) ? 0 : 1,
512                        0);
513
514    for (i = 0; i < 15; i++) {
515        int changed = 1;
516        int error = 0;
517
518        if (dwc_otg_module_params.dev_tx_fifo_size[i] == -1) {
519            changed = 0;
520            dwc_otg_module_params.dev_tx_fifo_size[i] = dwc_param_dev_tx_fifo_size_default;
521        }
522        if (!(dwc_otg_module_params.dev_tx_fifo_size[i] <= (dwc_read_reg32(&core_if->core_global_regs->dptxfsiz_dieptxf[i])))) {
523            if (changed) {
524                DWC_ERROR("%d' invalid for parameter `dev_perio_fifo_size_%d'. Check HW configuration.\n", dwc_otg_module_params.dev_tx_fifo_size[i], i);
525                error = 1;
526            }
527            dwc_otg_module_params.dev_tx_fifo_size[i] = dwc_read_reg32(&core_if->core_global_regs->dptxfsiz_dieptxf[i]);
528        }
529        retval += error;
530    }
531
532    retval += DWC_OTG_PARAM_CHECK_VALID(thr_ctl, "thr_ctl",
533                ((dwc_otg_module_params.thr_ctl != 0) && ((dwc_otg_module_params.dma_enable == 0) || (core_if->hwcfg4.b.ded_fifo_en == 0))) ? 0 : 1,
534                0);
535
536    DWC_OTG_PARAM_SET_DEFAULT(tx_thr_length);
537    DWC_OTG_PARAM_SET_DEFAULT(rx_thr_length);
538
539    retval += DWC_OTG_PARAM_CHECK_VALID(pti_enable, "pti_enable",
540        ((dwc_otg_module_params.pti_enable == 0) || ((dwc_otg_module_params.pti_enable == 1) && (core_if->snpsid >= 0x4F54272A))) ? 1 : 0,
541            0);
542
543    retval += DWC_OTG_PARAM_CHECK_VALID(mpi_enable, "mpi_enable",
544            ((dwc_otg_module_params.mpi_enable == 0) || ((dwc_otg_module_params.mpi_enable == 1) && (core_if->hwcfg2.b.multi_proc_int == 1))) ? 1 : 0,
545            0);
546    return retval;
547}
548
549/**
550 * This function is the top level interrupt handler for the Common
551 * (Device and host modes) interrupts.
552 */
553static irqreturn_t dwc_otg_common_irq(int irq, void *dev)
554{
555    dwc_otg_device_t *otg_dev = dev;
556    int32_t retval = IRQ_NONE;
557
558    retval = dwc_otg_handle_common_intr(otg_dev->core_if);
559    return IRQ_RETVAL(retval);
560}
561
562/**
563 * This function is called when a lm_device is unregistered with the
564 * dwc_otg_driver. This happens, for example, when the rmmod command is
565 * executed. The device may or may not be electrically present. If it is
566 * present, the driver stops device processing. Any resources used on behalf
567 * of this device are freed.
568 *
569 * @param[in] lmdev
570 */
571static int dwc_otg_driver_cleanup(struct platform_device *pdev)
572{
573    dwc_otg_device_t *otg_dev = platform_get_drvdata(pdev);
574    DWC_DEBUGPL(DBG_ANY, "%s(%p)\n", __func__, pdev);
575
576    if (!otg_dev) {
577        /* Memory allocation for the dwc_otg_device failed. */
578        DWC_DEBUGPL(DBG_ANY, "%s: otg_dev NULL!\n", __func__);
579        return 0;
580    }
581
582    /*
583     * Free the IRQ
584     */
585    if (otg_dev->common_irq_installed) {
586        free_irq(otg_dev->irq, otg_dev);
587    }
588
589#ifndef DWC_DEVICE_ONLY
590    if (otg_dev->hcd) {
591        dwc_otg_hcd_remove(pdev);
592    } else {
593        DWC_DEBUGPL(DBG_ANY, "%s: otg_dev->hcd NULL!\n", __func__);
594        return 0;
595    }
596#endif
597
598#ifndef DWC_HOST_ONLY
599    if (otg_dev->pcd) {
600        dwc_otg_pcd_remove(pdev);
601    }
602#endif
603    if (otg_dev->core_if) {
604        dwc_otg_cil_remove(otg_dev->core_if);
605    }
606
607    /*
608     * Remove the device attributes
609     */
610    dwc_otg_attr_remove(pdev);
611
612    /*
613     * Return the memory.
614     */
615    if (otg_dev->base) {
616        iounmap(otg_dev->base);
617    }
618    kfree(otg_dev);
619
620    /*
621     * Clear the drvdata pointer.
622     */
623    platform_set_drvdata(pdev, 0);
624
625    return 0;
626}
627
628/**
629 * This function is called when an lm_device is bound to a
630 * dwc_otg_driver. It creates the driver components required to
631 * control the device (CIL, HCD, and PCD) and it initializes the
632 * device. The driver components are stored in a dwc_otg_device
633 * structure. A reference to the dwc_otg_device is saved in the
634 * lm_device. This allows the driver to access the dwc_otg_device
635 * structure on subsequent calls to driver methods for this device.
636 *
637 * @param[in] lmdev lm_device definition
638 */
639static int __devinit dwc_otg_driver_probe(struct platform_device *pdev)
640{
641    struct device *dev = &pdev->dev;
642    int retval = 0;
643    uint32_t snpsid;
644    dwc_otg_device_t *dwc_otg_device;
645    struct resource *res;
646
647    dev_dbg(dev, "dwc_otg_driver_probe(%p)\n", pdev);
648
649    dwc_otg_device = kmalloc(sizeof(dwc_otg_device_t), GFP_KERNEL);
650
651    if (!dwc_otg_device) {
652        dev_err(dev, "kmalloc of dwc_otg_device failed\n");
653        retval = -ENOMEM;
654        goto fail;
655    }
656
657    memset(dwc_otg_device, 0, sizeof(*dwc_otg_device));
658    dwc_otg_device->reg_offset = 0xFFFFFFFF;
659
660    res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
661    if (!res) {
662        dev_err(dev, "Found OTG with no register addr.\n");
663        retval = -ENODEV;
664        goto fail;
665    }
666    dwc_otg_device->rsrc_start = res->start;
667    dwc_otg_device->rsrc_len = res->end - res->start + 1;
668
669    dwc_otg_device->base = ioremap(dwc_otg_device->rsrc_start, dwc_otg_device->rsrc_len);
670
671    if (!dwc_otg_device->base) {
672        dev_err(dev, "ioremap() failed\n");
673        retval = -ENOMEM;
674        goto fail;
675    }
676    dev_dbg(dev, "base=0x%08x\n", (unsigned)dwc_otg_device->base);
677
678    /*
679     * Attempt to ensure this device is really a DWC_otg Controller.
680     * Read and verify the SNPSID register contents. The value should be
681     * 0x45F42XXX, which corresponds to "OT2", as in "OTG version 2.XX".
682     */
683    snpsid = dwc_read_reg32((uint32_t *)((uint8_t *)dwc_otg_device->base + 0x40));
684
685    if ((snpsid & 0xFFFFF000) != OTG_CORE_REV_2_00) {
686        dev_err(dev, "Bad value for SNPSID: 0x%08x\n", snpsid);
687        retval = -EINVAL;
688        goto fail;
689    }
690
691    DWC_PRINT("Core Release: %x.%x%x%x\n",
692            (snpsid >> 12 & 0xF),
693            (snpsid >> 8 & 0xF),
694            (snpsid >> 4 & 0xF),
695            (snpsid & 0xF));
696
697    /*
698     * Initialize driver data to point to the global DWC_otg
699     * Device structure.
700     */
701    platform_set_drvdata(pdev, dwc_otg_device);
702
703    dev_dbg(dev, "dwc_otg_device=0x%p\n", dwc_otg_device);
704
705    dwc_otg_device->core_if = dwc_otg_cil_init(dwc_otg_device->base,
706                           &dwc_otg_module_params);
707
708    dwc_otg_device->core_if->snpsid = snpsid;
709
710    if (!dwc_otg_device->core_if) {
711        dev_err(dev, "CIL initialization failed!\n");
712        retval = -ENOMEM;
713        goto fail;
714    }
715
716    /*
717     * Validate parameter values.
718     */
719    if (check_parameters(dwc_otg_device->core_if)) {
720        retval = -EINVAL;
721        goto fail;
722    }
723
724    /*
725     * Create Device Attributes in sysfs
726     */
727    dwc_otg_attr_create(pdev);
728
729    /*
730     * Disable the global interrupt until all the interrupt
731     * handlers are installed.
732     */
733    dwc_otg_disable_global_interrupts(dwc_otg_device->core_if);
734
735    /*
736     * Install the interrupt handler for the common interrupts before
737     * enabling common interrupts in core_init below.
738     */
739    res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
740    if (!res) {
741        dev_err(dev, "Fount OTG with to IRQ.\n");
742        retval = -ENODEV;
743        goto fail;
744    }
745    dwc_otg_device->irq = res->start;
746
747    retval = request_irq(res->start, dwc_otg_common_irq,
748                 IRQF_SHARED, "dwc_otg", dwc_otg_device);
749    if (retval) {
750        DWC_ERROR("request of irq%d failed\n", res->start);
751        retval = -EBUSY;
752        goto fail;
753    } else {
754        dwc_otg_device->common_irq_installed = 1;
755    }
756
757    /*
758     * Initialize the DWC_otg core.
759     */
760    dwc_otg_core_init(dwc_otg_device->core_if);
761
762#ifndef DWC_HOST_ONLY
763    /*
764     * Initialize the PCD
765     */
766    retval = dwc_otg_pcd_init(pdev);
767    if (retval != 0) {
768        DWC_ERROR("dwc_otg_pcd_init failed\n");
769        dwc_otg_device->pcd = NULL;
770        goto fail;
771    }
772#endif
773#ifndef DWC_DEVICE_ONLY
774    /*
775     * Initialize the HCD
776     */
777    retval = dwc_otg_hcd_init(pdev);
778    if (retval != 0) {
779        DWC_ERROR("dwc_otg_hcd_init failed\n");
780        dwc_otg_device->hcd = NULL;
781        goto fail;
782    }
783#endif
784
785    /*
786     * Enable the global interrupt after all the interrupt
787     * handlers are installed.
788     */
789    dwc_otg_enable_global_interrupts(dwc_otg_device->core_if);
790
791    return 0;
792
793 fail:
794    dwc_otg_driver_cleanup(pdev);
795    return retval;
796}
797
798static int __devexit dwc_otg_driver_remove(struct platform_device *pdev)
799{
800    return dwc_otg_driver_cleanup(pdev);
801}
802
803static struct platform_driver dwc_otg_platform_driver = {
804    .driver.name = "dwc_otg",
805    .probe = dwc_otg_driver_probe,
806    .remove = __devexit_p(dwc_otg_driver_remove),
807};
808
809static int __init dwc_otg_init_module(void)
810{
811    return platform_driver_register(&dwc_otg_platform_driver);
812}
813
814static void __exit dwc_otg_cleanup_module(void)
815{
816    platform_driver_unregister(&dwc_otg_platform_driver);
817}
818
819module_init(dwc_otg_init_module);
820module_exit(dwc_otg_cleanup_module);
821
822/**
823 * This function is called when the driver is removed from the kernel
824 * with the rmmod command. The driver unregisters itself with its bus
825 * driver.
826 *
827 */
828
829MODULE_DESCRIPTION(DWC_DRIVER_DESC);
830MODULE_AUTHOR("Synopsys Inc.");
831MODULE_LICENSE("GPL");
832
833module_param_named(otg_cap, dwc_otg_module_params.otg_cap, int, 0444);
834MODULE_PARM_DESC(otg_cap, "OTG Capabilities 0=HNP&SRP 1=SRP Only 2=None");
835module_param_named(opt, dwc_otg_module_params.opt, int, 0444);
836MODULE_PARM_DESC(opt, "OPT Mode");
837module_param_named(dma_enable, dwc_otg_module_params.dma_enable, int, 0444);
838MODULE_PARM_DESC(dma_enable, "DMA Mode 0=Slave 1=DMA enabled");
839
840module_param_named(dma_desc_enable, dwc_otg_module_params.dma_desc_enable, int, 0444);
841MODULE_PARM_DESC(dma_desc_enable, "DMA Desc Mode 0=Address DMA 1=DMA Descriptor enabled");
842
843module_param_named(dma_burst_size, dwc_otg_module_params.dma_burst_size, int, 0444);
844MODULE_PARM_DESC(dma_burst_size, "DMA Burst Size 1, 4, 8, 16, 32, 64, 128, 256");
845module_param_named(speed, dwc_otg_module_params.speed, int, 0444);
846MODULE_PARM_DESC(speed, "Speed 0=High Speed 1=Full Speed");
847module_param_named(host_support_fs_ls_low_power, dwc_otg_module_params.host_support_fs_ls_low_power, int, 0444);
848MODULE_PARM_DESC(host_support_fs_ls_low_power, "Support Low Power w/FS or LS 0=Support 1=Don't Support");
849module_param_named(host_ls_low_power_phy_clk, dwc_otg_module_params.host_ls_low_power_phy_clk, int, 0444);
850MODULE_PARM_DESC(host_ls_low_power_phy_clk, "Low Speed Low Power Clock 0=48Mhz 1=6Mhz");
851module_param_named(enable_dynamic_fifo, dwc_otg_module_params.enable_dynamic_fifo, int, 0444);
852MODULE_PARM_DESC(enable_dynamic_fifo, "0=cC Setting 1=Allow Dynamic Sizing");
853module_param_named(data_fifo_size, dwc_otg_module_params.data_fifo_size, int, 0444);
854MODULE_PARM_DESC(data_fifo_size, "Total number of words in the data FIFO memory 32-32768");
855module_param_named(dev_rx_fifo_size, dwc_otg_module_params.dev_rx_fifo_size, int, 0444);
856MODULE_PARM_DESC(dev_rx_fifo_size, "Number of words in the Rx FIFO 16-32768");
857module_param_named(dev_nperio_tx_fifo_size, dwc_otg_module_params.dev_nperio_tx_fifo_size, int, 0444);
858MODULE_PARM_DESC(dev_nperio_tx_fifo_size, "Number of words in the non-periodic Tx FIFO 16-32768");
859module_param_named(dev_perio_tx_fifo_size_1, dwc_otg_module_params.dev_perio_tx_fifo_size[0], int, 0444);
860MODULE_PARM_DESC(dev_perio_tx_fifo_size_1, "Number of words in the periodic Tx FIFO 4-768");
861module_param_named(dev_perio_tx_fifo_size_2, dwc_otg_module_params.dev_perio_tx_fifo_size[1], int, 0444);
862MODULE_PARM_DESC(dev_perio_tx_fifo_size_2, "Number of words in the periodic Tx FIFO 4-768");
863module_param_named(dev_perio_tx_fifo_size_3, dwc_otg_module_params.dev_perio_tx_fifo_size[2], int, 0444);
864MODULE_PARM_DESC(dev_perio_tx_fifo_size_3, "Number of words in the periodic Tx FIFO 4-768");
865module_param_named(dev_perio_tx_fifo_size_4, dwc_otg_module_params.dev_perio_tx_fifo_size[3], int, 0444);
866MODULE_PARM_DESC(dev_perio_tx_fifo_size_4, "Number of words in the periodic Tx FIFO 4-768");
867module_param_named(dev_perio_tx_fifo_size_5, dwc_otg_module_params.dev_perio_tx_fifo_size[4], int, 0444);
868MODULE_PARM_DESC(dev_perio_tx_fifo_size_5, "Number of words in the periodic Tx FIFO 4-768");
869module_param_named(dev_perio_tx_fifo_size_6, dwc_otg_module_params.dev_perio_tx_fifo_size[5], int, 0444);
870MODULE_PARM_DESC(dev_perio_tx_fifo_size_6, "Number of words in the periodic Tx FIFO 4-768");
871module_param_named(dev_perio_tx_fifo_size_7, dwc_otg_module_params.dev_perio_tx_fifo_size[6], int, 0444);
872MODULE_PARM_DESC(dev_perio_tx_fifo_size_7, "Number of words in the periodic Tx FIFO 4-768");
873module_param_named(dev_perio_tx_fifo_size_8, dwc_otg_module_params.dev_perio_tx_fifo_size[7], int, 0444);
874MODULE_PARM_DESC(dev_perio_tx_fifo_size_8, "Number of words in the periodic Tx FIFO 4-768");
875module_param_named(dev_perio_tx_fifo_size_9, dwc_otg_module_params.dev_perio_tx_fifo_size[8], int, 0444);
876MODULE_PARM_DESC(dev_perio_tx_fifo_size_9, "Number of words in the periodic Tx FIFO 4-768");
877module_param_named(dev_perio_tx_fifo_size_10, dwc_otg_module_params.dev_perio_tx_fifo_size[9], int, 0444);
878MODULE_PARM_DESC(dev_perio_tx_fifo_size_10, "Number of words in the periodic Tx FIFO 4-768");
879module_param_named(dev_perio_tx_fifo_size_11, dwc_otg_module_params.dev_perio_tx_fifo_size[10], int, 0444);
880MODULE_PARM_DESC(dev_perio_tx_fifo_size_11, "Number of words in the periodic Tx FIFO 4-768");
881module_param_named(dev_perio_tx_fifo_size_12, dwc_otg_module_params.dev_perio_tx_fifo_size[11], int, 0444);
882MODULE_PARM_DESC(dev_perio_tx_fifo_size_12, "Number of words in the periodic Tx FIFO 4-768");
883module_param_named(dev_perio_tx_fifo_size_13, dwc_otg_module_params.dev_perio_tx_fifo_size[12], int, 0444);
884MODULE_PARM_DESC(dev_perio_tx_fifo_size_13, "Number of words in the periodic Tx FIFO 4-768");
885module_param_named(dev_perio_tx_fifo_size_14, dwc_otg_module_params.dev_perio_tx_fifo_size[13], int, 0444);
886MODULE_PARM_DESC(dev_perio_tx_fifo_size_14, "Number of words in the periodic Tx FIFO 4-768");
887module_param_named(dev_perio_tx_fifo_size_15, dwc_otg_module_params.dev_perio_tx_fifo_size[14], int, 0444);
888MODULE_PARM_DESC(dev_perio_tx_fifo_size_15, "Number of words in the periodic Tx FIFO 4-768");
889module_param_named(host_rx_fifo_size, dwc_otg_module_params.host_rx_fifo_size, int, 0444);
890MODULE_PARM_DESC(host_rx_fifo_size, "Number of words in the Rx FIFO 16-32768");
891module_param_named(host_nperio_tx_fifo_size, dwc_otg_module_params.host_nperio_tx_fifo_size, int, 0444);
892MODULE_PARM_DESC(host_nperio_tx_fifo_size, "Number of words in the non-periodic Tx FIFO 16-32768");
893module_param_named(host_perio_tx_fifo_size, dwc_otg_module_params.host_perio_tx_fifo_size, int, 0444);
894MODULE_PARM_DESC(host_perio_tx_fifo_size, "Number of words in the host periodic Tx FIFO 16-32768");
895module_param_named(max_transfer_size, dwc_otg_module_params.max_transfer_size, int, 0444);
896/** @todo Set the max to 512K, modify checks */
897MODULE_PARM_DESC(max_transfer_size, "The maximum transfer size supported in bytes 2047-65535");
898module_param_named(max_packet_count, dwc_otg_module_params.max_packet_count, int, 0444);
899MODULE_PARM_DESC(max_packet_count, "The maximum number of packets in a transfer 15-511");
900module_param_named(host_channels, dwc_otg_module_params.host_channels, int, 0444);
901MODULE_PARM_DESC(host_channels, "The number of host channel registers to use 1-16");
902module_param_named(dev_endpoints, dwc_otg_module_params.dev_endpoints, int, 0444);
903MODULE_PARM_DESC(dev_endpoints, "The number of endpoints in addition to EP0 available for device mode 1-15");
904module_param_named(phy_type, dwc_otg_module_params.phy_type, int, 0444);
905MODULE_PARM_DESC(phy_type, "0=Reserved 1=UTMI+ 2=ULPI");
906module_param_named(phy_utmi_width, dwc_otg_module_params.phy_utmi_width, int, 0444);
907MODULE_PARM_DESC(phy_utmi_width, "Specifies the UTMI+ Data Width 8 or 16 bits");
908module_param_named(phy_ulpi_ddr, dwc_otg_module_params.phy_ulpi_ddr, int, 0444);
909MODULE_PARM_DESC(phy_ulpi_ddr, "ULPI at double or single data rate 0=Single 1=Double");
910module_param_named(phy_ulpi_ext_vbus, dwc_otg_module_params.phy_ulpi_ext_vbus, int, 0444);
911MODULE_PARM_DESC(phy_ulpi_ext_vbus, "ULPI PHY using internal or external vbus 0=Internal");
912module_param_named(i2c_enable, dwc_otg_module_params.i2c_enable, int, 0444);
913MODULE_PARM_DESC(i2c_enable, "FS PHY Interface");
914module_param_named(ulpi_fs_ls, dwc_otg_module_params.ulpi_fs_ls, int, 0444);
915MODULE_PARM_DESC(ulpi_fs_ls, "ULPI PHY FS/LS mode only");
916module_param_named(ts_dline, dwc_otg_module_params.ts_dline, int, 0444);
917MODULE_PARM_DESC(ts_dline, "Term select Dline pulsing for all PHYs");
918module_param_named(debug, g_dbg_lvl, int, 0444);
919MODULE_PARM_DESC(debug, "");
920
921module_param_named(en_multiple_tx_fifo, dwc_otg_module_params.en_multiple_tx_fifo, int, 0444);
922MODULE_PARM_DESC(en_multiple_tx_fifo, "Dedicated Non Periodic Tx FIFOs 0=disabled 1=enabled");
923module_param_named(dev_tx_fifo_size_1, dwc_otg_module_params.dev_tx_fifo_size[0], int, 0444);
924MODULE_PARM_DESC(dev_tx_fifo_size_1, "Number of words in the Tx FIFO 4-768");
925module_param_named(dev_tx_fifo_size_2, dwc_otg_module_params.dev_tx_fifo_size[1], int, 0444);
926MODULE_PARM_DESC(dev_tx_fifo_size_2, "Number of words in the Tx FIFO 4-768");
927module_param_named(dev_tx_fifo_size_3, dwc_otg_module_params.dev_tx_fifo_size[2], int, 0444);
928MODULE_PARM_DESC(dev_tx_fifo_size_3, "Number of words in the Tx FIFO 4-768");
929module_param_named(dev_tx_fifo_size_4, dwc_otg_module_params.dev_tx_fifo_size[3], int, 0444);
930MODULE_PARM_DESC(dev_tx_fifo_size_4, "Number of words in the Tx FIFO 4-768");
931module_param_named(dev_tx_fifo_size_5, dwc_otg_module_params.dev_tx_fifo_size[4], int, 0444);
932MODULE_PARM_DESC(dev_tx_fifo_size_5, "Number of words in the Tx FIFO 4-768");
933module_param_named(dev_tx_fifo_size_6, dwc_otg_module_params.dev_tx_fifo_size[5], int, 0444);
934MODULE_PARM_DESC(dev_tx_fifo_size_6, "Number of words in the Tx FIFO 4-768");
935module_param_named(dev_tx_fifo_size_7, dwc_otg_module_params.dev_tx_fifo_size[6], int, 0444);
936MODULE_PARM_DESC(dev_tx_fifo_size_7, "Number of words in the Tx FIFO 4-768");
937module_param_named(dev_tx_fifo_size_8, dwc_otg_module_params.dev_tx_fifo_size[7], int, 0444);
938MODULE_PARM_DESC(dev_tx_fifo_size_8, "Number of words in the Tx FIFO 4-768");
939module_param_named(dev_tx_fifo_size_9, dwc_otg_module_params.dev_tx_fifo_size[8], int, 0444);
940MODULE_PARM_DESC(dev_tx_fifo_size_9, "Number of words in the Tx FIFO 4-768");
941module_param_named(dev_tx_fifo_size_10, dwc_otg_module_params.dev_tx_fifo_size[9], int, 0444);
942MODULE_PARM_DESC(dev_tx_fifo_size_10, "Number of words in the Tx FIFO 4-768");
943module_param_named(dev_tx_fifo_size_11, dwc_otg_module_params.dev_tx_fifo_size[10], int, 0444);
944MODULE_PARM_DESC(dev_tx_fifo_size_11, "Number of words in the Tx FIFO 4-768");
945module_param_named(dev_tx_fifo_size_12, dwc_otg_module_params.dev_tx_fifo_size[11], int, 0444);
946MODULE_PARM_DESC(dev_tx_fifo_size_12, "Number of words in the Tx FIFO 4-768");
947module_param_named(dev_tx_fifo_size_13, dwc_otg_module_params.dev_tx_fifo_size[12], int, 0444);
948MODULE_PARM_DESC(dev_tx_fifo_size_13, "Number of words in the Tx FIFO 4-768");
949module_param_named(dev_tx_fifo_size_14, dwc_otg_module_params.dev_tx_fifo_size[13], int, 0444);
950MODULE_PARM_DESC(dev_tx_fifo_size_14, "Number of words in the Tx FIFO 4-768");
951module_param_named(dev_tx_fifo_size_15, dwc_otg_module_params.dev_tx_fifo_size[14], int, 0444);
952MODULE_PARM_DESC(dev_tx_fifo_size_15, "Number of words in the Tx FIFO 4-768");
953
954module_param_named(thr_ctl, dwc_otg_module_params.thr_ctl, int, 0444);
955MODULE_PARM_DESC(thr_ctl, "Thresholding enable flag bit 0 - non ISO Tx thr., 1 - ISO Tx thr., 2 - Rx thr.- bit 0=disabled 1=enabled");
956module_param_named(tx_thr_length, dwc_otg_module_params.tx_thr_length, int, 0444);
957MODULE_PARM_DESC(tx_thr_length, "Tx Threshold length in 32 bit DWORDs");
958module_param_named(rx_thr_length, dwc_otg_module_params.rx_thr_length, int, 0444);
959MODULE_PARM_DESC(rx_thr_length, "Rx Threshold length in 32 bit DWORDs");
960
961module_param_named(pti_enable, dwc_otg_module_params.pti_enable, int, 0444);
962MODULE_PARM_DESC(pti_enable, "Per Transfer Interrupt mode 0=disabled 1=enabled");
963
964module_param_named(mpi_enable, dwc_otg_module_params.mpi_enable, int, 0444);
965MODULE_PARM_DESC(mpi_enable, "Multiprocessor Interrupt mode 0=disabled 1=enabled");
966

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