Root/target/linux/cns3xxx/files/drivers/usb/dwc/otg_hcd_queue.c

1/* ==========================================================================
2 * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_hcd_queue.c $
3 * $Revision: #33 $
4 * $Date: 2008/07/15 $
5 * $Change: 1064918 $
6 *
7 * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
8 * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
9 * otherwise expressly agreed to in writing between Synopsys and you.
10 *
11 * The Software IS NOT an item of Licensed Software or Licensed Product under
12 * any End User Software License Agreement or Agreement for Licensed Product
13 * with Synopsys or any supplement thereto. You are permitted to use and
14 * redistribute this Software in source and binary forms, with or without
15 * modification, provided that redistributions of source code must retain this
16 * notice. You may not view, use, disclose, copy or distribute this file or
17 * any information contained herein except pursuant to this license grant from
18 * Synopsys. If you do not agree with this notice, including the disclaimer
19 * below, then you are not authorized to use the Software.
20 *
21 * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
25 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
26 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
27 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
28 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
29 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
30 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
31 * DAMAGE.
32 * ========================================================================== */
33#ifndef DWC_DEVICE_ONLY
34
35/**
36 * @file
37 *
38 * This file contains the functions to manage Queue Heads and Queue
39 * Transfer Descriptors.
40 */
41#include <linux/kernel.h>
42#include <linux/module.h>
43#include <linux/moduleparam.h>
44#include <linux/init.h>
45#include <linux/device.h>
46#include <linux/errno.h>
47#include <linux/list.h>
48#include <linux/interrupt.h>
49#include <linux/string.h>
50#include <linux/version.h>
51
52#include <mach/irqs.h>
53
54#include "otg_driver.h"
55#include "otg_hcd.h"
56#include "otg_regs.h"
57
58/**
59 * This function allocates and initializes a QH.
60 *
61 * @param hcd The HCD state structure for the DWC OTG controller.
62 * @param[in] urb Holds the information about the device/endpoint that we need
63 * to initialize the QH.
64 *
65 * @return Returns pointer to the newly allocated QH, or NULL on error. */
66dwc_otg_qh_t *dwc_otg_hcd_qh_create (dwc_otg_hcd_t *hcd, struct urb *urb)
67{
68    dwc_otg_qh_t *qh;
69
70    /* Allocate memory */
71    /** @todo add memflags argument */
72    qh = dwc_otg_hcd_qh_alloc ();
73    if (qh == NULL) {
74        return NULL;
75    }
76
77    dwc_otg_hcd_qh_init (hcd, qh, urb);
78    return qh;
79}
80
81/** Free each QTD in the QH's QTD-list then free the QH. QH should already be
82 * removed from a list. QTD list should already be empty if called from URB
83 * Dequeue.
84 *
85 * @param[in] hcd HCD instance.
86 * @param[in] qh The QH to free.
87 */
88void dwc_otg_hcd_qh_free (dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh)
89{
90    dwc_otg_qtd_t *qtd;
91    struct list_head *pos;
92    //unsigned long flags;
93
94    /* Free each QTD in the QTD list */
95
96#ifdef CONFIG_SMP
97    //the spinlock is locked before this function get called,
98    //but in case the lock is needed, the check function is preserved
99
100    //but in non-SMP mode, all spinlock is lockable.
101    //don't do the test in non-SMP mode
102
103    if(spin_trylock(&hcd->lock)) {
104        printk("%s: It is not supposed to be lockable!!\n",__func__);
105        BUG();
106    }
107#endif
108// SPIN_LOCK_IRQSAVE(&hcd->lock, flags)
109    for (pos = qh->qtd_list.next;
110         pos != &qh->qtd_list;
111         pos = qh->qtd_list.next)
112    {
113        list_del (pos);
114        qtd = dwc_list_to_qtd (pos);
115        dwc_otg_hcd_qtd_free (qtd);
116    }
117// SPIN_UNLOCK_IRQRESTORE(&hcd->lock, flags)
118
119    kfree (qh);
120    return;
121}
122
123/** Initializes a QH structure.
124 *
125 * @param[in] hcd The HCD state structure for the DWC OTG controller.
126 * @param[in] qh The QH to init.
127 * @param[in] urb Holds the information about the device/endpoint that we need
128 * to initialize the QH. */
129#define SCHEDULE_SLOP 10
130void dwc_otg_hcd_qh_init(dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh, struct urb *urb)
131{
132    char *speed, *type;
133    memset (qh, 0, sizeof (dwc_otg_qh_t));
134
135    /* Initialize QH */
136    switch (usb_pipetype(urb->pipe)) {
137    case PIPE_CONTROL:
138        qh->ep_type = USB_ENDPOINT_XFER_CONTROL;
139        break;
140    case PIPE_BULK:
141        qh->ep_type = USB_ENDPOINT_XFER_BULK;
142        break;
143    case PIPE_ISOCHRONOUS:
144        qh->ep_type = USB_ENDPOINT_XFER_ISOC;
145        break;
146    case PIPE_INTERRUPT:
147        qh->ep_type = USB_ENDPOINT_XFER_INT;
148        break;
149    }
150
151    qh->ep_is_in = usb_pipein(urb->pipe) ? 1 : 0;
152
153    qh->data_toggle = DWC_OTG_HC_PID_DATA0;
154    qh->maxp = usb_maxpacket(urb->dev, urb->pipe, !(usb_pipein(urb->pipe)));
155    INIT_LIST_HEAD(&qh->qtd_list);
156    INIT_LIST_HEAD(&qh->qh_list_entry);
157    qh->channel = NULL;
158    qh->speed = urb->dev->speed;
159
160    /* FS/LS Enpoint on HS Hub
161     * NOT virtual root hub */
162    qh->do_split = 0;
163    if (((urb->dev->speed == USB_SPEED_LOW) ||
164         (urb->dev->speed == USB_SPEED_FULL)) &&
165        (urb->dev->tt) && (urb->dev->tt->hub) && (urb->dev->tt->hub->devnum != 1))
166    {
167        DWC_DEBUGPL(DBG_HCD, "QH init: EP %d: TT found at hub addr %d, for port %d\n",
168               usb_pipeendpoint(urb->pipe), urb->dev->tt->hub->devnum,
169               urb->dev->ttport);
170        qh->do_split = 1;
171    }
172
173    if (qh->ep_type == USB_ENDPOINT_XFER_INT ||
174        qh->ep_type == USB_ENDPOINT_XFER_ISOC) {
175        /* Compute scheduling parameters once and save them. */
176        hprt0_data_t hprt;
177
178        /** @todo Account for split transfers in the bus time. */
179        int bytecount = dwc_hb_mult(qh->maxp) * dwc_max_packet(qh->maxp);
180        qh->usecs = NS_TO_US(usb_calc_bus_time(urb->dev->speed,
181                           usb_pipein(urb->pipe),
182                           (qh->ep_type == USB_ENDPOINT_XFER_ISOC),
183                           bytecount));
184
185        /* Start in a slightly future (micro)frame. */
186        qh->sched_frame = dwc_frame_num_inc(hcd->frame_number,
187                             SCHEDULE_SLOP);
188        qh->interval = urb->interval;
189#if 0
190        /* Increase interrupt polling rate for debugging. */
191        if (qh->ep_type == USB_ENDPOINT_XFER_INT) {
192            qh->interval = 8;
193        }
194#endif
195        hprt.d32 = dwc_read_reg32(hcd->core_if->host_if->hprt0);
196        if ((hprt.b.prtspd == DWC_HPRT0_PRTSPD_HIGH_SPEED) &&
197            ((urb->dev->speed == USB_SPEED_LOW) ||
198             (urb->dev->speed == USB_SPEED_FULL))) {
199            qh->interval *= 8;
200            qh->sched_frame |= 0x7;
201            qh->start_split_frame = qh->sched_frame;
202        }
203
204    }
205
206    DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD QH Initialized\n");
207    DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD QH - qh = %p\n", qh);
208    DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD QH - Device Address = %d\n",
209            urb->dev->devnum);
210    DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD QH - Endpoint %d, %s\n",
211            usb_pipeendpoint(urb->pipe),
212            usb_pipein(urb->pipe) == USB_DIR_IN ? "IN" : "OUT");
213
214    switch(urb->dev->speed) {
215    case USB_SPEED_LOW:
216        speed = "low";
217        break;
218    case USB_SPEED_FULL:
219        speed = "full";
220        break;
221    case USB_SPEED_HIGH:
222        speed = "high";
223        break;
224    default:
225        speed = "?";
226        break;
227    }
228    DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD QH - Speed = %s\n", speed);
229
230    switch (qh->ep_type) {
231    case USB_ENDPOINT_XFER_ISOC:
232        type = "isochronous";
233        break;
234    case USB_ENDPOINT_XFER_INT:
235        type = "interrupt";
236        break;
237    case USB_ENDPOINT_XFER_CONTROL:
238        type = "control";
239        break;
240    case USB_ENDPOINT_XFER_BULK:
241        type = "bulk";
242        break;
243    default:
244        type = "?";
245        break;
246    }
247    DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD QH - Type = %s\n",type);
248
249#ifdef DEBUG
250    if (qh->ep_type == USB_ENDPOINT_XFER_INT) {
251        DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD QH - usecs = %d\n",
252                qh->usecs);
253        DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD QH - interval = %d\n",
254                qh->interval);
255    }
256#endif
257
258    return;
259}
260
261/**
262 * Microframe scheduler
263 * track the total use in hcd->frame_usecs
264 * keep each qh use in qh->frame_usecs
265 * when surrendering the qh then donate the time back
266 */
267static const u16 max_uframe_usecs[] = { 100, 100, 100, 100, 100, 100, 30, 0 };
268
269/*
270 * called from dwc_otg_hcd.c:dwc_otg_hcd_init
271 */
272int init_hcd_usecs(dwc_otg_hcd_t *hcd)
273{
274    int i;
275
276    for (i = 0; i < 8; i++)
277        hcd->frame_usecs[i] = max_uframe_usecs[i];
278
279    return 0;
280}
281
282static int find_single_uframe(dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh)
283{
284    int i;
285    u16 utime;
286    int t_left;
287    int ret;
288    int done;
289
290    ret = -1;
291    utime = qh->usecs;
292    t_left = utime;
293    i = 0;
294    done = 0;
295    while (done == 0) {
296        /* At the start hcd->frame_usecs[i] = max_uframe_usecs[i]; */
297        if (utime <= hcd->frame_usecs[i]) {
298            hcd->frame_usecs[i] -= utime;
299            qh->frame_usecs[i] += utime;
300            t_left -= utime;
301            ret = i;
302            done = 1;
303            return ret;
304        } else {
305            i++;
306            if (i == 8) {
307                done = 1;
308                ret = -1;
309            }
310        }
311    }
312    return ret;
313}
314
315/*
316 * use this for FS apps that can span multiple uframes
317 */
318static int find_multi_uframe(dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh)
319{
320    int i;
321    int j;
322    u16 utime;
323    int t_left;
324    int ret;
325    int done;
326    u16 xtime;
327
328    ret = -1;
329    utime = qh->usecs;
330    t_left = utime;
331    i = 0;
332    done = 0;
333loop:
334    while (done == 0) {
335        if (hcd->frame_usecs[i] <= 0) {
336            i++;
337            if (i == 8) {
338                done = 1;
339                ret = -1;
340            }
341            goto loop;
342        }
343
344        /*
345         * We need n consequtive slots so use j as a start slot.
346         * j plus j+1 must be enough time (for now)
347         */
348        xtime = hcd->frame_usecs[i];
349        for (j = i + 1; j < 8; j++) {
350            /*
351             * if we add this frame remaining time to xtime we may
352             * be OK, if not we need to test j for a complete frame.
353             */
354            if ((xtime + hcd->frame_usecs[j]) < utime) {
355                if (hcd->frame_usecs[j] < max_uframe_usecs[j]) {
356                    j = 8;
357                    ret = -1;
358                    continue;
359                }
360            }
361            if (xtime >= utime) {
362                ret = i;
363                j = 8; /* stop loop with a good value ret */
364                continue;
365            }
366            /* add the frame time to x time */
367            xtime += hcd->frame_usecs[j];
368            /* we must have a fully available next frame or break */
369            if ((xtime < utime) &&
370                (hcd->frame_usecs[j] == max_uframe_usecs[j])) {
371                ret = -1;
372                j = 8; /* stop loop with a bad value ret */
373                continue;
374            }
375        }
376        if (ret >= 0) {
377            t_left = utime;
378            for (j = i; (t_left > 0) && (j < 8); j++) {
379                t_left -= hcd->frame_usecs[j];
380                if (t_left <= 0) {
381                    qh->frame_usecs[j] +=
382                        hcd->frame_usecs[j] + t_left;
383                    hcd->frame_usecs[j] = -t_left;
384                    ret = i;
385                    done = 1;
386                } else {
387                    qh->frame_usecs[j] +=
388                        hcd->frame_usecs[j];
389                    hcd->frame_usecs[j] = 0;
390                }
391            }
392        } else {
393            i++;
394            if (i == 8) {
395                done = 1;
396                ret = -1;
397            }
398        }
399    }
400    return ret;
401}
402
403static int find_uframe(dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh)
404{
405    int ret = -1;
406
407    if (qh->speed == USB_SPEED_HIGH)
408        /* if this is a hs transaction we need a full frame */
409        ret = find_single_uframe(hcd, qh);
410    else
411        /* FS transaction may need a sequence of frames */
412        ret = find_multi_uframe(hcd, qh);
413
414    return ret;
415}
416
417/**
418 * Checks that the max transfer size allowed in a host channel is large enough
419 * to handle the maximum data transfer in a single (micro)frame for a periodic
420 * transfer.
421 *
422 * @param hcd The HCD state structure for the DWC OTG controller.
423 * @param qh QH for a periodic endpoint.
424 *
425 * @return 0 if successful, negative error code otherwise.
426 */
427static int check_max_xfer_size(dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh)
428{
429    int status;
430    uint32_t max_xfer_size;
431    uint32_t max_channel_xfer_size;
432
433    status = 0;
434
435    max_xfer_size = dwc_max_packet(qh->maxp) * dwc_hb_mult(qh->maxp);
436    max_channel_xfer_size = hcd->core_if->core_params->max_transfer_size;
437
438    if (max_xfer_size > max_channel_xfer_size) {
439        DWC_NOTICE("%s: Periodic xfer length %d > "
440                "max xfer length for channel %d\n",
441                __func__, max_xfer_size, max_channel_xfer_size);
442        status = -ENOSPC;
443    }
444
445    return status;
446}
447
448/**
449 * Schedules an interrupt or isochronous transfer in the periodic schedule.
450 */
451static int schedule_periodic(dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh)
452{
453    int status;
454    struct usb_bus *bus = hcd_to_bus(dwc_otg_hcd_to_hcd(hcd));
455    int frame;
456
457    status = find_uframe(hcd, qh);
458    frame = -1;
459    if (status == 0) {
460        frame = 7;
461    } else {
462        if (status > 0)
463            frame = status - 1;
464    }
465    /* Set the new frame up */
466    if (frame > -1) {
467        qh->sched_frame &= ~0x7;
468        qh->sched_frame |= (frame & 7);
469    }
470    if (status != -1)
471        status = 0;
472    if (status) {
473        pr_notice("%s: Insufficient periodic bandwidth for "
474              "periodic transfer.\n", __func__);
475        return status;
476    }
477    status = check_max_xfer_size(hcd, qh);
478    if (status) {
479        pr_notice("%s: Channel max transfer size too small "
480              "for periodic transfer.\n", __func__);
481        return status;
482    }
483    /* Always start in the inactive schedule. */
484    list_add_tail(&qh->qh_list_entry, &hcd->periodic_sched_inactive);
485
486    /* Update claimed usecs per (micro)frame. */
487    hcd->periodic_usecs += qh->usecs;
488
489    /*
490     * Update average periodic bandwidth claimed and # periodic reqs for
491     * usbfs.
492     */
493    bus->bandwidth_allocated += qh->usecs / qh->interval;
494
495    if (qh->ep_type == USB_ENDPOINT_XFER_INT)
496        bus->bandwidth_int_reqs++;
497    else
498        bus->bandwidth_isoc_reqs++;
499
500    return status;
501}
502
503/**
504 * This function adds a QH to either the non periodic or periodic schedule if
505 * it is not already in the schedule. If the QH is already in the schedule, no
506 * action is taken.
507 *
508 * @return 0 if successful, negative error code otherwise.
509 */
510int dwc_otg_hcd_qh_add (dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh)
511{
512    //unsigned long flags;
513    int status = 0;
514
515#ifdef CONFIG_SMP
516    //the spinlock is locked before this function get called,
517    //but in case the lock is needed, the check function is preserved
518    //but in non-SMP mode, all spinlock is lockable.
519    //don't do the test in non-SMP mode
520
521    if(spin_trylock(&hcd->lock)) {
522        printk("%s: It is not supposed to be lockable!!\n",__func__);
523        BUG();
524    }
525#endif
526// SPIN_LOCK_IRQSAVE(&hcd->lock, flags)
527
528    if (!list_empty(&qh->qh_list_entry)) {
529        /* QH already in a schedule. */
530        goto done;
531    }
532
533    /* Add the new QH to the appropriate schedule */
534    if (dwc_qh_is_non_per(qh)) {
535        /* Always start in the inactive schedule. */
536        list_add_tail(&qh->qh_list_entry, &hcd->non_periodic_sched_inactive);
537    } else {
538        status = schedule_periodic(hcd, qh);
539    }
540
541 done:
542// SPIN_UNLOCK_IRQRESTORE(&hcd->lock, flags)
543
544    return status;
545}
546
547/**
548 * Removes an interrupt or isochronous transfer from the periodic schedule.
549 */
550static void deschedule_periodic(dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh)
551{
552    struct usb_bus *bus = hcd_to_bus(dwc_otg_hcd_to_hcd(hcd));
553    int i;
554
555    list_del_init(&qh->qh_list_entry);
556    /* Update claimed usecs per (micro)frame. */
557    hcd->periodic_usecs -= qh->usecs;
558    for (i = 0; i < 8; i++) {
559        hcd->frame_usecs[i] += qh->frame_usecs[i];
560        qh->frame_usecs[i] = 0;
561    }
562    /*
563     * Update average periodic bandwidth claimed and # periodic reqs for
564     * usbfs.
565     */
566    bus->bandwidth_allocated -= qh->usecs / qh->interval;
567
568    if (qh->ep_type == USB_ENDPOINT_XFER_INT)
569        bus->bandwidth_int_reqs--;
570    else
571        bus->bandwidth_isoc_reqs--;
572}
573
574/**
575 * Removes a QH from either the non-periodic or periodic schedule. Memory is
576 * not freed.
577 *
578 * @param[in] hcd The HCD state structure.
579 * @param[in] qh QH to remove from schedule. */
580void dwc_otg_hcd_qh_remove (dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh)
581{
582    //unsigned long flags;
583
584#ifdef CONFIG_SMP
585    //the spinlock is locked before this function get called,
586    //but in case the lock is needed, the check function is preserved
587    //but in non-SMP mode, all spinlock is lockable.
588    //don't do the test in non-SMP mode
589
590    if(spin_trylock(&hcd->lock)) {
591        printk("%s: It is not supposed to be lockable!!\n",__func__);
592        BUG();
593    }
594#endif
595// SPIN_LOCK_IRQSAVE(&hcd->lock, flags);
596
597    if (list_empty(&qh->qh_list_entry)) {
598        /* QH is not in a schedule. */
599        goto done;
600    }
601
602    if (dwc_qh_is_non_per(qh)) {
603        if (hcd->non_periodic_qh_ptr == &qh->qh_list_entry) {
604            hcd->non_periodic_qh_ptr = hcd->non_periodic_qh_ptr->next;
605        }
606        list_del_init(&qh->qh_list_entry);
607    } else {
608        deschedule_periodic(hcd, qh);
609    }
610
611 done:
612// SPIN_UNLOCK_IRQRESTORE(&hcd->lock, flags);
613    return;
614}
615
616/**
617 * Deactivates a QH. For non-periodic QHs, removes the QH from the active
618 * non-periodic schedule. The QH is added to the inactive non-periodic
619 * schedule if any QTDs are still attached to the QH.
620 *
621 * For periodic QHs, the QH is removed from the periodic queued schedule. If
622 * there are any QTDs still attached to the QH, the QH is added to either the
623 * periodic inactive schedule or the periodic ready schedule and its next
624 * scheduled frame is calculated. The QH is placed in the ready schedule if
625 * the scheduled frame has been reached already. Otherwise it's placed in the
626 * inactive schedule. If there are no QTDs attached to the QH, the QH is
627 * completely removed from the periodic schedule.
628 */
629void dwc_otg_hcd_qh_deactivate(dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh, int sched_next_periodic_split)
630{
631    unsigned long flags;
632    SPIN_LOCK_IRQSAVE(&hcd->lock, flags);
633
634    if (dwc_qh_is_non_per(qh)) {
635        dwc_otg_hcd_qh_remove(hcd, qh);
636        if (!list_empty(&qh->qtd_list)) {
637            /* Add back to inactive non-periodic schedule. */
638            dwc_otg_hcd_qh_add(hcd, qh);
639        }
640    } else {
641        uint16_t frame_number = dwc_otg_hcd_get_frame_number(dwc_otg_hcd_to_hcd(hcd));
642
643        if (qh->do_split) {
644            /* Schedule the next continuing periodic split transfer */
645            if (sched_next_periodic_split) {
646
647                qh->sched_frame = frame_number;
648                if (dwc_frame_num_le(frame_number,
649                             dwc_frame_num_inc(qh->start_split_frame, 1))) {
650                    /*
651                     * Allow one frame to elapse after start
652                     * split microframe before scheduling
653                     * complete split, but DONT if we are
654                     * doing the next start split in the
655                     * same frame for an ISOC out.
656                     */
657                    if ((qh->ep_type != USB_ENDPOINT_XFER_ISOC) || (qh->ep_is_in != 0)) {
658                        qh->sched_frame = dwc_frame_num_inc(qh->sched_frame, 1);
659                    }
660                }
661            } else {
662                qh->sched_frame = dwc_frame_num_inc(qh->start_split_frame,
663                                     qh->interval);
664                if (dwc_frame_num_le(qh->sched_frame, frame_number)) {
665                    qh->sched_frame = frame_number;
666                }
667                qh->sched_frame |= 0x7;
668                qh->start_split_frame = qh->sched_frame;
669            }
670        } else {
671            qh->sched_frame = dwc_frame_num_inc(qh->sched_frame, qh->interval);
672            if (dwc_frame_num_le(qh->sched_frame, frame_number)) {
673                qh->sched_frame = frame_number;
674            }
675        }
676
677        if (list_empty(&qh->qtd_list)) {
678            dwc_otg_hcd_qh_remove(hcd, qh);
679        } else {
680            /*
681             * Remove from periodic_sched_queued and move to
682             * appropriate queue.
683             */
684            if (qh->sched_frame == frame_number) {
685                list_move(&qh->qh_list_entry,
686                      &hcd->periodic_sched_ready);
687            } else {
688                list_move(&qh->qh_list_entry,
689                      &hcd->periodic_sched_inactive);
690            }
691        }
692    }
693
694    SPIN_UNLOCK_IRQRESTORE(&hcd->lock, flags);
695}
696
697/**
698 * This function allocates and initializes a QTD.
699 *
700 * @param[in] urb The URB to create a QTD from. Each URB-QTD pair will end up
701 * pointing to each other so each pair should have a unique correlation.
702 *
703 * @return Returns pointer to the newly allocated QTD, or NULL on error. */
704dwc_otg_qtd_t *dwc_otg_hcd_qtd_create (struct urb *urb)
705{
706    dwc_otg_qtd_t *qtd;
707
708    qtd = dwc_otg_hcd_qtd_alloc ();
709    if (qtd == NULL) {
710        return NULL;
711    }
712
713    dwc_otg_hcd_qtd_init (qtd, urb);
714    return qtd;
715}
716
717/**
718 * Initializes a QTD structure.
719 *
720 * @param[in] qtd The QTD to initialize.
721 * @param[in] urb The URB to use for initialization. */
722void dwc_otg_hcd_qtd_init (dwc_otg_qtd_t *qtd, struct urb *urb)
723{
724    memset (qtd, 0, sizeof (dwc_otg_qtd_t));
725    qtd->urb = urb;
726    if (usb_pipecontrol(urb->pipe)) {
727        /*
728         * The only time the QTD data toggle is used is on the data
729         * phase of control transfers. This phase always starts with
730         * DATA1.
731         */
732        qtd->data_toggle = DWC_OTG_HC_PID_DATA1;
733        qtd->control_phase = DWC_OTG_CONTROL_SETUP;
734    }
735
736    /* start split */
737    qtd->complete_split = 0;
738    qtd->isoc_split_pos = DWC_HCSPLIT_XACTPOS_ALL;
739    qtd->isoc_split_offset = 0;
740
741    /* Store the qtd ptr in the urb to reference what QTD. */
742    urb->hcpriv = qtd;
743    return;
744}
745
746/**
747 * This function adds a QTD to the QTD-list of a QH. It will find the correct
748 * QH to place the QTD into. If it does not find a QH, then it will create a
749 * new QH. If the QH to which the QTD is added is not currently scheduled, it
750 * is placed into the proper schedule based on its EP type.
751 *
752 * @param[in] qtd The QTD to add
753 * @param[in] dwc_otg_hcd The DWC HCD structure
754 *
755 * @return 0 if successful, negative error code otherwise.
756 */
757int dwc_otg_hcd_qtd_add (dwc_otg_qtd_t *qtd,
758             dwc_otg_hcd_t *dwc_otg_hcd)
759{
760    struct usb_host_endpoint *ep;
761    dwc_otg_qh_t *qh;
762    unsigned long flags;
763    int retval = 0;
764
765    struct urb *urb = qtd->urb;
766
767    SPIN_LOCK_IRQSAVE(&dwc_otg_hcd->lock, flags);
768
769    /*
770     * Get the QH which holds the QTD-list to insert to. Create QH if it
771     * doesn't exist.
772     */
773    ep = dwc_urb_to_endpoint(urb);
774    qh = (dwc_otg_qh_t *)ep->hcpriv;
775    if (qh == NULL) {
776        qh = dwc_otg_hcd_qh_create (dwc_otg_hcd, urb);
777        if (qh == NULL) {
778            goto done;
779        }
780        ep->hcpriv = qh;
781    }
782
783    retval = dwc_otg_hcd_qh_add(dwc_otg_hcd, qh);
784    if (retval == 0) {
785        list_add_tail(&qtd->qtd_list_entry, &qh->qtd_list);
786    }
787
788 done:
789    SPIN_UNLOCK_IRQRESTORE(&dwc_otg_hcd->lock, flags);
790
791    return retval;
792}
793
794#endif /* DWC_DEVICE_ONLY */
795

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