| 1 | --- a/arch/arm/Kconfig |
| 2 | +++ b/arch/arm/Kconfig |
| 3 | @@ -373,6 +373,7 @@ config ARCH_CNS3XXX |
| 4 | select MIGHT_HAVE_PCI |
| 5 | select PCI_DOMAINS if PCI |
| 6 | select HAVE_SMP |
| 7 | + select FIQ |
| 8 | help |
| 9 | Support for Cavium Networks CNS3XXX platform. |
| 10 | |
| 11 | --- a/arch/arm/kernel/fiq.c |
| 12 | +++ b/arch/arm/kernel/fiq.c |
| 13 | @@ -49,6 +49,8 @@ |
| 14 | |
| 15 | static unsigned long no_fiq_insn; |
| 16 | |
| 17 | +unsigned int fiq_number[2] = {0, 0}; |
| 18 | + |
| 19 | /* Default reacquire function |
| 20 | * - we always relinquish FIQ control |
| 21 | * - we always reacquire FIQ control |
| 22 | @@ -70,9 +72,12 @@ static struct fiq_handler *current_fiq = |
| 23 | |
| 24 | int show_fiq_list(struct seq_file *p, int prec) |
| 25 | { |
| 26 | - if (current_fiq != &default_owner) |
| 27 | - seq_printf(p, "%*s: %s\n", prec, "FIQ", |
| 28 | - current_fiq->name); |
| 29 | + if (current_fiq != &default_owner) { |
| 30 | + seq_printf(p, "%*s: ", prec, "FIQ"); |
| 31 | + seq_printf(p, "%10u ", fiq_number[0]); |
| 32 | + seq_printf(p, "%10u ", fiq_number[1]); |
| 33 | + seq_printf(p, " %s\n", current_fiq->name); |
| 34 | + } |
| 35 | |
| 36 | return 0; |
| 37 | } |
| 38 | --- a/arch/arm/kernel/smp.c |
| 39 | +++ b/arch/arm/kernel/smp.c |
| 40 | @@ -400,13 +400,13 @@ void show_ipi_list(struct seq_file *p, i |
| 41 | unsigned int cpu, i; |
| 42 | |
| 43 | for (i = 0; i < NR_IPI; i++) { |
| 44 | - seq_printf(p, "%*s%u: ", prec - 1, "IPI", i); |
| 45 | + seq_printf(p, "%*s%u:", prec - 1, "IPI", i); |
| 46 | |
| 47 | for_each_present_cpu(cpu) |
| 48 | seq_printf(p, "%10u ", |
| 49 | __get_irq_stat(cpu, ipi_irqs[i])); |
| 50 | |
| 51 | - seq_printf(p, " %s\n", ipi_types[i]); |
| 52 | + seq_printf(p, " %s\n", ipi_types[i]); |
| 53 | } |
| 54 | } |
| 55 | |
| 56 | --- a/arch/arm/mach-cns3xxx/Makefile |
| 57 | +++ b/arch/arm/mach-cns3xxx/Makefile |
| 58 | @@ -1,6 +1,6 @@ |
| 59 | obj-$(CONFIG_ARCH_CNS3XXX) += core.o pm.o devices.o |
| 60 | obj-$(CONFIG_PCI) += pcie.o |
| 61 | obj-$(CONFIG_MACH_CNS3420VB) += cns3420vb.o |
| 62 | -obj-$(CONFIG_SMP) += platsmp.o headsmp.o |
| 63 | +obj-$(CONFIG_SMP) += platsmp.o headsmp.o cns3xxx_fiq.o |
| 64 | obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o |
| 65 | obj-$(CONFIG_LOCAL_TIMERS) += localtimer.o |
| 66 | --- a/arch/arm/mach-cns3xxx/include/mach/cns3xxx.h |
| 67 | +++ b/arch/arm/mach-cns3xxx/include/mach/cns3xxx.h |
| 68 | @@ -294,6 +294,7 @@ |
| 69 | #define MISC_PCIE_INT_MASK(x) MISC_MEM_MAP(0x978 + (x) * 0x100) |
| 70 | #define MISC_PCIE_INT_STATUS(x) MISC_MEM_MAP(0x97C + (x) * 0x100) |
| 71 | |
| 72 | +#define MISC_FIQ_CPU(x) MISC_MEM_MAP(0xA58 - (x) * 0x4) |
| 73 | /* |
| 74 | * Power management and clock control |
| 75 | */ |
| 76 | --- a/arch/arm/mach-cns3xxx/include/mach/irqs.h |
| 77 | +++ b/arch/arm/mach-cns3xxx/include/mach/irqs.h |
| 78 | @@ -14,6 +14,7 @@ |
| 79 | #define IRQ_LOCALTIMER 29 |
| 80 | #define IRQ_LOCALWDOG 30 |
| 81 | #define IRQ_TC11MP_GIC_START 32 |
| 82 | +#define FIQ_START 0 |
| 83 | |
| 84 | #include <mach/cns3xxx.h> |
| 85 | |
| 86 | --- a/arch/arm/mm/Kconfig |
| 87 | +++ b/arch/arm/mm/Kconfig |
| 88 | @@ -793,7 +793,7 @@ config NEEDS_SYSCALL_FOR_CMPXCHG |
| 89 | |
| 90 | config DMA_CACHE_RWFO |
| 91 | bool "Enable read/write for ownership DMA cache maintenance" |
| 92 | - depends on CPU_V6K && SMP |
| 93 | + depends on CPU_V6K && SMP && !ARCH_CNS3XXX |
| 94 | default y |
| 95 | help |
| 96 | The Snoop Control Unit on ARM11MPCore does not detect the |
| 97 | |
