| 1 | --- a/arch/arm/mach-cns3xxx/core.c |
| 2 | +++ b/arch/arm/mach-cns3xxx/core.c |
| 3 | @@ -284,11 +284,24 @@ struct sys_timer cns3xxx_timer = { |
| 4 | |
| 5 | #ifdef CONFIG_CACHE_L2X0 |
| 6 | |
| 7 | +static int cns3xxx_l2x0_enable = 1; |
| 8 | + |
| 9 | +static int __init cns3xxx_l2x0_disable(char *s) |
| 10 | +{ |
| 11 | + cns3xxx_l2x0_enable = 0; |
| 12 | + return 1; |
| 13 | +} |
| 14 | +__setup("nol2x0", cns3xxx_l2x0_disable); |
| 15 | + |
| 16 | void __init cns3xxx_l2x0_init(void) |
| 17 | { |
| 18 | - void __iomem *base = ioremap(CNS3XXX_L2C_BASE, SZ_4K); |
| 19 | + void __iomem *base; |
| 20 | u32 val; |
| 21 | |
| 22 | + if (!cns3xxx_l2x0_enable) |
| 23 | + return; |
| 24 | + |
| 25 | + base = ioremap(CNS3XXX_L2C_BASE, SZ_4K); |
| 26 | if (WARN_ON(!base)) |
| 27 | return; |
| 28 | |
| 29 | @@ -321,6 +334,7 @@ void __init cns3xxx_l2x0_init(void) |
| 30 | /* 32 KiB, 8-way, parity disable */ |
| 31 | l2x0_init(base, 0x00540000, 0xfe000fff); |
| 32 | } |
| 33 | +arch_initcall(cns3xxx_l2x0_init); |
| 34 | |
| 35 | #endif /* CONFIG_CACHE_L2X0 */ |
| 36 | |
| 37 | --- a/arch/arm/mach-cns3xxx/cns3420vb.c |
| 38 | +++ b/arch/arm/mach-cns3xxx/cns3420vb.c |
| 39 | @@ -193,8 +193,6 @@ static struct platform_device *cns3420_p |
| 40 | |
| 41 | static void __init cns3420_init(void) |
| 42 | { |
| 43 | - cns3xxx_l2x0_init(); |
| 44 | - |
| 45 | platform_add_devices(cns3420_pdevs, ARRAY_SIZE(cns3420_pdevs)); |
| 46 | |
| 47 | cns3xxx_ahci_init(); |
| 48 | |
