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Root/target/linux/generic/files/crypto/ocf/hifn/hifn7751.c

1	/* $OpenBSD: hifn7751.c,v 1.120 2002/05/17 00:33:34 deraadt Exp $ */
2
3	/*-
4	* Invertex AEON / Hifn 7751 driver
5	* Copyright (c) 1999 Invertex Inc. All rights reserved.
6	* Copyright (c) 1999 Theo de Raadt
7	* Copyright (c) 2000-2001 Network Security Technologies, Inc.
8	* http://www.netsec.net
9	* Copyright (c) 2003 Hifn Inc.
10	*
11	* This driver is based on a previous driver by Invertex, for which they
12	* requested: Please send any comments, feedback, bug-fixes, or feature
13	* requests to software@invertex.com.
14	*
15	* Redistribution and use in source and binary forms, with or without
16	* modification, are permitted provided that the following conditions
17	* are met:
18	*
19	* 1. Redistributions of source code must retain the above copyright
20	* notice, this list of conditions and the following disclaimer.
21	* 2. Redistributions in binary form must reproduce the above copyright
22	* notice, this list of conditions and the following disclaimer in the
23	* documentation and/or other materials provided with the distribution.
24	* 3. The name of the author may not be used to endorse or promote products
25	* derived from this software without specific prior written permission.
26	*
27	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
28	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
29	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
30	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
31	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
32	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
33	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
34	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
35	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
36	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
37	*
38	* Effort sponsored in part by the Defense Advanced Research Projects
39	* Agency (DARPA) and Air Force Research Laboratory, Air Force
40	* Materiel Command, USAF, under agreement number F30602-01-2-0537.
41	*
42	*
43	__FBSDID("$FreeBSD: src/sys/dev/hifn/hifn7751.c,v 1.40 2007/03/21 03:42:49 sam Exp $");
44	*/
45
46	/*
47	* Driver for various Hifn encryption processors.
48	*/
49	#include <linux/version.h>
50	#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,38) && !defined(AUTOCONF_INCLUDED)
51	#include <linux/config.h>
52	#endif
53	#include <linux/module.h>
54	#include <linux/init.h>
55	#include <linux/list.h>
56	#include <linux/slab.h>
57	#include <linux/wait.h>
58	#include <linux/sched.h>
59	#include <linux/pci.h>
60	#include <linux/delay.h>
61	#include <linux/interrupt.h>
62	#include <linux/spinlock.h>
63	#include <linux/random.h>
64	#include <linux/skbuff.h>
65	#include <asm/io.h>
66
67	#include <cryptodev.h>
68	#include <uio.h>
69	#include <hifn/hifn7751reg.h>
70	#include <hifn/hifn7751var.h>
71
72	#if 1
73	#define DPRINTF(a...) if (hifn_debug) { \
74	printk("%s: ", sc ? \
75	device_get_nameunit(sc->sc_dev) : "hifn"); \
76	printk(a); \
77	} else
78	#else
79	#define DPRINTF(a...)
80	#endif
81
82	static inline int
83	pci_get_revid(struct pci_dev *dev)
84	{
85	u8 rid = 0;
86	pci_read_config_byte(dev, PCI_REVISION_ID, &rid);
87	return rid;
88	}
89
90	static struct hifn_stats hifnstats;
91
92	#define debug hifn_debug
93	int hifn_debug = 0;
94	module_param(hifn_debug, int, 0644);
95	MODULE_PARM_DESC(hifn_debug, "Enable debug");
96
97	int hifn_maxbatch = 1;
98	module_param(hifn_maxbatch, int, 0644);
99	MODULE_PARM_DESC(hifn_maxbatch, "max ops to batch w/o interrupt");
100
101	int hifn_cache_linesize = 0x10;
102	module_param(hifn_cache_linesize, int, 0444);
103	MODULE_PARM_DESC(hifn_cache_linesize, "PCI config cache line size");
104
105	#ifdef MODULE_PARM
106	char *hifn_pllconfig = NULL;
107	MODULE_PARM(hifn_pllconfig, "s");
108	#else
109	char hifn_pllconfig[32]; /* This setting is RO after loading */
110	module_param_string(hifn_pllconfig, hifn_pllconfig, 32, 0444);
111	#endif
112	MODULE_PARM_DESC(hifn_pllconfig, "PLL config, ie., pci66, ext33, ...");
113
114	#ifdef HIFN_VULCANDEV
115	#include <sys/conf.h>
116	#include <sys/uio.h>
117
118	static struct cdevsw vulcanpk_cdevsw; /* forward declaration */
119	#endif
120
121	/*
122	* Prototypes and count for the pci_device structure
123	*/
124	static int hifn_probe(struct pci_dev dev, const struct pci_device_id ent);
125	static void hifn_remove(struct pci_dev *dev);
126
127	static int hifn_newsession(device_t, u_int32_t , struct cryptoini );
128	static int hifn_freesession(device_t, u_int64_t);
129	static int hifn_process(device_t, struct cryptop *, int);
130
131	static device_method_t hifn_methods = {
132	/* crypto device methods */
133	DEVMETHOD(cryptodev_newsession, hifn_newsession),
134	DEVMETHOD(cryptodev_freesession,hifn_freesession),
135	DEVMETHOD(cryptodev_process, hifn_process),
136	};
137
138	static void hifn_reset_board(struct hifn_softc *, int);
139	static void hifn_reset_puc(struct hifn_softc *);
140	static void hifn_puc_wait(struct hifn_softc *);
141	static int hifn_enable_crypto(struct hifn_softc *);
142	static void hifn_set_retry(struct hifn_softc *sc);
143	static void hifn_init_dma(struct hifn_softc *);
144	static void hifn_init_pci_registers(struct hifn_softc *);
145	static int hifn_sramsize(struct hifn_softc *);
146	static int hifn_dramsize(struct hifn_softc *);
147	static int hifn_ramtype(struct hifn_softc *);
148	static void hifn_sessions(struct hifn_softc *);
149	#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,19)
150	static irqreturn_t hifn_intr(int irq, void *arg);
151	#else
152	static irqreturn_t hifn_intr(int irq, void arg, struct pt_regs regs);
153	#endif
154	static u_int hifn_write_command(struct hifn_command , u_int8_t );
155	static u_int32_t hifn_next_signature(u_int32_t a, u_int cnt);
156	static void hifn_callback(struct hifn_softc , struct hifn_command , u_int8_t *);
157	static int hifn_crypto(struct hifn_softc , struct hifn_command , struct cryptop *, int);
158	static int hifn_readramaddr(struct hifn_softc , int, u_int8_t );
159	static int hifn_writeramaddr(struct hifn_softc , int, u_int8_t );
160	static int hifn_dmamap_load_src(struct hifn_softc , struct hifn_command );
161	static int hifn_dmamap_load_dst(struct hifn_softc , struct hifn_command );
162	static int hifn_init_pubrng(struct hifn_softc *);
163	static void hifn_tick(unsigned long arg);
164	static void hifn_abort(struct hifn_softc *);
165	static void hifn_alloc_slot(struct hifn_softc , int , int , int , int *);
166
167	static void hifn_write_reg_0(struct hifn_softc *, bus_size_t, u_int32_t);
168	static void hifn_write_reg_1(struct hifn_softc *, bus_size_t, u_int32_t);
169
170	#ifdef CONFIG_OCF_RANDOMHARVEST
171	static int hifn_read_random(void arg, u_int32_t buf, int len);
172	#endif
173
174	#define HIFN_MAX_CHIPS 8
175	static struct hifn_softc *hifn_chip_idx[HIFN_MAX_CHIPS];
176
177	static __inline u_int32_t
178	READ_REG_0(struct hifn_softc *sc, bus_size_t reg)
179	{
180	u_int32_t v = readl(sc->sc_bar0 + reg);
181	sc->sc_bar0_lastreg = (bus_size_t) -1;
182	return (v);
183	}
184	#define WRITE_REG_0(sc, reg, val) hifn_write_reg_0(sc, reg, val)
185
186	static __inline u_int32_t
187	READ_REG_1(struct hifn_softc *sc, bus_size_t reg)
188	{
189	u_int32_t v = readl(sc->sc_bar1 + reg);
190	sc->sc_bar1_lastreg = (bus_size_t) -1;
191	return (v);
192	}
193	#define WRITE_REG_1(sc, reg, val) hifn_write_reg_1(sc, reg, val)
194
195	/*
196	* map in a given buffer (great on some arches :-)
197	*/
198
199	static int
200	pci_map_uio(struct hifn_softc sc, struct hifn_operand buf, struct uio *uio)
201	{
202	struct iovec *iov = uio->uio_iov;
203
204	DPRINTF("%s()\n", __FUNCTION__);
205
206	buf->mapsize = 0;
207	for (buf->nsegs = 0; buf->nsegs < uio->uio_iovcnt; ) {
208	buf->segs[buf->nsegs].ds_addr = pci_map_single(sc->sc_pcidev,
209	iov->iov_base, iov->iov_len,
210	PCI_DMA_BIDIRECTIONAL);
211	buf->segs[buf->nsegs].ds_len = iov->iov_len;
212	buf->mapsize += iov->iov_len;
213	iov++;
214	buf->nsegs++;
215	}
216	/* identify this buffer by the first segment */
217	buf->map = (void *) buf->segs[0].ds_addr;
218	return(0);
219	}
220
221	/*
222	* map in a given sk_buff
223	*/
224
225	static int
226	pci_map_skb(struct hifn_softc sc,struct hifn_operand buf,struct sk_buff *skb)
227	{
228	int i;
229
230	DPRINTF("%s()\n", __FUNCTION__);
231
232	buf->mapsize = 0;
233
234	buf->segs[0].ds_addr = pci_map_single(sc->sc_pcidev,
235	skb->data, skb_headlen(skb), PCI_DMA_BIDIRECTIONAL);
236	buf->segs[0].ds_len = skb_headlen(skb);
237	buf->mapsize += buf->segs[0].ds_len;
238
239	buf->nsegs = 1;
240
241	for (i = 0; i < skb_shinfo(skb)->nr_frags; ) {
242	buf->segs[buf->nsegs].ds_len = skb_shinfo(skb)->frags[i].size;
243	buf->segs[buf->nsegs].ds_addr = pci_map_single(sc->sc_pcidev,
244	page_address(skb_frag_page(&skb_shinfo(skb)->frags[i])) +
245	skb_shinfo(skb)->frags[i].page_offset,
246	buf->segs[buf->nsegs].ds_len, PCI_DMA_BIDIRECTIONAL);
247	buf->mapsize += buf->segs[buf->nsegs].ds_len;
248	buf->nsegs++;
249	}
250
251	/* identify this buffer by the first segment */
252	buf->map = (void *) buf->segs[0].ds_addr;
253	return(0);
254	}
255
256	/*
257	* map in a given contiguous buffer
258	*/
259
260	static int
261	pci_map_buf(struct hifn_softc sc,struct hifn_operand buf, void *b, int len)
262	{
263	DPRINTF("%s()\n", __FUNCTION__);
264
265	buf->mapsize = 0;
266	buf->segs[0].ds_addr = pci_map_single(sc->sc_pcidev,
267	b, len, PCI_DMA_BIDIRECTIONAL);
268	buf->segs[0].ds_len = len;
269	buf->mapsize += buf->segs[0].ds_len;
270	buf->nsegs = 1;
271
272	/* identify this buffer by the first segment */
273	buf->map = (void *) buf->segs[0].ds_addr;
274	return(0);
275	}
276
277	#if 0 /* not needed at this time */
278	static void
279	pci_sync_iov(struct hifn_softc sc, struct hifn_operand buf)
280	{
281	int i;
282
283	DPRINTF("%s()\n", __FUNCTION__);
284	for (i = 0; i < buf->nsegs; i++)
285	pci_dma_sync_single_for_cpu(sc->sc_pcidev, buf->segs[i].ds_addr,
286	buf->segs[i].ds_len, PCI_DMA_BIDIRECTIONAL);
287	}
288	#endif
289
290	static void
291	pci_unmap_buf(struct hifn_softc sc, struct hifn_operand buf)
292	{
293	int i;
294	DPRINTF("%s()\n", __FUNCTION__);
295	for (i = 0; i < buf->nsegs; i++) {
296	pci_unmap_single(sc->sc_pcidev, buf->segs[i].ds_addr,
297	buf->segs[i].ds_len, PCI_DMA_BIDIRECTIONAL);
298	buf->segs[i].ds_addr = 0;
299	buf->segs[i].ds_len = 0;
300	}
301	buf->nsegs = 0;
302	buf->mapsize = 0;
303	buf->map = 0;
304	}
305
306	static const char*
307	hifn_partname(struct hifn_softc *sc)
308	{
309	/* XXX sprintf numbers when not decoded */
310	switch (pci_get_vendor(sc->sc_pcidev)) {
311	case PCI_VENDOR_HIFN:
312	switch (pci_get_device(sc->sc_pcidev)) {
313	case PCI_PRODUCT_HIFN_6500: return "Hifn 6500";
314	case PCI_PRODUCT_HIFN_7751: return "Hifn 7751";
315	case PCI_PRODUCT_HIFN_7811: return "Hifn 7811";
316	case PCI_PRODUCT_HIFN_7951: return "Hifn 7951";
317	case PCI_PRODUCT_HIFN_7955: return "Hifn 7955";
318	case PCI_PRODUCT_HIFN_7956: return "Hifn 7956";
319	}
320	return "Hifn unknown-part";
321	case PCI_VENDOR_INVERTEX:
322	switch (pci_get_device(sc->sc_pcidev)) {
323	case PCI_PRODUCT_INVERTEX_AEON: return "Invertex AEON";
324	}
325	return "Invertex unknown-part";
326	case PCI_VENDOR_NETSEC:
327	switch (pci_get_device(sc->sc_pcidev)) {
328	case PCI_PRODUCT_NETSEC_7751: return "NetSec 7751";
329	}
330	return "NetSec unknown-part";
331	}
332	return "Unknown-vendor unknown-part";
333	}
334
335	static u_int
336	checkmaxmin(struct pci_dev dev, const char what, u_int v, u_int min, u_int max)
337	{
338	struct hifn_softc *sc = pci_get_drvdata(dev);
339	if (v > max) {
340	device_printf(sc->sc_dev, "Warning, %s %u out of range, "
341	"using max %u\n", what, v, max);
342	v = max;
343	} else if (v < min) {
344	device_printf(sc->sc_dev, "Warning, %s %u out of range, "
345	"using min %u\n", what, v, min);
346	v = min;
347	}
348	return v;
349	}
350
351	/*
352	* Select PLL configuration for 795x parts. This is complicated in
353	* that we cannot determine the optimal parameters without user input.
354	* The reference clock is derived from an external clock through a
355	* multiplier. The external clock is either the host bus (i.e. PCI)
356	* or an external clock generator. When using the PCI bus we assume
357	* the clock is either 33 or 66 MHz; for an external source we cannot
358	* tell the speed.
359	*
360	* PLL configuration is done with a string: "pci" for PCI bus, or "ext"
361	* for an external source, followed by the frequency. We calculate
362	* the appropriate multiplier and PLL register contents accordingly.
363	* When no configuration is given we default to "pci66" since that
364	* always will allow the card to work. If a card is using the PCI
365	* bus clock and in a 33MHz slot then it will be operating at half
366	* speed until the correct information is provided.
367	*
368	* We use a default setting of "ext66" because according to Mike Ham
369	* of HiFn, almost every board in existence has an external crystal
370	* populated at 66Mhz. Using PCI can be a problem on modern motherboards,
371	* because PCI33 can have clocks from 0 to 33Mhz, and some have
372	* non-PCI-compliant spread-spectrum clocks, which can confuse the pll.
373	*/
374	static void
375	hifn_getpllconfig(struct pci_dev dev, u_int pll)
376	{
377	const char *pllspec = hifn_pllconfig;
378	u_int freq, mul, fl, fh;
379	u_int32_t pllconfig;
380	char *nxt;
381
382	if (pllspec == NULL)
383	pllspec = "ext66";
384	fl = 33, fh = 66;
385	pllconfig = 0;
386	if (strncmp(pllspec, "ext", 3) == 0) {
387	pllspec += 3;
388	pllconfig \|= HIFN_PLL_REF_SEL;
389	switch (pci_get_device(dev)) {
390	case PCI_PRODUCT_HIFN_7955:
391	case PCI_PRODUCT_HIFN_7956:
392	fl = 20, fh = 100;
393	break;
394	#ifdef notyet
395	case PCI_PRODUCT_HIFN_7954:
396	fl = 20, fh = 66;
397	break;
398	#endif
399	}
400	} else if (strncmp(pllspec, "pci", 3) == 0)
401	pllspec += 3;
402	freq = strtoul(pllspec, &nxt, 10);
403	if (nxt == pllspec)
404	freq = 66;
405	else
406	freq = checkmaxmin(dev, "frequency", freq, fl, fh);
407	/*
408	* Calculate multiplier. We target a Fck of 266 MHz,
409	* allowing only even values, possibly rounded down.
410	* Multipliers > 8 must set the charge pump current.
411	*/
412	mul = checkmaxmin(dev, "PLL divisor", (266 / freq) &~ 1, 2, 12);
413	pllconfig \|= (mul / 2 - 1) << HIFN_PLL_ND_SHIFT;
414	if (mul > 8)
415	pllconfig \|= HIFN_PLL_IS;
416	*pll = pllconfig;
417	}
418
419	/*
420	* Attach an interface that successfully probed.
421	*/
422	static int
423	hifn_probe(struct pci_dev dev, const struct pci_device_id ent)
424	{
425	struct hifn_softc *sc = NULL;
426	char rbase;
427	u_int16_t ena, rev;
428	int rseg, rc;
429	unsigned long mem_start, mem_len;
430	static int num_chips = 0;
431
432	DPRINTF("%s()\n", __FUNCTION__);
433
434	if (pci_enable_device(dev) < 0)
435	return(-ENODEV);
436
437	if (pci_set_mwi(dev))
438	return(-ENODEV);
439
440	if (!dev->irq) {
441	printk("hifn: found device with no IRQ assigned. check BIOS settings!");
442	pci_disable_device(dev);
443	return(-ENODEV);
444	}
445
446	sc = (struct hifn_softc ) kmalloc(sizeof(sc), GFP_KERNEL);
447	if (!sc)
448	return(-ENOMEM);
449	memset(sc, 0, sizeof(*sc));
450
451	softc_device_init(sc, "hifn", num_chips, hifn_methods);
452
453	sc->sc_pcidev = dev;
454	sc->sc_irq = -1;
455	sc->sc_cid = -1;
456	sc->sc_num = num_chips++;
457	if (sc->sc_num < HIFN_MAX_CHIPS)
458	hifn_chip_idx[sc->sc_num] = sc;
459
460	pci_set_drvdata(sc->sc_pcidev, sc);
461
462	spin_lock_init(&sc->sc_mtx);
463
464	/* XXX handle power management */
465
466	/*
467	* The 7951 and 795x have a random number generator and
468	* public key support; note this.
469	*/
470	if (pci_get_vendor(dev) == PCI_VENDOR_HIFN &&
471	(pci_get_device(dev) == PCI_PRODUCT_HIFN_7951 \|\|
472	pci_get_device(dev) == PCI_PRODUCT_HIFN_7955 \|\|
473	pci_get_device(dev) == PCI_PRODUCT_HIFN_7956))
474	sc->sc_flags = HIFN_HAS_RNG \| HIFN_HAS_PUBLIC;
475	/*
476	* The 7811 has a random number generator and
477	* we also note it's identity 'cuz of some quirks.
478	*/
479	if (pci_get_vendor(dev) == PCI_VENDOR_HIFN &&
480	pci_get_device(dev) == PCI_PRODUCT_HIFN_7811)
481	sc->sc_flags \|= HIFN_IS_7811 \| HIFN_HAS_RNG;
482
483	/*
484	* The 795x parts support AES.
485	*/
486	if (pci_get_vendor(dev) == PCI_VENDOR_HIFN &&
487	(pci_get_device(dev) == PCI_PRODUCT_HIFN_7955 \|\|
488	pci_get_device(dev) == PCI_PRODUCT_HIFN_7956)) {
489	sc->sc_flags \|= HIFN_IS_7956 \| HIFN_HAS_AES;
490	/*
491	* Select PLL configuration. This depends on the
492	* bus and board design and must be manually configured
493	* if the default setting is unacceptable.
494	*/
495	hifn_getpllconfig(dev, &sc->sc_pllconfig);
496	}
497
498	/*
499	* Setup PCI resources. Note that we record the bus
500	* tag and handle for each register mapping, this is
501	* used by the READ_REG_0, WRITE_REG_0, READ_REG_1,
502	* and WRITE_REG_1 macros throughout the driver.
503	*/
504	mem_start = pci_resource_start(sc->sc_pcidev, 0);
505	mem_len = pci_resource_len(sc->sc_pcidev, 0);
506	sc->sc_bar0 = (ocf_iomem_t) ioremap(mem_start, mem_len);
507	if (!sc->sc_bar0) {
508	device_printf(sc->sc_dev, "cannot map bar%d register space\n", 0);
509	goto fail;
510	}
511	sc->sc_bar0_lastreg = (bus_size_t) -1;
512
513	mem_start = pci_resource_start(sc->sc_pcidev, 1);
514	mem_len = pci_resource_len(sc->sc_pcidev, 1);
515	sc->sc_bar1 = (ocf_iomem_t) ioremap(mem_start, mem_len);
516	if (!sc->sc_bar1) {
517	device_printf(sc->sc_dev, "cannot map bar%d register space\n", 1);
518	goto fail;
519	}
520	sc->sc_bar1_lastreg = (bus_size_t) -1;
521
522	/* fix up the bus size */
523	if (pci_set_dma_mask(dev, DMA_32BIT_MASK)) {
524	device_printf(sc->sc_dev, "No usable DMA configuration, aborting.\n");
525	goto fail;
526	}
527	if (pci_set_consistent_dma_mask(dev, DMA_32BIT_MASK)) {
528	device_printf(sc->sc_dev,
529	"No usable consistent DMA configuration, aborting.\n");
530	goto fail;
531	}
532
533	hifn_set_retry(sc);
534
535	/*
536	* Setup the area where the Hifn DMA's descriptors
537	* and associated data structures.
538	*/
539	sc->sc_dma = (struct hifn_dma *) pci_alloc_consistent(dev,
540	sizeof(*sc->sc_dma),
541	&sc->sc_dma_physaddr);
542	if (!sc->sc_dma) {
543	device_printf(sc->sc_dev, "cannot alloc sc_dma\n");
544	goto fail;
545	}
546	bzero(sc->sc_dma, sizeof(*sc->sc_dma));
547
548	/*
549	* Reset the board and do the ``secret handshake''
550	* to enable the crypto support. Then complete the
551	* initialization procedure by setting up the interrupt
552	* and hooking in to the system crypto support so we'll
553	* get used for system services like the crypto device,
554	* IPsec, RNG device, etc.
555	*/
556	hifn_reset_board(sc, 0);
557
558	if (hifn_enable_crypto(sc) != 0) {
559	device_printf(sc->sc_dev, "crypto enabling failed\n");
560	goto fail;
561	}
562	hifn_reset_puc(sc);
563
564	hifn_init_dma(sc);
565	hifn_init_pci_registers(sc);
566
567	pci_set_master(sc->sc_pcidev);
568
569	/* XXX can't dynamically determine ram type for 795x; force dram */
570	if (sc->sc_flags & HIFN_IS_7956)
571	sc->sc_drammodel = 1;
572	else if (hifn_ramtype(sc))
573	goto fail;
574
575	if (sc->sc_drammodel == 0)
576	hifn_sramsize(sc);
577	else
578	hifn_dramsize(sc);
579
580	/*
581	* Workaround for NetSec 7751 rev A: half ram size because two
582	* of the address lines were left floating
583	*/
584	if (pci_get_vendor(dev) == PCI_VENDOR_NETSEC &&
585	pci_get_device(dev) == PCI_PRODUCT_NETSEC_7751 &&
586	pci_get_revid(dev) == 0x61) /XXX???/
587	sc->sc_ramsize >>= 1;
588
589	/*
590	* Arrange the interrupt line.
591	*/
592	rc = request_irq(dev->irq, hifn_intr, IRQF_SHARED, "hifn", sc);
593	if (rc) {
594	device_printf(sc->sc_dev, "could not map interrupt: %d\n", rc);
595	goto fail;
596	}
597	sc->sc_irq = dev->irq;
598
599	hifn_sessions(sc);
600
601	/*
602	* NB: Keep only the low 16 bits; this masks the chip id
603	* from the 7951.
604	*/
605	rev = READ_REG_1(sc, HIFN_1_REVID) & 0xffff;
606
607	rseg = sc->sc_ramsize / 1024;
608	rbase = 'K';
609	if (sc->sc_ramsize >= (1024 * 1024)) {
610	rbase = 'M';
611	rseg /= 1024;
612	}
613	device_printf(sc->sc_dev, "%s, rev %u, %d%cB %cram",
614	hifn_partname(sc), rev,
615	rseg, rbase, sc->sc_drammodel ? 'd' : 's');
616	if (sc->sc_flags & HIFN_IS_7956)
617	printf(", pll=0x%x<%s clk, %ux mult>",
618	sc->sc_pllconfig,
619	sc->sc_pllconfig & HIFN_PLL_REF_SEL ? "ext" : "pci",
620	2 + 2*((sc->sc_pllconfig & HIFN_PLL_ND) >> 11));
621	printf("\n");
622
623	sc->sc_cid = crypto_get_driverid(softc_get_device(sc),CRYPTOCAP_F_HARDWARE);
624	if (sc->sc_cid < 0) {
625	device_printf(sc->sc_dev, "could not get crypto driver id\n");
626	goto fail;
627	}
628
629	WRITE_REG_0(sc, HIFN_0_PUCNFG,
630	READ_REG_0(sc, HIFN_0_PUCNFG) \| HIFN_PUCNFG_CHIPID);
631	ena = READ_REG_0(sc, HIFN_0_PUSTAT) & HIFN_PUSTAT_CHIPENA;
632
633	switch (ena) {
634	case HIFN_PUSTAT_ENA_2:
635	crypto_register(sc->sc_cid, CRYPTO_3DES_CBC, 0, 0);
636	crypto_register(sc->sc_cid, CRYPTO_ARC4, 0, 0);
637	if (sc->sc_flags & HIFN_HAS_AES)
638	crypto_register(sc->sc_cid, CRYPTO_AES_CBC, 0, 0);
639	/FALLTHROUGH/
640	case HIFN_PUSTAT_ENA_1:
641	crypto_register(sc->sc_cid, CRYPTO_MD5, 0, 0);
642	crypto_register(sc->sc_cid, CRYPTO_SHA1, 0, 0);
643	crypto_register(sc->sc_cid, CRYPTO_MD5_HMAC, 0, 0);
644	crypto_register(sc->sc_cid, CRYPTO_SHA1_HMAC, 0, 0);
645	crypto_register(sc->sc_cid, CRYPTO_DES_CBC, 0, 0);
646	break;
647	}
648
649	if (sc->sc_flags & (HIFN_HAS_PUBLIC \| HIFN_HAS_RNG))
650	hifn_init_pubrng(sc);
651
652	init_timer(&sc->sc_tickto);
653	sc->sc_tickto.function = hifn_tick;
654	sc->sc_tickto.data = (unsigned long) sc->sc_num;
655	mod_timer(&sc->sc_tickto, jiffies + HZ);
656
657	return (0);
658
659	fail:
660	if (sc->sc_cid >= 0)
661	crypto_unregister_all(sc->sc_cid);
662	if (sc->sc_irq != -1)
663	free_irq(sc->sc_irq, sc);
664	if (sc->sc_dma) {
665	/* Turn off DMA polling */
666	WRITE_REG_1(sc, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MSTRESET \|
667	HIFN_DMACNFG_DMARESET \| HIFN_DMACNFG_MODE);
668
669	pci_free_consistent(sc->sc_pcidev,
670	sizeof(*sc->sc_dma),
671	sc->sc_dma, sc->sc_dma_physaddr);
672	}
673	kfree(sc);
674	return (-ENXIO);
675	}
676
677	/*
678	* Detach an interface that successfully probed.
679	*/
680	static void
681	hifn_remove(struct pci_dev *dev)
682	{
683	struct hifn_softc *sc = pci_get_drvdata(dev);
684	unsigned long l_flags;
685
686	DPRINTF("%s()\n", __FUNCTION__);
687
688	KASSERT(sc != NULL, ("hifn_detach: null software carrier!"));
689
690	/* disable interrupts */
691	HIFN_LOCK(sc);
692	WRITE_REG_1(sc, HIFN_1_DMA_IER, 0);
693	HIFN_UNLOCK(sc);
694
695	/XXX other resources /
696	del_timer_sync(&sc->sc_tickto);
697
698	/* Turn off DMA polling */
699	WRITE_REG_1(sc, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MSTRESET \|
700	HIFN_DMACNFG_DMARESET \| HIFN_DMACNFG_MODE);
701
702	crypto_unregister_all(sc->sc_cid);
703
704	free_irq(sc->sc_irq, sc);
705
706	pci_free_consistent(sc->sc_pcidev, sizeof(*sc->sc_dma),
707	sc->sc_dma, sc->sc_dma_physaddr);
708	}
709
710
711	static int
712	hifn_init_pubrng(struct hifn_softc *sc)
713	{
714	int i;
715
716	DPRINTF("%s()\n", __FUNCTION__);
717
718	if ((sc->sc_flags & HIFN_IS_7811) == 0) {
719	/* Reset 7951 public key/rng engine */
720	WRITE_REG_1(sc, HIFN_1_PUB_RESET,
721	READ_REG_1(sc, HIFN_1_PUB_RESET) \| HIFN_PUBRST_RESET);
722
723	for (i = 0; i < 100; i++) {
724	DELAY(1000);
725	if ((READ_REG_1(sc, HIFN_1_PUB_RESET) &
726	HIFN_PUBRST_RESET) == 0)
727	break;
728	}
729
730	if (i == 100) {
731	device_printf(sc->sc_dev, "public key init failed\n");
732	return (1);
733	}
734	}
735
736	/* Enable the rng, if available */
737	#ifdef CONFIG_OCF_RANDOMHARVEST
738	if (sc->sc_flags & HIFN_HAS_RNG) {
739	if (sc->sc_flags & HIFN_IS_7811) {
740	u_int32_t r;
741	r = READ_REG_1(sc, HIFN_1_7811_RNGENA);
742	if (r & HIFN_7811_RNGENA_ENA) {
743	r &= ~HIFN_7811_RNGENA_ENA;
744	WRITE_REG_1(sc, HIFN_1_7811_RNGENA, r);
745	}
746	WRITE_REG_1(sc, HIFN_1_7811_RNGCFG,
747	HIFN_7811_RNGCFG_DEFL);
748	r \|= HIFN_7811_RNGENA_ENA;
749	WRITE_REG_1(sc, HIFN_1_7811_RNGENA, r);
750	} else
751	WRITE_REG_1(sc, HIFN_1_RNG_CONFIG,
752	READ_REG_1(sc, HIFN_1_RNG_CONFIG) \|
753	HIFN_RNGCFG_ENA);
754
755	sc->sc_rngfirst = 1;
756	crypto_rregister(sc->sc_cid, hifn_read_random, sc);
757	}
758	#endif
759
760	/* Enable public key engine, if available */
761	if (sc->sc_flags & HIFN_HAS_PUBLIC) {
762	WRITE_REG_1(sc, HIFN_1_PUB_IEN, HIFN_PUBIEN_DONE);
763	sc->sc_dmaier \|= HIFN_DMAIER_PUBDONE;
764	WRITE_REG_1(sc, HIFN_1_DMA_IER, sc->sc_dmaier);
765	#ifdef HIFN_VULCANDEV
766	sc->sc_pkdev = make_dev(&vulcanpk_cdevsw, 0,
767	UID_ROOT, GID_WHEEL, 0666,
768	"vulcanpk");
769	sc->sc_pkdev->si_drv1 = sc;
770	#endif
771	}
772
773	return (0);
774	}
775
776	#ifdef CONFIG_OCF_RANDOMHARVEST
777	static int
778	hifn_read_random(void arg, u_int32_t buf, int len)
779	{
780	struct hifn_softc sc = (struct hifn_softc ) arg;
781	u_int32_t sts;
782	int i, rc = 0;
783
784	if (len <= 0)
785	return rc;
786
787	if (sc->sc_flags & HIFN_IS_7811) {
788	/* ONLY VALID ON 7811!!!! */
789	for (i = 0; i < 5; i++) {
790	sts = READ_REG_1(sc, HIFN_1_7811_RNGSTS);
791	if (sts & HIFN_7811_RNGSTS_UFL) {
792	device_printf(sc->sc_dev,
793	"RNG underflow: disabling\n");
794	/* DAVIDM perhaps return -1 */
795	break;
796	}
797	if ((sts & HIFN_7811_RNGSTS_RDY) == 0)
798	break;
799
800	/*
801	* There are at least two words in the RNG FIFO
802	* at this point.
803	*/
804	if (rc < len)
805	buf[rc++] = READ_REG_1(sc, HIFN_1_7811_RNGDAT);
806	if (rc < len)
807	buf[rc++] = READ_REG_1(sc, HIFN_1_7811_RNGDAT);
808	}
809	} else
810	buf[rc++] = READ_REG_1(sc, HIFN_1_RNG_DATA);
811
812	/* NB: discard first data read */
813	if (sc->sc_rngfirst) {
814	sc->sc_rngfirst = 0;
815	rc = 0;
816	}
817
818	return(rc);
819	}
820	#endif /* CONFIG_OCF_RANDOMHARVEST */
821
822	static void
823	hifn_puc_wait(struct hifn_softc *sc)
824	{
825	int i;
826	int reg = HIFN_0_PUCTRL;
827
828	if (sc->sc_flags & HIFN_IS_7956) {
829	reg = HIFN_0_PUCTRL2;
830	}
831
832	for (i = 5000; i > 0; i--) {
833	DELAY(1);
834	if (!(READ_REG_0(sc, reg) & HIFN_PUCTRL_RESET))
835	break;
836	}
837	if (!i)
838	device_printf(sc->sc_dev, "proc unit did not reset(0x%x)\n",
839	READ_REG_0(sc, HIFN_0_PUCTRL));
840	}
841
842	/*
843	* Reset the processing unit.
844	*/
845	static void
846	hifn_reset_puc(struct hifn_softc *sc)
847	{
848	/* Reset processing unit */
849	int reg = HIFN_0_PUCTRL;
850
851	if (sc->sc_flags & HIFN_IS_7956) {
852	reg = HIFN_0_PUCTRL2;
853	}
854	WRITE_REG_0(sc, reg, HIFN_PUCTRL_DMAENA);
855
856	hifn_puc_wait(sc);
857	}
858
859	/*
860	* Set the Retry and TRDY registers; note that we set them to
861	* zero because the 7811 locks up when forced to retry (section
862	* 3.6 of "Specification Update SU-0014-04". Not clear if we
863	* should do this for all Hifn parts, but it doesn't seem to hurt.
864	*/
865	static void
866	hifn_set_retry(struct hifn_softc *sc)
867	{
868	DPRINTF("%s()\n", __FUNCTION__);
869	/* NB: RETRY only responds to 8-bit reads/writes */
870	pci_write_config_byte(sc->sc_pcidev, HIFN_RETRY_TIMEOUT, 0);
871	pci_write_config_byte(sc->sc_pcidev, HIFN_TRDY_TIMEOUT, 0);
872	/* piggy back the cache line setting here */
873	pci_write_config_byte(sc->sc_pcidev, PCI_CACHE_LINE_SIZE, hifn_cache_linesize);
874	}
875
876	/*
877	* Resets the board. Values in the regesters are left as is
878	* from the reset (i.e. initial values are assigned elsewhere).
879	*/
880	static void
881	hifn_reset_board(struct hifn_softc *sc, int full)
882	{
883	u_int32_t reg;
884
885	DPRINTF("%s()\n", __FUNCTION__);
886	/*
887	* Set polling in the DMA configuration register to zero. 0x7 avoids
888	* resetting the board and zeros out the other fields.
889	*/
890	WRITE_REG_1(sc, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MSTRESET \|
891	HIFN_DMACNFG_DMARESET \| HIFN_DMACNFG_MODE);
892
893	/*
894	* Now that polling has been disabled, we have to wait 1 ms
895	* before resetting the board.
896	*/
897	DELAY(1000);
898
899	/* Reset the DMA unit */
900	if (full) {
901	WRITE_REG_1(sc, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MODE);
902	DELAY(1000);
903	} else {
904	WRITE_REG_1(sc, HIFN_1_DMA_CNFG,
905	HIFN_DMACNFG_MODE \| HIFN_DMACNFG_MSTRESET);
906	hifn_reset_puc(sc);
907	}
908
909	KASSERT(sc->sc_dma != NULL, ("hifn_reset_board: null DMA tag!"));
910	bzero(sc->sc_dma, sizeof(*sc->sc_dma));
911
912	/* Bring dma unit out of reset */
913	WRITE_REG_1(sc, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MSTRESET \|
914	HIFN_DMACNFG_DMARESET \| HIFN_DMACNFG_MODE);
915
916	hifn_puc_wait(sc);
917	hifn_set_retry(sc);
918
919	if (sc->sc_flags & HIFN_IS_7811) {
920	for (reg = 0; reg < 1000; reg++) {
921	if (READ_REG_1(sc, HIFN_1_7811_MIPSRST) &
922	HIFN_MIPSRST_CRAMINIT)
923	break;
924	DELAY(1000);
925	}
926	if (reg == 1000)
927	device_printf(sc->sc_dev, ": cram init timeout\n");
928	} else {
929	/* set up DMA configuration register #2 */
930	/* turn off all PK and BAR0 swaps */
931	WRITE_REG_1(sc, HIFN_1_DMA_CNFG2,
932	(3 << HIFN_DMACNFG2_INIT_WRITE_BURST_SHIFT)\|
933	(3 << HIFN_DMACNFG2_INIT_READ_BURST_SHIFT)\|
934	(2 << HIFN_DMACNFG2_TGT_WRITE_BURST_SHIFT)\|
935	(2 << HIFN_DMACNFG2_TGT_READ_BURST_SHIFT));
936	}
937	}
938
939	static u_int32_t
940	hifn_next_signature(u_int32_t a, u_int cnt)
941	{
942	int i;
943	u_int32_t v;
944
945	for (i = 0; i < cnt; i++) {
946
947	/* get the parity */
948	v = a & 0x80080125;
949	v ^= v >> 16;
950	v ^= v >> 8;
951	v ^= v >> 4;
952	v ^= v >> 2;
953	v ^= v >> 1;
954
955	a = (v & 1) ^ (a << 1);
956	}
957
958	return a;
959	}
960
961
962	/*
963	* Checks to see if crypto is already enabled. If crypto isn't enable,
964	* "hifn_enable_crypto" is called to enable it. The check is important,
965	* as enabling crypto twice will lock the board.
966	*/
967	static int
968	hifn_enable_crypto(struct hifn_softc *sc)
969	{
970	u_int32_t dmacfg, ramcfg, encl, addr, i;
971	char offtbl[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
972	0x00, 0x00, 0x00, 0x00 };
973
974	DPRINTF("%s()\n", __FUNCTION__);
975
976	ramcfg = READ_REG_0(sc, HIFN_0_PUCNFG);
977	dmacfg = READ_REG_1(sc, HIFN_1_DMA_CNFG);
978
979	/*
980	* The RAM config register's encrypt level bit needs to be set before
981	* every read performed on the encryption level register.
982	*/
983	WRITE_REG_0(sc, HIFN_0_PUCNFG, ramcfg \| HIFN_PUCNFG_CHIPID);
984
985	encl = READ_REG_0(sc, HIFN_0_PUSTAT) & HIFN_PUSTAT_CHIPENA;
986
987	/*
988	* Make sure we don't re-unlock. Two unlocks kills chip until the
989	* next reboot.
990	*/
991	if (encl == HIFN_PUSTAT_ENA_1 \|\| encl == HIFN_PUSTAT_ENA_2) {
992	#ifdef HIFN_DEBUG
993	if (hifn_debug)
994	device_printf(sc->sc_dev,
995	"Strong crypto already enabled!\n");
996	#endif
997	goto report;
998	}
999
1000	if (encl != 0 && encl != HIFN_PUSTAT_ENA_0) {
1001	#ifdef HIFN_DEBUG
1002	if (hifn_debug)
1003	device_printf(sc->sc_dev,
1004	"Unknown encryption level 0x%x\n", encl);
1005	#endif
1006	return 1;
1007	}
1008
1009	WRITE_REG_1(sc, HIFN_1_DMA_CNFG, HIFN_DMACNFG_UNLOCK \|
1010	HIFN_DMACNFG_MSTRESET \| HIFN_DMACNFG_DMARESET \| HIFN_DMACNFG_MODE);
1011	DELAY(1000);
1012	addr = READ_REG_1(sc, HIFN_UNLOCK_SECRET1);
1013	DELAY(1000);
1014	WRITE_REG_1(sc, HIFN_UNLOCK_SECRET2, 0);
1015	DELAY(1000);
1016
1017	for (i = 0; i <= 12; i++) {
1018	addr = hifn_next_signature(addr, offtbl[i] + 0x101);
1019	WRITE_REG_1(sc, HIFN_UNLOCK_SECRET2, addr);
1020
1021	DELAY(1000);
1022	}
1023
1024	WRITE_REG_0(sc, HIFN_0_PUCNFG, ramcfg \| HIFN_PUCNFG_CHIPID);
1025	encl = READ_REG_0(sc, HIFN_0_PUSTAT) & HIFN_PUSTAT_CHIPENA;
1026
1027	#ifdef HIFN_DEBUG
1028	if (hifn_debug) {
1029	if (encl != HIFN_PUSTAT_ENA_1 && encl != HIFN_PUSTAT_ENA_2)
1030	device_printf(sc->sc_dev, "Engine is permanently "
1031	"locked until next system reset!\n");
1032	else
1033	device_printf(sc->sc_dev, "Engine enabled "
1034	"successfully!\n");
1035	}
1036	#endif
1037
1038	report:
1039	WRITE_REG_0(sc, HIFN_0_PUCNFG, ramcfg);
1040	WRITE_REG_1(sc, HIFN_1_DMA_CNFG, dmacfg);
1041
1042	switch (encl) {
1043	case HIFN_PUSTAT_ENA_1:
1044	case HIFN_PUSTAT_ENA_2:
1045	break;
1046	case HIFN_PUSTAT_ENA_0:
1047	default:
1048	device_printf(sc->sc_dev, "disabled\n");
1049	break;
1050	}
1051
1052	return 0;
1053	}
1054
1055	/*
1056	* Give initial values to the registers listed in the "Register Space"
1057	* section of the HIFN Software Development reference manual.
1058	*/
1059	static void
1060	hifn_init_pci_registers(struct hifn_softc *sc)
1061	{
1062	DPRINTF("%s()\n", __FUNCTION__);
1063
1064	/* write fixed values needed by the Initialization registers */
1065	WRITE_REG_0(sc, HIFN_0_PUCTRL, HIFN_PUCTRL_DMAENA);
1066	WRITE_REG_0(sc, HIFN_0_FIFOCNFG, HIFN_FIFOCNFG_THRESHOLD);
1067	WRITE_REG_0(sc, HIFN_0_PUIER, HIFN_PUIER_DSTOVER);
1068
1069	/* write all 4 ring address registers */
1070	WRITE_REG_1(sc, HIFN_1_DMA_CRAR, sc->sc_dma_physaddr +
1071	offsetof(struct hifn_dma, cmdr[0]));
1072	WRITE_REG_1(sc, HIFN_1_DMA_SRAR, sc->sc_dma_physaddr +
1073	offsetof(struct hifn_dma, srcr[0]));
1074	WRITE_REG_1(sc, HIFN_1_DMA_DRAR, sc->sc_dma_physaddr +
1075	offsetof(struct hifn_dma, dstr[0]));
1076	WRITE_REG_1(sc, HIFN_1_DMA_RRAR, sc->sc_dma_physaddr +
1077	offsetof(struct hifn_dma, resr[0]));
1078
1079	DELAY(2000);
1080
1081	/* write status register */
1082	WRITE_REG_1(sc, HIFN_1_DMA_CSR,
1083	HIFN_DMACSR_D_CTRL_DIS \| HIFN_DMACSR_R_CTRL_DIS \|
1084	HIFN_DMACSR_S_CTRL_DIS \| HIFN_DMACSR_C_CTRL_DIS \|
1085	HIFN_DMACSR_D_ABORT \| HIFN_DMACSR_D_DONE \| HIFN_DMACSR_D_LAST \|
1086	HIFN_DMACSR_D_WAIT \| HIFN_DMACSR_D_OVER \|
1087	HIFN_DMACSR_R_ABORT \| HIFN_DMACSR_R_DONE \| HIFN_DMACSR_R_LAST \|
1088	HIFN_DMACSR_R_WAIT \| HIFN_DMACSR_R_OVER \|
1089	HIFN_DMACSR_S_ABORT \| HIFN_DMACSR_S_DONE \| HIFN_DMACSR_S_LAST \|
1090	HIFN_DMACSR_S_WAIT \|
1091	HIFN_DMACSR_C_ABORT \| HIFN_DMACSR_C_DONE \| HIFN_DMACSR_C_LAST \|
1092	HIFN_DMACSR_C_WAIT \|
1093	HIFN_DMACSR_ENGINE \|
1094	((sc->sc_flags & HIFN_HAS_PUBLIC) ?
1095	HIFN_DMACSR_PUBDONE : 0) \|
1096	((sc->sc_flags & HIFN_IS_7811) ?
1097	HIFN_DMACSR_ILLW \| HIFN_DMACSR_ILLR : 0));
1098
1099	sc->sc_d_busy = sc->sc_r_busy = sc->sc_s_busy = sc->sc_c_busy = 0;
1100	sc->sc_dmaier \|= HIFN_DMAIER_R_DONE \| HIFN_DMAIER_C_ABORT \|
1101	HIFN_DMAIER_D_OVER \| HIFN_DMAIER_R_OVER \|
1102	HIFN_DMAIER_S_ABORT \| HIFN_DMAIER_D_ABORT \| HIFN_DMAIER_R_ABORT \|
1103	((sc->sc_flags & HIFN_IS_7811) ?
1104	HIFN_DMAIER_ILLW \| HIFN_DMAIER_ILLR : 0);
1105	sc->sc_dmaier &= ~HIFN_DMAIER_C_WAIT;
1106	WRITE_REG_1(sc, HIFN_1_DMA_IER, sc->sc_dmaier);
1107
1108
1109	if (sc->sc_flags & HIFN_IS_7956) {
1110	u_int32_t pll;
1111
1112	WRITE_REG_0(sc, HIFN_0_PUCNFG, HIFN_PUCNFG_COMPSING \|
1113	HIFN_PUCNFG_TCALLPHASES \|
1114	HIFN_PUCNFG_TCDRVTOTEM \| HIFN_PUCNFG_BUS32);
1115
1116	/* turn off the clocks and insure bypass is set */
1117	pll = READ_REG_1(sc, HIFN_1_PLL);
1118	pll = (pll &~ (HIFN_PLL_PK_CLK_SEL \| HIFN_PLL_PE_CLK_SEL))
1119	\| HIFN_PLL_BP \| HIFN_PLL_MBSET;
1120	WRITE_REG_1(sc, HIFN_1_PLL, pll);
1121	DELAY(101000); / 10ms */
1122
1123	/* change configuration */
1124	pll = (pll &~ HIFN_PLL_CONFIG) \| sc->sc_pllconfig;
1125	WRITE_REG_1(sc, HIFN_1_PLL, pll);
1126	DELAY(101000); / 10ms */
1127
1128	/* disable bypass */
1129	pll &= ~HIFN_PLL_BP;
1130	WRITE_REG_1(sc, HIFN_1_PLL, pll);
1131	/* enable clocks with new configuration */
1132	pll \|= HIFN_PLL_PK_CLK_SEL \| HIFN_PLL_PE_CLK_SEL;
1133	WRITE_REG_1(sc, HIFN_1_PLL, pll);
1134	} else {
1135	WRITE_REG_0(sc, HIFN_0_PUCNFG, HIFN_PUCNFG_COMPSING \|
1136	HIFN_PUCNFG_DRFR_128 \| HIFN_PUCNFG_TCALLPHASES \|
1137	HIFN_PUCNFG_TCDRVTOTEM \| HIFN_PUCNFG_BUS32 \|
1138	(sc->sc_drammodel ? HIFN_PUCNFG_DRAM : HIFN_PUCNFG_SRAM));
1139	}
1140
1141	WRITE_REG_0(sc, HIFN_0_PUISR, HIFN_PUISR_DSTOVER);
1142	WRITE_REG_1(sc, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MSTRESET \|
1143	HIFN_DMACNFG_DMARESET \| HIFN_DMACNFG_MODE \| HIFN_DMACNFG_LAST \|
1144	((HIFN_POLL_FREQUENCY << 16 ) & HIFN_DMACNFG_POLLFREQ) \|
1145	((HIFN_POLL_SCALAR << 8) & HIFN_DMACNFG_POLLINVAL));
1146	}
1147
1148	/*
1149	* The maximum number of sessions supported by the card
1150	* is dependent on the amount of context ram, which
1151	* encryption algorithms are enabled, and how compression
1152	* is configured. This should be configured before this
1153	* routine is called.
1154	*/
1155	static void
1156	hifn_sessions(struct hifn_softc *sc)
1157	{
1158	u_int32_t pucnfg;
1159	int ctxsize;
1160
1161	DPRINTF("%s()\n", __FUNCTION__);
1162
1163	pucnfg = READ_REG_0(sc, HIFN_0_PUCNFG);
1164
1165	if (pucnfg & HIFN_PUCNFG_COMPSING) {
1166	if (pucnfg & HIFN_PUCNFG_ENCCNFG)
1167	ctxsize = 128;
1168	else
1169	ctxsize = 512;
1170	/*
1171	* 7955/7956 has internal context memory of 32K
1172	*/
1173	if (sc->sc_flags & HIFN_IS_7956)
1174	sc->sc_maxses = 32768 / ctxsize;
1175	else
1176	sc->sc_maxses = 1 +
1177	((sc->sc_ramsize - 32768) / ctxsize);
1178	} else
1179	sc->sc_maxses = sc->sc_ramsize / 16384;
1180
1181	if (sc->sc_maxses > 2048)
1182	sc->sc_maxses = 2048;
1183	}
1184
1185	/*
1186	* Determine ram type (sram or dram). Board should be just out of a reset
1187	* state when this is called.
1188	*/
1189	static int
1190	hifn_ramtype(struct hifn_softc *sc)
1191	{
1192	u_int8_t data[8], dataexpect[8];
1193	int i;
1194
1195	for (i = 0; i < sizeof(data); i++)
1196	data[i] = dataexpect[i] = 0x55;
1197	if (hifn_writeramaddr(sc, 0, data))
1198	return (-1);
1199	if (hifn_readramaddr(sc, 0, data))
1200	return (-1);
1201	if (bcmp(data, dataexpect, sizeof(data)) != 0) {
1202	sc->sc_drammodel = 1;
1203	return (0);
1204	}
1205
1206	for (i = 0; i < sizeof(data); i++)
1207	data[i] = dataexpect[i] = 0xaa;
1208	if (hifn_writeramaddr(sc, 0, data))
1209	return (-1);
1210	if (hifn_readramaddr(sc, 0, data))
1211	return (-1);
1212	if (bcmp(data, dataexpect, sizeof(data)) != 0) {
1213	sc->sc_drammodel = 1;
1214	return (0);
1215	}
1216
1217	return (0);
1218	}
1219
1220	#define HIFN_SRAM_MAX (32 << 20)
1221	#define HIFN_SRAM_STEP_SIZE 16384
1222	#define HIFN_SRAM_GRANULARITY (HIFN_SRAM_MAX / HIFN_SRAM_STEP_SIZE)
1223
1224	static int
1225	hifn_sramsize(struct hifn_softc *sc)
1226	{
1227	u_int32_t a;
1228	u_int8_t data[8];
1229	u_int8_t dataexpect[sizeof(data)];
1230	int32_t i;
1231
1232	for (i = 0; i < sizeof(data); i++)
1233	data[i] = dataexpect[i] = i ^ 0x5a;
1234
1235	for (i = HIFN_SRAM_GRANULARITY - 1; i >= 0; i--) {
1236	a = i * HIFN_SRAM_STEP_SIZE;
1237	bcopy(&i, data, sizeof(i));
1238	hifn_writeramaddr(sc, a, data);
1239	}
1240
1241	for (i = 0; i < HIFN_SRAM_GRANULARITY; i++) {
1242	a = i * HIFN_SRAM_STEP_SIZE;
1243	bcopy(&i, dataexpect, sizeof(i));
1244	if (hifn_readramaddr(sc, a, data) < 0)
1245	return (0);
1246	if (bcmp(data, dataexpect, sizeof(data)) != 0)
1247	return (0);
1248	sc->sc_ramsize = a + HIFN_SRAM_STEP_SIZE;
1249	}
1250
1251	return (0);
1252	}
1253
1254	/*
1255	* XXX For dram boards, one should really try all of the
1256	* HIFN_PUCNFG_DSZ_*'s. This just assumes that PUCNFG
1257	* is already set up correctly.
1258	*/
1259	static int
1260	hifn_dramsize(struct hifn_softc *sc)
1261	{
1262	u_int32_t cnfg;
1263
1264	if (sc->sc_flags & HIFN_IS_7956) {
1265	/*
1266	* 7955/7956 have a fixed internal ram of only 32K.
1267	*/
1268	sc->sc_ramsize = 32768;
1269	} else {
1270	cnfg = READ_REG_0(sc, HIFN_0_PUCNFG) &
1271	HIFN_PUCNFG_DRAMMASK;
1272	sc->sc_ramsize = 1 << ((cnfg >> 13) + 18);
1273	}
1274	return (0);
1275	}
1276
1277	static void
1278	hifn_alloc_slot(struct hifn_softc sc, int cmdp, int srcp, int dstp, int *resp)
1279	{
1280	struct hifn_dma *dma = sc->sc_dma;
1281
1282	DPRINTF("%s()\n", __FUNCTION__);
1283
1284	if (dma->cmdi == HIFN_D_CMD_RSIZE) {
1285	dma->cmdi = 0;
1286	dma->cmdr[HIFN_D_CMD_RSIZE].l = htole32(HIFN_D_JUMP\|HIFN_D_MASKDONEIRQ);
1287	wmb();
1288	dma->cmdr[HIFN_D_CMD_RSIZE].l \|= htole32(HIFN_D_VALID);
1289	HIFN_CMDR_SYNC(sc, HIFN_D_CMD_RSIZE,
1290	BUS_DMASYNC_PREWRITE \| BUS_DMASYNC_PREREAD);
1291	}
1292	*cmdp = dma->cmdi++;
1293	dma->cmdk = dma->cmdi;
1294
1295	if (dma->srci == HIFN_D_SRC_RSIZE) {
1296	dma->srci = 0;
1297	dma->srcr[HIFN_D_SRC_RSIZE].l = htole32(HIFN_D_JUMP\|HIFN_D_MASKDONEIRQ);
1298	wmb();
1299	dma->srcr[HIFN_D_SRC_RSIZE].l \|= htole32(HIFN_D_VALID);
1300	HIFN_SRCR_SYNC(sc, HIFN_D_SRC_RSIZE,
1301	BUS_DMASYNC_PREWRITE \| BUS_DMASYNC_PREREAD);
1302	}
1303	*srcp = dma->srci++;
1304	dma->srck = dma->srci;
1305
1306	if (dma->dsti == HIFN_D_DST_RSIZE) {
1307	dma->dsti = 0;
1308	dma->dstr[HIFN_D_DST_RSIZE].l = htole32(HIFN_D_JUMP\|HIFN_D_MASKDONEIRQ);
1309	wmb();
1310	dma->dstr[HIFN_D_DST_RSIZE].l \|= htole32(HIFN_D_VALID);
1311	HIFN_DSTR_SYNC(sc, HIFN_D_DST_RSIZE,
1312	BUS_DMASYNC_PREWRITE \| BUS_DMASYNC_PREREAD);
1313	}
1314	*dstp = dma->dsti++;
1315	dma->dstk = dma->dsti;
1316
1317	if (dma->resi == HIFN_D_RES_RSIZE) {
1318	dma->resi = 0;
1319	dma->resr[HIFN_D_RES_RSIZE].l = htole32(HIFN_D_JUMP\|HIFN_D_MASKDONEIRQ);
1320	wmb();
1321	dma->resr[HIFN_D_RES_RSIZE].l \|= htole32(HIFN_D_VALID);
1322	HIFN_RESR_SYNC(sc, HIFN_D_RES_RSIZE,
1323	BUS_DMASYNC_PREWRITE \| BUS_DMASYNC_PREREAD);
1324	}
1325	*resp = dma->resi++;
1326	dma->resk = dma->resi;
1327	}
1328
1329	static int
1330	hifn_writeramaddr(struct hifn_softc sc, int addr, u_int8_t data)
1331	{
1332	struct hifn_dma *dma = sc->sc_dma;
1333	hifn_base_command_t wc;
1334	const u_int32_t masks = HIFN_D_VALID \| HIFN_D_LAST \| HIFN_D_MASKDONEIRQ;
1335	int r, cmdi, resi, srci, dsti;
1336
1337	DPRINTF("%s()\n", __FUNCTION__);
1338
1339	wc.masks = htole16(3 << 13);
1340	wc.session_num = htole16(addr >> 14);
1341	wc.total_source_count = htole16(8);
1342	wc.total_dest_count = htole16(addr & 0x3fff);
1343
1344	hifn_alloc_slot(sc, &cmdi, &srci, &dsti, &resi);
1345
1346	WRITE_REG_1(sc, HIFN_1_DMA_CSR,
1347	HIFN_DMACSR_C_CTRL_ENA \| HIFN_DMACSR_S_CTRL_ENA \|
1348	HIFN_DMACSR_D_CTRL_ENA \| HIFN_DMACSR_R_CTRL_ENA);
1349
1350	/* build write command */
1351	bzero(dma->command_bufs[cmdi], HIFN_MAX_COMMAND);
1352	(hifn_base_command_t )dma->command_bufs[cmdi] = wc;
1353	bcopy(data, &dma->test_src, sizeof(dma->test_src));
1354
1355	dma->srcr[srci].p = htole32(sc->sc_dma_physaddr
1356	+ offsetof(struct hifn_dma, test_src));
1357	dma->dstr[dsti].p = htole32(sc->sc_dma_physaddr
1358	+ offsetof(struct hifn_dma, test_dst));
1359
1360	dma->cmdr[cmdi].l = htole32(16 \| masks);
1361	dma->srcr[srci].l = htole32(8 \| masks);
1362	dma->dstr[dsti].l = htole32(4 \| masks);
1363	dma->resr[resi].l = htole32(4 \| masks);
1364
1365	for (r = 10000; r >= 0; r--) {
1366	DELAY(10);
1367	if ((dma->resr[resi].l & htole32(HIFN_D_VALID)) == 0)
1368	break;
1369	}
1370	if (r == 0) {
1371	device_printf(sc->sc_dev, "writeramaddr -- "
1372	"result[%d](addr %d) still valid\n", resi, addr);
1373	r = -1;
1374	return (-1);
1375	} else
1376	r = 0;
1377
1378	WRITE_REG_1(sc, HIFN_1_DMA_CSR,
1379	HIFN_DMACSR_C_CTRL_DIS \| HIFN_DMACSR_S_CTRL_DIS \|
1380	HIFN_DMACSR_D_CTRL_DIS \| HIFN_DMACSR_R_CTRL_DIS);
1381
1382	return (r);
1383	}
1384
1385	static int
1386	hifn_readramaddr(struct hifn_softc sc, int addr, u_int8_t data)
1387	{
1388	struct hifn_dma *dma = sc->sc_dma;
1389	hifn_base_command_t rc;
1390	const u_int32_t masks = HIFN_D_VALID \| HIFN_D_LAST \| HIFN_D_MASKDONEIRQ;
1391	int r, cmdi, srci, dsti, resi;
1392
1393	DPRINTF("%s()\n", __FUNCTION__);
1394
1395	rc.masks = htole16(2 << 13);
1396	rc.session_num = htole16(addr >> 14);
1397	rc.total_source_count = htole16(addr & 0x3fff);
1398	rc.total_dest_count = htole16(8);
1399
1400	hifn_alloc_slot(sc, &cmdi, &srci, &dsti, &resi);
1401
1402	WRITE_REG_1(sc, HIFN_1_DMA_CSR,
1403	HIFN_DMACSR_C_CTRL_ENA \| HIFN_DMACSR_S_CTRL_ENA \|
1404	HIFN_DMACSR_D_CTRL_ENA \| HIFN_DMACSR_R_CTRL_ENA);
1405
1406	bzero(dma->command_bufs[cmdi], HIFN_MAX_COMMAND);
1407	(hifn_base_command_t )dma->command_bufs[cmdi] = rc;
1408
1409	dma->srcr[srci].p = htole32(sc->sc_dma_physaddr +
1410	offsetof(struct hifn_dma, test_src));
1411	dma->test_src = 0;
1412	dma->dstr[dsti].p = htole32(sc->sc_dma_physaddr +
1413	offsetof(struct hifn_dma, test_dst));
1414	dma->test_dst = 0;
1415	dma->cmdr[cmdi].l = htole32(8 \| masks);
1416	dma->srcr[srci].l = htole32(8 \| masks);
1417	dma->dstr[dsti].l = htole32(8 \| masks);
1418	dma->resr[resi].l = htole32(HIFN_MAX_RESULT \| masks);
1419
1420	for (r = 10000; r >= 0; r--) {
1421	DELAY(10);
1422	if ((dma->resr[resi].l & htole32(HIFN_D_VALID)) == 0)
1423	break;
1424	}
1425	if (r == 0) {
1426	device_printf(sc->sc_dev, "readramaddr -- "
1427	"result[%d](addr %d) still valid\n", resi, addr);
1428	r = -1;
1429	} else {
1430	r = 0;
1431	bcopy(&dma->test_dst, data, sizeof(dma->test_dst));
1432	}
1433
1434	WRITE_REG_1(sc, HIFN_1_DMA_CSR,
1435	HIFN_DMACSR_C_CTRL_DIS \| HIFN_DMACSR_S_CTRL_DIS \|
1436	HIFN_DMACSR_D_CTRL_DIS \| HIFN_DMACSR_R_CTRL_DIS);
1437
1438	return (r);
1439	}
1440
1441	/*
1442	* Initialize the descriptor rings.
1443	*/
1444	static void
1445	hifn_init_dma(struct hifn_softc *sc)
1446	{
1447	struct hifn_dma *dma = sc->sc_dma;
1448	int i;
1449
1450	DPRINTF("%s()\n", __FUNCTION__);
1451
1452	hifn_set_retry(sc);
1453
1454	/* initialize static pointer values */
1455	for (i = 0; i < HIFN_D_CMD_RSIZE; i++)
1456	dma->cmdr[i].p = htole32(sc->sc_dma_physaddr +
1457	offsetof(struct hifn_dma, command_bufs[i][0]));
1458	for (i = 0; i < HIFN_D_RES_RSIZE; i++)
1459	dma->resr[i].p = htole32(sc->sc_dma_physaddr +
1460	offsetof(struct hifn_dma, result_bufs[i][0]));
1461
1462	dma->cmdr[HIFN_D_CMD_RSIZE].p =
1463	htole32(sc->sc_dma_physaddr + offsetof(struct hifn_dma, cmdr[0]));
1464	dma->srcr[HIFN_D_SRC_RSIZE].p =
1465	htole32(sc->sc_dma_physaddr + offsetof(struct hifn_dma, srcr[0]));
1466	dma->dstr[HIFN_D_DST_RSIZE].p =
1467	htole32(sc->sc_dma_physaddr + offsetof(struct hifn_dma, dstr[0]));
1468	dma->resr[HIFN_D_RES_RSIZE].p =
1469	htole32(sc->sc_dma_physaddr + offsetof(struct hifn_dma, resr[0]));
1470
1471	dma->cmdu = dma->srcu = dma->dstu = dma->resu = 0;
1472	dma->cmdi = dma->srci = dma->dsti = dma->resi = 0;
1473	dma->cmdk = dma->srck = dma->dstk = dma->resk = 0;
1474	}
1475
1476	/*
1477	* Writes out the raw command buffer space. Returns the
1478	* command buffer size.
1479	*/
1480	static u_int
1481	hifn_write_command(struct hifn_command cmd, u_int8_t buf)
1482	{
1483	struct hifn_softc *sc = NULL;
1484	u_int8_t *buf_pos;
1485	hifn_base_command_t *base_cmd;
1486	hifn_mac_command_t *mac_cmd;
1487	hifn_crypt_command_t *cry_cmd;
1488	int using_mac, using_crypt, len, ivlen;
1489	u_int32_t dlen, slen;
1490
1491	DPRINTF("%s()\n", __FUNCTION__);
1492
1493	buf_pos = buf;
1494	using_mac = cmd->base_masks & HIFN_BASE_CMD_MAC;
1495	using_crypt = cmd->base_masks & HIFN_BASE_CMD_CRYPT;
1496
1497	base_cmd = (hifn_base_command_t *)buf_pos;
1498	base_cmd->masks = htole16(cmd->base_masks);
1499	slen = cmd->src_mapsize;
1500	if (cmd->sloplen)
1501	dlen = cmd->dst_mapsize - cmd->sloplen + sizeof(u_int32_t);
1502	else
1503	dlen = cmd->dst_mapsize;
1504	base_cmd->total_source_count = htole16(slen & HIFN_BASE_CMD_LENMASK_LO);
1505	base_cmd->total_dest_count = htole16(dlen & HIFN_BASE_CMD_LENMASK_LO);
1506	dlen >>= 16;
1507	slen >>= 16;
1508	base_cmd->session_num = htole16(
1509	((slen << HIFN_BASE_CMD_SRCLEN_S) & HIFN_BASE_CMD_SRCLEN_M) \|
1510	((dlen << HIFN_BASE_CMD_DSTLEN_S) & HIFN_BASE_CMD_DSTLEN_M));
1511	buf_pos += sizeof(hifn_base_command_t);
1512
1513	if (using_mac) {
1514	mac_cmd = (hifn_mac_command_t *)buf_pos;
1515	dlen = cmd->maccrd->crd_len;
1516	mac_cmd->source_count = htole16(dlen & 0xffff);
1517	dlen >>= 16;
1518	mac_cmd->masks = htole16(cmd->mac_masks \|
1519	((dlen << HIFN_MAC_CMD_SRCLEN_S) & HIFN_MAC_CMD_SRCLEN_M));
1520	mac_cmd->header_skip = htole16(cmd->maccrd->crd_skip);
1521	mac_cmd->reserved = 0;
1522	buf_pos += sizeof(hifn_mac_command_t);
1523	}
1524
1525	if (using_crypt) {
1526	cry_cmd = (hifn_crypt_command_t *)buf_pos;
1527	dlen = cmd->enccrd->crd_len;
1528	cry_cmd->source_count = htole16(dlen & 0xffff);
1529	dlen >>= 16;
1530	cry_cmd->masks = htole16(cmd->cry_masks \|
1531	((dlen << HIFN_CRYPT_CMD_SRCLEN_S) & HIFN_CRYPT_CMD_SRCLEN_M));
1532	cry_cmd->header_skip = htole16(cmd->enccrd->crd_skip);
1533	cry_cmd->reserved = 0;
1534	buf_pos += sizeof(hifn_crypt_command_t);
1535	}
1536
1537	if (using_mac && cmd->mac_masks & HIFN_MAC_CMD_NEW_KEY) {
1538	bcopy(cmd->mac, buf_pos, HIFN_MAC_KEY_LENGTH);
1539	buf_pos += HIFN_MAC_KEY_LENGTH;
1540	}
1541
1542	if (using_crypt && cmd->cry_masks & HIFN_CRYPT_CMD_NEW_KEY) {
1543	switch (cmd->cry_masks & HIFN_CRYPT_CMD_ALG_MASK) {
1544	case HIFN_CRYPT_CMD_ALG_3DES:
1545	bcopy(cmd->ck, buf_pos, HIFN_3DES_KEY_LENGTH);
1546	buf_pos += HIFN_3DES_KEY_LENGTH;
1547	break;
1548	case HIFN_CRYPT_CMD_ALG_DES:
1549	bcopy(cmd->ck, buf_pos, HIFN_DES_KEY_LENGTH);
1550	buf_pos += HIFN_DES_KEY_LENGTH;
1551	break;
1552	case HIFN_CRYPT_CMD_ALG_RC4:
1553	len = 256;
1554	do {
1555	int clen;
1556
1557	clen = MIN(cmd->cklen, len);
1558	bcopy(cmd->ck, buf_pos, clen);
1559	len -= clen;
1560	buf_pos += clen;
1561	} while (len > 0);
1562	bzero(buf_pos, 4);
1563	buf_pos += 4;
1564	break;
1565	case HIFN_CRYPT_CMD_ALG_AES:
1566	/*
1567	* AES keys are variable 128, 192 and
1568	* 256 bits (16, 24 and 32 bytes).
1569	*/
1570	bcopy(cmd->ck, buf_pos, cmd->cklen);
1571	buf_pos += cmd->cklen;
1572	break;
1573	}
1574	}
1575
1576	if (using_crypt && cmd->cry_masks & HIFN_CRYPT_CMD_NEW_IV) {
1577	switch (cmd->cry_masks & HIFN_CRYPT_CMD_ALG_MASK) {
1578	case HIFN_CRYPT_CMD_ALG_AES:
1579	ivlen = HIFN_AES_IV_LENGTH;
1580	break;
1581	default:
1582	ivlen = HIFN_IV_LENGTH;
1583	break;
1584	}
1585	bcopy(cmd->iv, buf_pos, ivlen);
1586	buf_pos += ivlen;
1587	}
1588
1589	if ((cmd->base_masks & (HIFN_BASE_CMD_MAC\|HIFN_BASE_CMD_CRYPT)) == 0) {
1590	bzero(buf_pos, 8);
1591	buf_pos += 8;
1592	}
1593
1594	return (buf_pos - buf);
1595	}
1596
1597	static int
1598	hifn_dmamap_aligned(struct hifn_operand *op)
1599	{
1600	struct hifn_softc *sc = NULL;
1601	int i;
1602
1603	DPRINTF("%s()\n", __FUNCTION__);
1604
1605	for (i = 0; i < op->nsegs; i++) {
1606	if (op->segs[i].ds_addr & 3)
1607	return (0);
1608	if ((i != (op->nsegs - 1)) && (op->segs[i].ds_len & 3))
1609	return (0);
1610	}
1611	return (1);
1612	}
1613
1614	static __inline int
1615	hifn_dmamap_dstwrap(struct hifn_softc *sc, int idx)
1616	{
1617	struct hifn_dma *dma = sc->sc_dma;
1618
1619	if (++idx == HIFN_D_DST_RSIZE) {
1620	dma->dstr[idx].l = htole32(HIFN_D_VALID \| HIFN_D_JUMP \|
1621	HIFN_D_MASKDONEIRQ);
1622	HIFN_DSTR_SYNC(sc, idx,
1623	BUS_DMASYNC_PREREAD \| BUS_DMASYNC_PREWRITE);
1624	idx = 0;
1625	}
1626	return (idx);
1627	}
1628
1629	static int
1630	hifn_dmamap_load_dst(struct hifn_softc sc, struct hifn_command cmd)
1631	{
1632	struct hifn_dma *dma = sc->sc_dma;
1633	struct hifn_operand *dst = &cmd->dst;
1634	u_int32_t p, l;
1635	int idx, used = 0, i;
1636
1637	DPRINTF("%s()\n", __FUNCTION__);
1638
1639	idx = dma->dsti;
1640	for (i = 0; i < dst->nsegs - 1; i++) {
1641	dma->dstr[idx].p = htole32(dst->segs[i].ds_addr);
1642	dma->dstr[idx].l = htole32(HIFN_D_MASKDONEIRQ \| dst->segs[i].ds_len);
1643	wmb();
1644	dma->dstr[idx].l \|= htole32(HIFN_D_VALID);
1645	HIFN_DSTR_SYNC(sc, idx,
1646	BUS_DMASYNC_PREREAD \| BUS_DMASYNC_PREWRITE);
1647	used++;
1648
1649	idx = hifn_dmamap_dstwrap(sc, idx);
1650	}
1651
1652	if (cmd->sloplen == 0) {
1653	p = dst->segs[i].ds_addr;
1654	l = HIFN_D_MASKDONEIRQ \| HIFN_D_LAST \|
1655	dst->segs[i].ds_len;
1656	} else {
1657	p = sc->sc_dma_physaddr +
1658	offsetof(struct hifn_dma, slop[cmd->slopidx]);
1659	l = HIFN_D_MASKDONEIRQ \| HIFN_D_LAST \|
1660	sizeof(u_int32_t);
1661
1662	if ((dst->segs[i].ds_len - cmd->sloplen) != 0) {
1663	dma->dstr[idx].p = htole32(dst->segs[i].ds_addr);
1664	dma->dstr[idx].l = htole32(HIFN_D_MASKDONEIRQ \|
1665	(dst->segs[i].ds_len - cmd->sloplen));
1666	wmb();
1667	dma->dstr[idx].l \|= htole32(HIFN_D_VALID);
1668	HIFN_DSTR_SYNC(sc, idx,
1669	BUS_DMASYNC_PREREAD \| BUS_DMASYNC_PREWRITE);
1670	used++;
1671
1672	idx = hifn_dmamap_dstwrap(sc, idx);
1673	}
1674	}
1675	dma->dstr[idx].p = htole32(p);
1676	dma->dstr[idx].l = htole32(l);
1677	wmb();
1678	dma->dstr[idx].l \|= htole32(HIFN_D_VALID);
1679	HIFN_DSTR_SYNC(sc, idx, BUS_DMASYNC_PREREAD \| BUS_DMASYNC_PREWRITE);
1680	used++;
1681
1682	idx = hifn_dmamap_dstwrap(sc, idx);
1683
1684	dma->dsti = idx;
1685	dma->dstu += used;
1686	return (idx);
1687	}
1688
1689	static __inline int
1690	hifn_dmamap_srcwrap(struct hifn_softc *sc, int idx)
1691	{
1692	struct hifn_dma *dma = sc->sc_dma;
1693
1694	if (++idx == HIFN_D_SRC_RSIZE) {
1695	dma->srcr[idx].l = htole32(HIFN_D_VALID \|
1696	HIFN_D_JUMP \| HIFN_D_MASKDONEIRQ);
1697	HIFN_SRCR_SYNC(sc, HIFN_D_SRC_RSIZE,
1698	BUS_DMASYNC_PREWRITE \| BUS_DMASYNC_PREREAD);
1699	idx = 0;
1700	}
1701	return (idx);
1702	}
1703
1704	static int
1705	hifn_dmamap_load_src(struct hifn_softc sc, struct hifn_command cmd)
1706	{
1707	struct hifn_dma *dma = sc->sc_dma;
1708	struct hifn_operand *src = &cmd->src;
1709	int idx, i;
1710	u_int32_t last = 0;
1711
1712	DPRINTF("%s()\n", __FUNCTION__);
1713
1714	idx = dma->srci;
1715	for (i = 0; i < src->nsegs; i++) {
1716	if (i == src->nsegs - 1)
1717	last = HIFN_D_LAST;
1718
1719	dma->srcr[idx].p = htole32(src->segs[i].ds_addr);
1720	dma->srcr[idx].l = htole32(src->segs[i].ds_len \|
1721	HIFN_D_MASKDONEIRQ \| last);
1722	wmb();
1723	dma->srcr[idx].l \|= htole32(HIFN_D_VALID);
1724	HIFN_SRCR_SYNC(sc, idx,
1725	BUS_DMASYNC_PREWRITE \| BUS_DMASYNC_PREREAD);
1726
1727	idx = hifn_dmamap_srcwrap(sc, idx);
1728	}
1729	dma->srci = idx;
1730	dma->srcu += src->nsegs;
1731	return (idx);
1732	}
1733
1734
1735	static int
1736	hifn_crypto(
1737	struct hifn_softc *sc,
1738	struct hifn_command *cmd,
1739	struct cryptop *crp,
1740	int hint)
1741	{
1742	struct hifn_dma *dma = sc->sc_dma;
1743	u_int32_t cmdlen, csr;
1744	int cmdi, resi, err = 0;
1745	unsigned long l_flags;
1746
1747	DPRINTF("%s()\n", __FUNCTION__);
1748
1749	/*
1750	* need 1 cmd, and 1 res
1751	*
1752	* NB: check this first since it's easy.
1753	*/
1754	HIFN_LOCK(sc);
1755	if ((dma->cmdu + 1) > HIFN_D_CMD_RSIZE \|\|
1756	(dma->resu + 1) > HIFN_D_RES_RSIZE) {
1757	#ifdef HIFN_DEBUG
1758	if (hifn_debug) {
1759	device_printf(sc->sc_dev,
1760	"cmd/result exhaustion, cmdu %u resu %u\n",
1761	dma->cmdu, dma->resu);
1762	}
1763	#endif
1764	hifnstats.hst_nomem_cr++;
1765	sc->sc_needwakeup \|= CRYPTO_SYMQ;
1766	HIFN_UNLOCK(sc);
1767	return (ERESTART);
1768	}
1769
1770	if (crp->crp_flags & CRYPTO_F_SKBUF) {
1771	if (pci_map_skb(sc, &cmd->src, cmd->src_skb)) {
1772	hifnstats.hst_nomem_load++;
1773	err = ENOMEM;
1774	goto err_srcmap1;
1775	}
1776	} else if (crp->crp_flags & CRYPTO_F_IOV) {
1777	if (pci_map_uio(sc, &cmd->src, cmd->src_io)) {
1778	hifnstats.hst_nomem_load++;
1779	err = ENOMEM;
1780	goto err_srcmap1;
1781	}
1782	} else {
1783	if (pci_map_buf(sc, &cmd->src, cmd->src_buf, crp->crp_ilen)) {
1784	hifnstats.hst_nomem_load++;
1785	err = ENOMEM;
1786	goto err_srcmap1;
1787	}
1788	}
1789
1790	if (hifn_dmamap_aligned(&cmd->src)) {
1791	cmd->sloplen = cmd->src_mapsize & 3;
1792	cmd->dst = cmd->src;
1793	} else {
1794	if (crp->crp_flags & CRYPTO_F_IOV) {
1795	DPRINTF("%s,%d: %s - EINVAL\n",__FILE__,__LINE__,__FUNCTION__);
1796	err = EINVAL;
1797	goto err_srcmap;
1798	} else if (crp->crp_flags & CRYPTO_F_SKBUF) {
1799	#ifdef NOTYET
1800	int totlen, len;
1801	struct mbuf m, m0, *mlast;
1802
1803	KASSERT(cmd->dst_m == cmd->src_m,
1804	("hifn_crypto: dst_m initialized improperly"));
1805	hifnstats.hst_unaligned++;
1806	/*
1807	* Source is not aligned on a longword boundary.
1808	* Copy the data to insure alignment. If we fail
1809	* to allocate mbufs or clusters while doing this
1810	* we return ERESTART so the operation is requeued
1811	* at the crypto later, but only if there are
1812	* ops already posted to the hardware; otherwise we
1813	* have no guarantee that we'll be re-entered.
1814	*/
1815	totlen = cmd->src_mapsize;
1816	if (cmd->src_m->m_flags & M_PKTHDR) {
1817	len = MHLEN;
1818	MGETHDR(m0, M_DONTWAIT, MT_DATA);
1819	if (m0 && !m_dup_pkthdr(m0, cmd->src_m, M_DONTWAIT)) {
1820	m_free(m0);
1821	m0 = NULL;
1822	}
1823	} else {
1824	len = MLEN;
1825	MGET(m0, M_DONTWAIT, MT_DATA);
1826	}
1827	if (m0 == NULL) {
1828	hifnstats.hst_nomem_mbuf++;
1829	err = dma->cmdu ? ERESTART : ENOMEM;
1830	goto err_srcmap;
1831	}
1832	if (totlen >= MINCLSIZE) {
1833	MCLGET(m0, M_DONTWAIT);
1834	if ((m0->m_flags & M_EXT) == 0) {
1835	hifnstats.hst_nomem_mcl++;
1836	err = dma->cmdu ? ERESTART : ENOMEM;
1837	m_freem(m0);
1838	goto err_srcmap;
1839	}
1840	len = MCLBYTES;
1841	}
1842	totlen -= len;
1843	m0->m_pkthdr.len = m0->m_len = len;
1844	mlast = m0;
1845
1846	while (totlen > 0) {
1847	MGET(m, M_DONTWAIT, MT_DATA);
1848	if (m == NULL) {
1849	hifnstats.hst_nomem_mbuf++;
1850	err = dma->cmdu ? ERESTART : ENOMEM;
1851	m_freem(m0);
1852	goto err_srcmap;
1853	}
1854	len = MLEN;
1855	if (totlen >= MINCLSIZE) {
1856	MCLGET(m, M_DONTWAIT);
1857	if ((m->m_flags & M_EXT) == 0) {
1858	hifnstats.hst_nomem_mcl++;
1859	err = dma->cmdu ? ERESTART : ENOMEM;
1860	mlast->m_next = m;
1861	m_freem(m0);
1862	goto err_srcmap;
1863	}
1864	len = MCLBYTES;
1865	}
1866
1867	m->m_len = len;
1868	m0->m_pkthdr.len += len;
1869	totlen -= len;
1870
1871	mlast->m_next = m;
1872	mlast = m;
1873	}
1874	cmd->dst_m = m0;
1875	#else
1876	device_printf(sc->sc_dev,
1877	"%s,%d: CRYPTO_F_SKBUF unaligned not implemented\n",
1878	__FILE__, __LINE__);
1879	err = EINVAL;
1880	goto err_srcmap;
1881	#endif
1882	} else {
1883	device_printf(sc->sc_dev,
1884	"%s,%d: unaligned contig buffers not implemented\n",
1885	__FILE__, __LINE__);
1886	err = EINVAL;
1887	goto err_srcmap;
1888	}
1889	}
1890
1891	if (cmd->dst_map == NULL) {
1892	if (crp->crp_flags & CRYPTO_F_SKBUF) {
1893	if (pci_map_skb(sc, &cmd->dst, cmd->dst_skb)) {
1894	hifnstats.hst_nomem_map++;
1895	err = ENOMEM;
1896	goto err_dstmap1;
1897	}
1898	} else if (crp->crp_flags & CRYPTO_F_IOV) {
1899	if (pci_map_uio(sc, &cmd->dst, cmd->dst_io)) {
1900	hifnstats.hst_nomem_load++;
1901	err = ENOMEM;
1902	goto err_dstmap1;
1903	}
1904	} else {
1905	if (pci_map_buf(sc, &cmd->dst, cmd->dst_buf, crp->crp_ilen)) {
1906	hifnstats.hst_nomem_load++;
1907	err = ENOMEM;
1908	goto err_dstmap1;
1909	}
1910	}
1911	}
1912
1913	#ifdef HIFN_DEBUG
1914	if (hifn_debug) {
1915	device_printf(sc->sc_dev,
1916	"Entering cmd: stat %8x ien %8x u %d/%d/%d/%d n %d/%d\n",
1917	READ_REG_1(sc, HIFN_1_DMA_CSR),
1918	READ_REG_1(sc, HIFN_1_DMA_IER),
1919	dma->cmdu, dma->srcu, dma->dstu, dma->resu,
1920	cmd->src_nsegs, cmd->dst_nsegs);
1921	}
1922	#endif
1923
1924	#if 0
1925	if (cmd->src_map == cmd->dst_map) {
1926	bus_dmamap_sync(sc->sc_dmat, cmd->src_map,
1927	BUS_DMASYNC_PREWRITE\|BUS_DMASYNC_PREREAD);
1928	} else {
1929	bus_dmamap_sync(sc->sc_dmat, cmd->src_map,
1930	BUS_DMASYNC_PREWRITE);
1931	bus_dmamap_sync(sc->sc_dmat, cmd->dst_map,
1932	BUS_DMASYNC_PREREAD);
1933	}
1934	#endif
1935
1936	/*
1937	* need N src, and N dst
1938	*/
1939	if ((dma->srcu + cmd->src_nsegs) > HIFN_D_SRC_RSIZE \|\|
1940	(dma->dstu + cmd->dst_nsegs + 1) > HIFN_D_DST_RSIZE) {
1941	#ifdef HIFN_DEBUG
1942	if (hifn_debug) {
1943	device_printf(sc->sc_dev,
1944	"src/dst exhaustion, srcu %u+%u dstu %u+%u\n",
1945	dma->srcu, cmd->src_nsegs,
1946	dma->dstu, cmd->dst_nsegs);
1947	}
1948	#endif
1949	hifnstats.hst_nomem_sd++;
1950	err = ERESTART;
1951	goto err_dstmap;
1952	}
1953
1954	if (dma->cmdi == HIFN_D_CMD_RSIZE) {
1955	dma->cmdi = 0;
1956	dma->cmdr[HIFN_D_CMD_RSIZE].l = htole32(HIFN_D_JUMP\|HIFN_D_MASKDONEIRQ);
1957	wmb();
1958	dma->cmdr[HIFN_D_CMD_RSIZE].l \|= htole32(HIFN_D_VALID);
1959	HIFN_CMDR_SYNC(sc, HIFN_D_CMD_RSIZE,
1960	BUS_DMASYNC_PREWRITE \| BUS_DMASYNC_PREREAD);
1961	}
1962	cmdi = dma->cmdi++;
1963	cmdlen = hifn_write_command(cmd, dma->command_bufs[cmdi]);
1964	HIFN_CMD_SYNC(sc, cmdi, BUS_DMASYNC_PREWRITE);
1965
1966	/* .p for command/result already set */
1967	dma->cmdr[cmdi].l = htole32(cmdlen \| HIFN_D_LAST \|
1968	HIFN_D_MASKDONEIRQ);
1969	wmb();
1970	dma->cmdr[cmdi].l \|= htole32(HIFN_D_VALID);
1971	HIFN_CMDR_SYNC(sc, cmdi,
1972	BUS_DMASYNC_PREWRITE \| BUS_DMASYNC_PREREAD);
1973	dma->cmdu++;
1974
1975	/*
1976	* We don't worry about missing an interrupt (which a "command wait"
1977	* interrupt salvages us from), unless there is more than one command
1978	* in the queue.
1979	*/
1980	if (dma->cmdu > 1) {
1981	sc->sc_dmaier \|= HIFN_DMAIER_C_WAIT;
1982	WRITE_REG_1(sc, HIFN_1_DMA_IER, sc->sc_dmaier);
1983	}
1984
1985	hifnstats.hst_ipackets++;
1986	hifnstats.hst_ibytes += cmd->src_mapsize;
1987
1988	hifn_dmamap_load_src(sc, cmd);
1989
1990	/*
1991	* Unlike other descriptors, we don't mask done interrupt from
1992	* result descriptor.
1993	*/
1994	#ifdef HIFN_DEBUG
1995	if (hifn_debug)
1996	device_printf(sc->sc_dev, "load res\n");
1997	#endif
1998	if (dma->resi == HIFN_D_RES_RSIZE) {
1999	dma->resi = 0;
2000	dma->resr[HIFN_D_RES_RSIZE].l = htole32(HIFN_D_JUMP\|HIFN_D_MASKDONEIRQ);
2001	wmb();
2002	dma->resr[HIFN_D_RES_RSIZE].l \|= htole32(HIFN_D_VALID);
2003	HIFN_RESR_SYNC(sc, HIFN_D_RES_RSIZE,
2004	BUS_DMASYNC_PREREAD \| BUS_DMASYNC_PREWRITE);
2005	}
2006	resi = dma->resi++;
2007	KASSERT(dma->hifn_commands[resi] == NULL,
2008	("hifn_crypto: command slot %u busy", resi));
2009	dma->hifn_commands[resi] = cmd;
2010	HIFN_RES_SYNC(sc, resi, BUS_DMASYNC_PREREAD);
2011	if ((hint & CRYPTO_HINT_MORE) && sc->sc_curbatch < hifn_maxbatch) {
2012	dma->resr[resi].l = htole32(HIFN_MAX_RESULT \|
2013	HIFN_D_LAST \| HIFN_D_MASKDONEIRQ);
2014	wmb();
2015	dma->resr[resi].l \|= htole32(HIFN_D_VALID);
2016	sc->sc_curbatch++;
2017	if (sc->sc_curbatch > hifnstats.hst_maxbatch)
2018	hifnstats.hst_maxbatch = sc->sc_curbatch;
2019	hifnstats.hst_totbatch++;
2020	} else {
2021	dma->resr[resi].l = htole32(HIFN_MAX_RESULT \| HIFN_D_LAST);
2022	wmb();
2023	dma->resr[resi].l \|= htole32(HIFN_D_VALID);
2024	sc->sc_curbatch = 0;
2025	}
2026	HIFN_RESR_SYNC(sc, resi,
2027	BUS_DMASYNC_PREREAD \| BUS_DMASYNC_PREWRITE);
2028	dma->resu++;
2029
2030	if (cmd->sloplen)
2031	cmd->slopidx = resi;
2032
2033	hifn_dmamap_load_dst(sc, cmd);
2034
2035	csr = 0;
2036	if (sc->sc_c_busy == 0) {
2037	csr \|= HIFN_DMACSR_C_CTRL_ENA;
2038	sc->sc_c_busy = 1;
2039	}
2040	if (sc->sc_s_busy == 0) {
2041	csr \|= HIFN_DMACSR_S_CTRL_ENA;
2042	sc->sc_s_busy = 1;
2043	}
2044	if (sc->sc_r_busy == 0) {
2045	csr \|= HIFN_DMACSR_R_CTRL_ENA;
2046	sc->sc_r_busy = 1;
2047	}
2048	if (sc->sc_d_busy == 0) {
2049	csr \|= HIFN_DMACSR_D_CTRL_ENA;
2050	sc->sc_d_busy = 1;
2051	}
2052	if (csr)
2053	WRITE_REG_1(sc, HIFN_1_DMA_CSR, csr);
2054
2055	#ifdef HIFN_DEBUG
2056	if (hifn_debug) {
2057	device_printf(sc->sc_dev, "command: stat %8x ier %8x\n",
2058	READ_REG_1(sc, HIFN_1_DMA_CSR),
2059	READ_REG_1(sc, HIFN_1_DMA_IER));
2060	}
2061	#endif
2062
2063	sc->sc_active = 5;
2064	HIFN_UNLOCK(sc);
2065	KASSERT(err == 0, ("hifn_crypto: success with error %u", err));
2066	return (err); /* success */
2067
2068	err_dstmap:
2069	if (cmd->src_map != cmd->dst_map)
2070	pci_unmap_buf(sc, &cmd->dst);
2071	err_dstmap1:
2072	err_srcmap:
2073	if (crp->crp_flags & CRYPTO_F_SKBUF) {
2074	if (cmd->src_skb != cmd->dst_skb)
2075	#ifdef NOTYET
2076	m_freem(cmd->dst_m);
2077	#else
2078	device_printf(sc->sc_dev,
2079	"%s,%d: CRYPTO_F_SKBUF src != dst not implemented\n",
2080	__FILE__, __LINE__);
2081	#endif
2082	}
2083	pci_unmap_buf(sc, &cmd->src);
2084	err_srcmap1:
2085	HIFN_UNLOCK(sc);
2086	return (err);
2087	}
2088
2089	static void
2090	hifn_tick(unsigned long arg)
2091	{
2092	struct hifn_softc *sc;
2093	unsigned long l_flags;
2094
2095	if (arg >= HIFN_MAX_CHIPS)
2096	return;
2097	sc = hifn_chip_idx[arg];
2098	if (!sc)
2099	return;
2100
2101	HIFN_LOCK(sc);
2102	if (sc->sc_active == 0) {
2103	struct hifn_dma *dma = sc->sc_dma;
2104	u_int32_t r = 0;
2105
2106	if (dma->cmdu == 0 && sc->sc_c_busy) {
2107	sc->sc_c_busy = 0;
2108	r \|= HIFN_DMACSR_C_CTRL_DIS;
2109	}
2110	if (dma->srcu == 0 && sc->sc_s_busy) {
2111	sc->sc_s_busy = 0;
2112	r \|= HIFN_DMACSR_S_CTRL_DIS;
2113	}
2114	if (dma->dstu == 0 && sc->sc_d_busy) {
2115	sc->sc_d_busy = 0;
2116	r \|= HIFN_DMACSR_D_CTRL_DIS;
2117	}
2118	if (dma->resu == 0 && sc->sc_r_busy) {
2119	sc->sc_r_busy = 0;
2120	r \|= HIFN_DMACSR_R_CTRL_DIS;
2121	}
2122	if (r)
2123	WRITE_REG_1(sc, HIFN_1_DMA_CSR, r);
2124	} else
2125	sc->sc_active--;
2126	HIFN_UNLOCK(sc);
2127	mod_timer(&sc->sc_tickto, jiffies + HZ);
2128	}
2129
2130	static irqreturn_t
2131	#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,19)
2132	hifn_intr(int irq, void *arg)
2133	#else
2134	hifn_intr(int irq, void arg, struct pt_regs regs)
2135	#endif
2136	{
2137	struct hifn_softc *sc = arg;
2138	struct hifn_dma *dma;
2139	u_int32_t dmacsr, restart;
2140	int i, u;
2141	unsigned long l_flags;
2142
2143	dmacsr = READ_REG_1(sc, HIFN_1_DMA_CSR);
2144
2145	/* Nothing in the DMA unit interrupted */
2146	if ((dmacsr & sc->sc_dmaier) == 0)
2147	return IRQ_NONE;
2148
2149	HIFN_LOCK(sc);
2150
2151	dma = sc->sc_dma;
2152
2153	#ifdef HIFN_DEBUG
2154	if (hifn_debug) {
2155	device_printf(sc->sc_dev,
2156	"irq: stat %08x ien %08x damier %08x i %d/%d/%d/%d k %d/%d/%d/%d u %d/%d/%d/%d\n",
2157	dmacsr, READ_REG_1(sc, HIFN_1_DMA_IER), sc->sc_dmaier,
2158	dma->cmdi, dma->srci, dma->dsti, dma->resi,
2159	dma->cmdk, dma->srck, dma->dstk, dma->resk,
2160	dma->cmdu, dma->srcu, dma->dstu, dma->resu);
2161	}
2162	#endif
2163
2164	WRITE_REG_1(sc, HIFN_1_DMA_CSR, dmacsr & sc->sc_dmaier);
2165
2166	if ((sc->sc_flags & HIFN_HAS_PUBLIC) &&
2167	(dmacsr & HIFN_DMACSR_PUBDONE))
2168	WRITE_REG_1(sc, HIFN_1_PUB_STATUS,
2169	READ_REG_1(sc, HIFN_1_PUB_STATUS) \| HIFN_PUBSTS_DONE);
2170
2171	restart = dmacsr & (HIFN_DMACSR_D_OVER \| HIFN_DMACSR_R_OVER);
2172	if (restart)
2173	device_printf(sc->sc_dev, "overrun %x\n", dmacsr);
2174
2175	if (sc->sc_flags & HIFN_IS_7811) {
2176	if (dmacsr & HIFN_DMACSR_ILLR)
2177	device_printf(sc->sc_dev, "illegal read\n");
2178	if (dmacsr & HIFN_DMACSR_ILLW)
2179	device_printf(sc->sc_dev, "illegal write\n");
2180	}
2181
2182	restart = dmacsr & (HIFN_DMACSR_C_ABORT \| HIFN_DMACSR_S_ABORT \|
2183	HIFN_DMACSR_D_ABORT \| HIFN_DMACSR_R_ABORT);
2184	if (restart) {
2185	device_printf(sc->sc_dev, "abort, resetting.\n");
2186	hifnstats.hst_abort++;
2187	hifn_abort(sc);
2188	HIFN_UNLOCK(sc);
2189	return IRQ_HANDLED;
2190	}
2191
2192	if ((dmacsr & HIFN_DMACSR_C_WAIT) && (dma->cmdu == 0)) {
2193	/*
2194	* If no slots to process and we receive a "waiting on
2195	* command" interrupt, we disable the "waiting on command"
2196	* (by clearing it).
2197	*/
2198	sc->sc_dmaier &= ~HIFN_DMAIER_C_WAIT;
2199	WRITE_REG_1(sc, HIFN_1_DMA_IER, sc->sc_dmaier);
2200	}
2201
2202	/* clear the rings */
2203	i = dma->resk; u = dma->resu;
2204	while (u != 0) {
2205	HIFN_RESR_SYNC(sc, i,
2206	BUS_DMASYNC_POSTREAD \| BUS_DMASYNC_POSTWRITE);
2207	if (dma->resr[i].l & htole32(HIFN_D_VALID)) {
2208	HIFN_RESR_SYNC(sc, i,
2209	BUS_DMASYNC_PREREAD \| BUS_DMASYNC_PREWRITE);
2210	break;
2211	}
2212
2213	if (i != HIFN_D_RES_RSIZE) {
2214	struct hifn_command *cmd;
2215	u_int8_t *macbuf = NULL;
2216
2217	HIFN_RES_SYNC(sc, i, BUS_DMASYNC_POSTREAD);
2218	cmd = dma->hifn_commands[i];
2219	KASSERT(cmd != NULL,
2220	("hifn_intr: null command slot %u", i));
2221	dma->hifn_commands[i] = NULL;
2222
2223	if (cmd->base_masks & HIFN_BASE_CMD_MAC) {
2224	macbuf = dma->result_bufs[i];
2225	macbuf += 12;
2226	}
2227
2228	hifn_callback(sc, cmd, macbuf);
2229	hifnstats.hst_opackets++;
2230	u--;
2231	}
2232
2233	if (++i == (HIFN_D_RES_RSIZE + 1))
2234	i = 0;
2235	}
2236	dma->resk = i; dma->resu = u;
2237
2238	i = dma->srck; u = dma->srcu;
2239	while (u != 0) {
2240	if (i == HIFN_D_SRC_RSIZE)
2241	i = 0;
2242	HIFN_SRCR_SYNC(sc, i,
2243	BUS_DMASYNC_POSTREAD \| BUS_DMASYNC_POSTWRITE);
2244	if (dma->srcr[i].l & htole32(HIFN_D_VALID)) {
2245	HIFN_SRCR_SYNC(sc, i,
2246	BUS_DMASYNC_PREREAD \| BUS_DMASYNC_PREWRITE);
2247	break;
2248	}
2249	i++, u--;
2250	}
2251	dma->srck = i; dma->srcu = u;
2252
2253	i = dma->cmdk; u = dma->cmdu;
2254	while (u != 0) {
2255	HIFN_CMDR_SYNC(sc, i,
2256	BUS_DMASYNC_POSTREAD \| BUS_DMASYNC_POSTWRITE);
2257	if (dma->cmdr[i].l & htole32(HIFN_D_VALID)) {
2258	HIFN_CMDR_SYNC(sc, i,
2259	BUS_DMASYNC_PREREAD \| BUS_DMASYNC_PREWRITE);
2260	break;
2261	}
2262	if (i != HIFN_D_CMD_RSIZE) {
2263	u--;
2264	HIFN_CMD_SYNC(sc, i, BUS_DMASYNC_POSTWRITE);
2265	}
2266	if (++i == (HIFN_D_CMD_RSIZE + 1))
2267	i = 0;
2268	}
2269	dma->cmdk = i; dma->cmdu = u;
2270
2271	HIFN_UNLOCK(sc);
2272
2273	if (sc->sc_needwakeup) { /* XXX check high watermark */
2274	int wakeup = sc->sc_needwakeup & (CRYPTO_SYMQ\|CRYPTO_ASYMQ);
2275	#ifdef HIFN_DEBUG
2276	if (hifn_debug)
2277	device_printf(sc->sc_dev,
2278	"wakeup crypto (%x) u %d/%d/%d/%d\n",
2279	sc->sc_needwakeup,
2280	dma->cmdu, dma->srcu, dma->dstu, dma->resu);
2281	#endif
2282	sc->sc_needwakeup &= ~wakeup;
2283	crypto_unblock(sc->sc_cid, wakeup);
2284	}
2285
2286	return IRQ_HANDLED;
2287	}
2288
2289	/*
2290	* Allocate a new 'session' and return an encoded session id. 'sidp'
2291	* contains our registration id, and should contain an encoded session
2292	* id on successful allocation.
2293	*/
2294	static int
2295	hifn_newsession(device_t dev, u_int32_t sidp, struct cryptoini cri)
2296	{
2297	struct hifn_softc *sc = device_get_softc(dev);
2298	struct cryptoini *c;
2299	int mac = 0, cry = 0, sesn;
2300	struct hifn_session *ses = NULL;
2301	unsigned long l_flags;
2302
2303	DPRINTF("%s()\n", __FUNCTION__);
2304
2305	KASSERT(sc != NULL, ("hifn_newsession: null softc"));
2306	if (sidp == NULL \|\| cri == NULL \|\| sc == NULL) {
2307	DPRINTF("%s,%d: %s - EINVAL\n", __FILE__, __LINE__, __FUNCTION__);
2308	return (EINVAL);
2309	}
2310
2311	HIFN_LOCK(sc);
2312	if (sc->sc_sessions == NULL) {
2313	ses = sc->sc_sessions = (struct hifn_session )kmalloc(sizeof(ses),
2314	SLAB_ATOMIC);
2315	if (ses == NULL) {
2316	HIFN_UNLOCK(sc);
2317	return (ENOMEM);
2318	}
2319	sesn = 0;
2320	sc->sc_nsessions = 1;
2321	} else {
2322	for (sesn = 0; sesn < sc->sc_nsessions; sesn++) {
2323	if (!sc->sc_sessions[sesn].hs_used) {
2324	ses = &sc->sc_sessions[sesn];
2325	break;
2326	}
2327	}
2328
2329	if (ses == NULL) {
2330	sesn = sc->sc_nsessions;
2331	ses = (struct hifn_session )kmalloc((sesn + 1) sizeof(*ses),
2332	SLAB_ATOMIC);
2333	if (ses == NULL) {
2334	HIFN_UNLOCK(sc);
2335	return (ENOMEM);
2336	}
2337	bcopy(sc->sc_sessions, ses, sesn * sizeof(*ses));
2338	bzero(sc->sc_sessions, sesn * sizeof(*ses));
2339	kfree(sc->sc_sessions);
2340	sc->sc_sessions = ses;
2341	ses = &sc->sc_sessions[sesn];
2342	sc->sc_nsessions++;
2343	}
2344	}
2345	HIFN_UNLOCK(sc);
2346
2347	bzero(ses, sizeof(*ses));
2348	ses->hs_used = 1;
2349
2350	for (c = cri; c != NULL; c = c->cri_next) {
2351	switch (c->cri_alg) {
2352	case CRYPTO_MD5:
2353	case CRYPTO_SHA1:
2354	case CRYPTO_MD5_HMAC:
2355	case CRYPTO_SHA1_HMAC:
2356	if (mac) {
2357	DPRINTF("%s,%d: %s - EINVAL\n",__FILE__,__LINE__,__FUNCTION__);
2358	return (EINVAL);
2359	}
2360	mac = 1;
2361	ses->hs_mlen = c->cri_mlen;
2362	if (ses->hs_mlen == 0) {
2363	switch (c->cri_alg) {
2364	case CRYPTO_MD5:
2365	case CRYPTO_MD5_HMAC:
2366	ses->hs_mlen = 16;
2367	break;
2368	case CRYPTO_SHA1:
2369	case CRYPTO_SHA1_HMAC:
2370	ses->hs_mlen = 20;
2371	break;
2372	}
2373	}
2374	break;
2375	case CRYPTO_DES_CBC:
2376	case CRYPTO_3DES_CBC:
2377	case CRYPTO_AES_CBC:
2378	case CRYPTO_ARC4:
2379	if (cry) {
2380	DPRINTF("%s,%d: %s - EINVAL\n",__FILE__,__LINE__,__FUNCTION__);
2381	return (EINVAL);
2382	}
2383	cry = 1;
2384	break;
2385	default:
2386	DPRINTF("%s,%d: %s - EINVAL\n",__FILE__,__LINE__,__FUNCTION__);
2387	return (EINVAL);
2388	}
2389	}
2390	if (mac == 0 && cry == 0) {
2391	DPRINTF("%s,%d: %s - EINVAL\n",__FILE__,__LINE__,__FUNCTION__);
2392	return (EINVAL);
2393	}
2394
2395	*sidp = HIFN_SID(device_get_unit(sc->sc_dev), sesn);
2396
2397	return (0);
2398	}
2399
2400	/*
2401	* Deallocate a session.
2402	* XXX this routine should run a zero'd mac/encrypt key into context ram.
2403	* XXX to blow away any keys already stored there.
2404	*/
2405	static int
2406	hifn_freesession(device_t dev, u_int64_t tid)
2407	{
2408	struct hifn_softc *sc = device_get_softc(dev);
2409	int session, error;
2410	u_int32_t sid = CRYPTO_SESID2LID(tid);
2411	unsigned long l_flags;
2412
2413	DPRINTF("%s()\n", __FUNCTION__);
2414
2415	KASSERT(sc != NULL, ("hifn_freesession: null softc"));
2416	if (sc == NULL) {
2417	DPRINTF("%s,%d: %s - EINVAL\n",__FILE__,__LINE__,__FUNCTION__);
2418	return (EINVAL);
2419	}
2420
2421	HIFN_LOCK(sc);
2422	session = HIFN_SESSION(sid);
2423	if (session < sc->sc_nsessions) {
2424	bzero(&sc->sc_sessions[session], sizeof(struct hifn_session));
2425	error = 0;
2426	} else {
2427	DPRINTF("%s,%d: %s - EINVAL\n",__FILE__,__LINE__,__FUNCTION__);
2428	error = EINVAL;
2429	}
2430	HIFN_UNLOCK(sc);
2431
2432	return (error);
2433	}
2434
2435	static int
2436	hifn_process(device_t dev, struct cryptop *crp, int hint)
2437	{
2438	struct hifn_softc *sc = device_get_softc(dev);
2439	struct hifn_command *cmd = NULL;
2440	int session, err, ivlen;
2441	struct cryptodesc crd1, crd2, maccrd, enccrd;
2442
2443	DPRINTF("%s()\n", __FUNCTION__);
2444
2445	if (crp == NULL \|\| crp->crp_callback == NULL) {
2446	hifnstats.hst_invalid++;
2447	DPRINTF("%s,%d: %s - EINVAL\n",__FILE__,__LINE__,__FUNCTION__);
2448	return (EINVAL);
2449	}
2450	session = HIFN_SESSION(crp->crp_sid);
2451
2452	if (sc == NULL \|\| session >= sc->sc_nsessions) {
2453	DPRINTF("%s,%d: %s - EINVAL\n",__FILE__,__LINE__,__FUNCTION__);
2454	err = EINVAL;
2455	goto errout;
2456	}
2457
2458	cmd = kmalloc(sizeof(struct hifn_command), SLAB_ATOMIC);
2459	if (cmd == NULL) {
2460	hifnstats.hst_nomem++;
2461	err = ENOMEM;
2462	goto errout;
2463	}
2464	memset(cmd, 0, sizeof(*cmd));
2465
2466	if (crp->crp_flags & CRYPTO_F_SKBUF) {
2467	cmd->src_skb = (struct sk_buff *)crp->crp_buf;
2468	cmd->dst_skb = (struct sk_buff *)crp->crp_buf;
2469	} else if (crp->crp_flags & CRYPTO_F_IOV) {
2470	cmd->src_io = (struct uio *)crp->crp_buf;
2471	cmd->dst_io = (struct uio *)crp->crp_buf;
2472	} else {
2473	cmd->src_buf = crp->crp_buf;
2474	cmd->dst_buf = crp->crp_buf;
2475	}
2476
2477	crd1 = crp->crp_desc;
2478	if (crd1 == NULL) {
2479	DPRINTF("%s,%d: %s - EINVAL\n",__FILE__,__LINE__,__FUNCTION__);
2480	err = EINVAL;
2481	goto errout;
2482	}
2483	crd2 = crd1->crd_next;
2484
2485	if (crd2 == NULL) {
2486	if (crd1->crd_alg == CRYPTO_MD5_HMAC \|\|
2487	crd1->crd_alg == CRYPTO_SHA1_HMAC \|\|
2488	crd1->crd_alg == CRYPTO_SHA1 \|\|
2489	crd1->crd_alg == CRYPTO_MD5) {
2490	maccrd = crd1;
2491	enccrd = NULL;
2492	} else if (crd1->crd_alg == CRYPTO_DES_CBC \|\|
2493	crd1->crd_alg == CRYPTO_3DES_CBC \|\|
2494	crd1->crd_alg == CRYPTO_AES_CBC \|\|
2495	crd1->crd_alg == CRYPTO_ARC4) {
2496	if ((crd1->crd_flags & CRD_F_ENCRYPT) == 0)
2497	cmd->base_masks \|= HIFN_BASE_CMD_DECODE;
2498	maccrd = NULL;
2499	enccrd = crd1;
2500	} else {
2501	DPRINTF("%s,%d: %s - EINVAL\n",__FILE__,__LINE__,__FUNCTION__);
2502	err = EINVAL;
2503	goto errout;
2504	}
2505	} else {
2506	if ((crd1->crd_alg == CRYPTO_MD5_HMAC \|\|
2507	crd1->crd_alg == CRYPTO_SHA1_HMAC \|\|
2508	crd1->crd_alg == CRYPTO_MD5 \|\|
2509	crd1->crd_alg == CRYPTO_SHA1) &&
2510	(crd2->crd_alg == CRYPTO_DES_CBC \|\|
2511	crd2->crd_alg == CRYPTO_3DES_CBC \|\|
2512	crd2->crd_alg == CRYPTO_AES_CBC \|\|
2513	crd2->crd_alg == CRYPTO_ARC4) &&
2514	((crd2->crd_flags & CRD_F_ENCRYPT) == 0)) {
2515	cmd->base_masks = HIFN_BASE_CMD_DECODE;
2516	maccrd = crd1;
2517	enccrd = crd2;
2518	} else if ((crd1->crd_alg == CRYPTO_DES_CBC \|\|
2519	crd1->crd_alg == CRYPTO_ARC4 \|\|
2520	crd1->crd_alg == CRYPTO_3DES_CBC \|\|
2521	crd1->crd_alg == CRYPTO_AES_CBC) &&
2522	(crd2->crd_alg == CRYPTO_MD5_HMAC \|\|
2523	crd2->crd_alg == CRYPTO_SHA1_HMAC \|\|
2524	crd2->crd_alg == CRYPTO_MD5 \|\|
2525	crd2->crd_alg == CRYPTO_SHA1) &&
2526	(crd1->crd_flags & CRD_F_ENCRYPT)) {
2527	enccrd = crd1;
2528	maccrd = crd2;
2529	} else {
2530	/*
2531	* We cannot order the 7751 as requested
2532	*/
2533	DPRINTF("%s,%d: %s %d,%d,%d - EINVAL\n",__FILE__,__LINE__,__FUNCTION__, crd1->crd_alg, crd2->crd_alg, crd1->crd_flags & CRD_F_ENCRYPT);
2534	err = EINVAL;
2535	goto errout;
2536	}
2537	}
2538
2539	if (enccrd) {
2540	cmd->enccrd = enccrd;
2541	cmd->base_masks \|= HIFN_BASE_CMD_CRYPT;
2542	switch (enccrd->crd_alg) {
2543	case CRYPTO_ARC4:
2544	cmd->cry_masks \|= HIFN_CRYPT_CMD_ALG_RC4;
2545	break;
2546	case CRYPTO_DES_CBC:
2547	cmd->cry_masks \|= HIFN_CRYPT_CMD_ALG_DES \|
2548	HIFN_CRYPT_CMD_MODE_CBC \|
2549	HIFN_CRYPT_CMD_NEW_IV;
2550	break;
2551	case CRYPTO_3DES_CBC:
2552	cmd->cry_masks \|= HIFN_CRYPT_CMD_ALG_3DES \|
2553	HIFN_CRYPT_CMD_MODE_CBC \|
2554	HIFN_CRYPT_CMD_NEW_IV;
2555	break;
2556	case CRYPTO_AES_CBC:
2557	cmd->cry_masks \|= HIFN_CRYPT_CMD_ALG_AES \|
2558	HIFN_CRYPT_CMD_MODE_CBC \|
2559	HIFN_CRYPT_CMD_NEW_IV;
2560	break;
2561	default:
2562	DPRINTF("%s,%d: %s - EINVAL\n",__FILE__,__LINE__,__FUNCTION__);
2563	err = EINVAL;
2564	goto errout;
2565	}
2566	if (enccrd->crd_alg != CRYPTO_ARC4) {
2567	ivlen = ((enccrd->crd_alg == CRYPTO_AES_CBC) ?
2568	HIFN_AES_IV_LENGTH : HIFN_IV_LENGTH);
2569	if (enccrd->crd_flags & CRD_F_ENCRYPT) {
2570	if (enccrd->crd_flags & CRD_F_IV_EXPLICIT)
2571	bcopy(enccrd->crd_iv, cmd->iv, ivlen);
2572	else
2573	read_random(cmd->iv, ivlen);
2574
2575	if ((enccrd->crd_flags & CRD_F_IV_PRESENT)
2576	== 0) {
2577	crypto_copyback(crp->crp_flags,
2578	crp->crp_buf, enccrd->crd_inject,
2579	ivlen, cmd->iv);
2580	}
2581	} else {
2582	if (enccrd->crd_flags & CRD_F_IV_EXPLICIT)
2583	bcopy(enccrd->crd_iv, cmd->iv, ivlen);
2584	else {
2585	crypto_copydata(crp->crp_flags,
2586	crp->crp_buf, enccrd->crd_inject,
2587	ivlen, cmd->iv);
2588	}
2589	}
2590	}
2591
2592	if (enccrd->crd_flags & CRD_F_KEY_EXPLICIT)
2593	cmd->cry_masks \|= HIFN_CRYPT_CMD_NEW_KEY;
2594	cmd->ck = enccrd->crd_key;
2595	cmd->cklen = enccrd->crd_klen >> 3;
2596	cmd->cry_masks \|= HIFN_CRYPT_CMD_NEW_KEY;
2597
2598	/*
2599	* Need to specify the size for the AES key in the masks.
2600	*/
2601	if ((cmd->cry_masks & HIFN_CRYPT_CMD_ALG_MASK) ==
2602	HIFN_CRYPT_CMD_ALG_AES) {
2603	switch (cmd->cklen) {
2604	case 16:
2605	cmd->cry_masks \|= HIFN_CRYPT_CMD_KSZ_128;
2606	break;
2607	case 24:
2608	cmd->cry_masks \|= HIFN_CRYPT_CMD_KSZ_192;
2609	break;
2610	case 32:
2611	cmd->cry_masks \|= HIFN_CRYPT_CMD_KSZ_256;
2612	break;
2613	default:
2614	DPRINTF("%s,%d: %s - EINVAL\n",__FILE__,__LINE__,__FUNCTION__);
2615	err = EINVAL;
2616	goto errout;
2617	}
2618	}
2619	}
2620
2621	if (maccrd) {
2622	cmd->maccrd = maccrd;
2623	cmd->base_masks \|= HIFN_BASE_CMD_MAC;
2624
2625	switch (maccrd->crd_alg) {
2626	case CRYPTO_MD5:
2627	cmd->mac_masks \|= HIFN_MAC_CMD_ALG_MD5 \|
2628	HIFN_MAC_CMD_RESULT \| HIFN_MAC_CMD_MODE_HASH \|
2629	HIFN_MAC_CMD_POS_IPSEC;
2630	break;
2631	case CRYPTO_MD5_HMAC:
2632	cmd->mac_masks \|= HIFN_MAC_CMD_ALG_MD5 \|
2633	HIFN_MAC_CMD_RESULT \| HIFN_MAC_CMD_MODE_HMAC \|
2634	HIFN_MAC_CMD_POS_IPSEC \| HIFN_MAC_CMD_TRUNC;
2635	break;
2636	case CRYPTO_SHA1:
2637	cmd->mac_masks \|= HIFN_MAC_CMD_ALG_SHA1 \|
2638	HIFN_MAC_CMD_RESULT \| HIFN_MAC_CMD_MODE_HASH \|
2639	HIFN_MAC_CMD_POS_IPSEC;
2640	break;
2641	case CRYPTO_SHA1_HMAC:
2642	cmd->mac_masks \|= HIFN_MAC_CMD_ALG_SHA1 \|
2643	HIFN_MAC_CMD_RESULT \| HIFN_MAC_CMD_MODE_HMAC \|
2644	HIFN_MAC_CMD_POS_IPSEC \| HIFN_MAC_CMD_TRUNC;
2645	break;
2646	}
2647
2648	if (maccrd->crd_alg == CRYPTO_SHA1_HMAC \|\|
2649	maccrd->crd_alg == CRYPTO_MD5_HMAC) {
2650	cmd->mac_masks \|= HIFN_MAC_CMD_NEW_KEY;
2651	bcopy(maccrd->crd_key, cmd->mac, maccrd->crd_klen >> 3);
2652	bzero(cmd->mac + (maccrd->crd_klen >> 3),
2653	HIFN_MAC_KEY_LENGTH - (maccrd->crd_klen >> 3));
2654	}
2655	}
2656
2657	cmd->crp = crp;
2658	cmd->session_num = session;
2659	cmd->softc = sc;
2660
2661	err = hifn_crypto(sc, cmd, crp, hint);
2662	if (!err) {
2663	return 0;
2664	} else if (err == ERESTART) {
2665	/*
2666	* There weren't enough resources to dispatch the request
2667	* to the part. Notify the caller so they'll requeue this
2668	* request and resubmit it again soon.
2669	*/
2670	#ifdef HIFN_DEBUG
2671	if (hifn_debug)
2672	device_printf(sc->sc_dev, "requeue request\n");
2673	#endif
2674	kfree(cmd);
2675	sc->sc_needwakeup \|= CRYPTO_SYMQ;
2676	return (err);
2677	}
2678
2679	errout:
2680	if (cmd != NULL)
2681	kfree(cmd);
2682	if (err == EINVAL)
2683	hifnstats.hst_invalid++;
2684	else
2685	hifnstats.hst_nomem++;
2686	crp->crp_etype = err;
2687	crypto_done(crp);
2688	return (err);
2689	}
2690
2691	static void
2692	hifn_abort(struct hifn_softc *sc)
2693	{
2694	struct hifn_dma *dma = sc->sc_dma;
2695	struct hifn_command *cmd;
2696	struct cryptop *crp;
2697	int i, u;
2698
2699	DPRINTF("%s()\n", __FUNCTION__);
2700
2701	i = dma->resk; u = dma->resu;
2702	while (u != 0) {
2703	cmd = dma->hifn_commands[i];
2704	KASSERT(cmd != NULL, ("hifn_abort: null command slot %u", i));
2705	dma->hifn_commands[i] = NULL;
2706	crp = cmd->crp;
2707
2708	if ((dma->resr[i].l & htole32(HIFN_D_VALID)) == 0) {
2709	/* Salvage what we can. */
2710	u_int8_t *macbuf;
2711
2712	if (cmd->base_masks & HIFN_BASE_CMD_MAC) {
2713	macbuf = dma->result_bufs[i];
2714	macbuf += 12;
2715	} else
2716	macbuf = NULL;
2717	hifnstats.hst_opackets++;
2718	hifn_callback(sc, cmd, macbuf);
2719	} else {
2720	#if 0
2721	if (cmd->src_map == cmd->dst_map) {
2722	bus_dmamap_sync(sc->sc_dmat, cmd->src_map,
2723	BUS_DMASYNC_POSTREAD\|BUS_DMASYNC_POSTWRITE);
2724	} else {
2725	bus_dmamap_sync(sc->sc_dmat, cmd->src_map,
2726	BUS_DMASYNC_POSTWRITE);
2727	bus_dmamap_sync(sc->sc_dmat, cmd->dst_map,
2728	BUS_DMASYNC_POSTREAD);
2729	}
2730	#endif
2731
2732	if (cmd->src_skb != cmd->dst_skb) {
2733	#ifdef NOTYET
2734	m_freem(cmd->src_m);
2735	crp->crp_buf = (caddr_t)cmd->dst_m;
2736	#else
2737	device_printf(sc->sc_dev,
2738	"%s,%d: CRYPTO_F_SKBUF src != dst not implemented\n",
2739	__FILE__, __LINE__);
2740	#endif
2741	}
2742
2743	/* non-shared buffers cannot be restarted */
2744	if (cmd->src_map != cmd->dst_map) {
2745	/*
2746	* XXX should be EAGAIN, delayed until
2747	* after the reset.
2748	*/
2749	crp->crp_etype = ENOMEM;
2750	pci_unmap_buf(sc, &cmd->dst);
2751	} else
2752	crp->crp_etype = ENOMEM;
2753
2754	pci_unmap_buf(sc, &cmd->src);
2755
2756	kfree(cmd);
2757	if (crp->crp_etype != EAGAIN)
2758	crypto_done(crp);
2759	}
2760
2761	if (++i == HIFN_D_RES_RSIZE)
2762	i = 0;
2763	u--;
2764	}
2765	dma->resk = i; dma->resu = u;
2766
2767	hifn_reset_board(sc, 1);
2768	hifn_init_dma(sc);
2769	hifn_init_pci_registers(sc);
2770	}
2771
2772	static void
2773	hifn_callback(struct hifn_softc sc, struct hifn_command cmd, u_int8_t *macbuf)
2774	{
2775	struct hifn_dma *dma = sc->sc_dma;
2776	struct cryptop *crp = cmd->crp;
2777	struct cryptodesc *crd;
2778	int i, u;
2779
2780	DPRINTF("%s()\n", __FUNCTION__);
2781
2782	#if 0
2783	if (cmd->src_map == cmd->dst_map) {
2784	bus_dmamap_sync(sc->sc_dmat, cmd->src_map,
2785	BUS_DMASYNC_POSTWRITE \| BUS_DMASYNC_POSTREAD);
2786	} else {
2787	bus_dmamap_sync(sc->sc_dmat, cmd->src_map,
2788	BUS_DMASYNC_POSTWRITE);
2789	bus_dmamap_sync(sc->sc_dmat, cmd->dst_map,
2790	BUS_DMASYNC_POSTREAD);
2791	}
2792	#endif
2793
2794	if (crp->crp_flags & CRYPTO_F_SKBUF) {
2795	if (cmd->src_skb != cmd->dst_skb) {
2796	#ifdef NOTYET
2797	crp->crp_buf = (caddr_t)cmd->dst_m;
2798	totlen = cmd->src_mapsize;
2799	for (m = cmd->dst_m; m != NULL; m = m->m_next) {
2800	if (totlen < m->m_len) {
2801	m->m_len = totlen;
2802	totlen = 0;
2803	} else
2804	totlen -= m->m_len;
2805	}
2806	cmd->dst_m->m_pkthdr.len = cmd->src_m->m_pkthdr.len;
2807	m_freem(cmd->src_m);
2808	#else
2809	device_printf(sc->sc_dev,
2810	"%s,%d: CRYPTO_F_SKBUF src != dst not implemented\n",
2811	__FILE__, __LINE__);
2812	#endif
2813	}
2814	}
2815
2816	if (cmd->sloplen != 0) {
2817	crypto_copyback(crp->crp_flags, crp->crp_buf,
2818	cmd->src_mapsize - cmd->sloplen, cmd->sloplen,
2819	(caddr_t)&dma->slop[cmd->slopidx]);
2820	}
2821
2822	i = dma->dstk; u = dma->dstu;
2823	while (u != 0) {
2824	if (i == HIFN_D_DST_RSIZE)
2825	i = 0;
2826	#if 0
2827	bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap,
2828	BUS_DMASYNC_POSTREAD \| BUS_DMASYNC_POSTWRITE);
2829	#endif
2830	if (dma->dstr[i].l & htole32(HIFN_D_VALID)) {
2831	#if 0
2832	bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap,
2833	BUS_DMASYNC_PREREAD \| BUS_DMASYNC_PREWRITE);
2834	#endif
2835	break;
2836	}
2837	i++, u--;
2838	}
2839	dma->dstk = i; dma->dstu = u;
2840
2841	hifnstats.hst_obytes += cmd->dst_mapsize;
2842
2843	if (macbuf != NULL) {
2844	for (crd = crp->crp_desc; crd; crd = crd->crd_next) {
2845	int len;
2846
2847	if (crd->crd_alg != CRYPTO_MD5 &&
2848	crd->crd_alg != CRYPTO_SHA1 &&
2849	crd->crd_alg != CRYPTO_MD5_HMAC &&
2850	crd->crd_alg != CRYPTO_SHA1_HMAC) {
2851	continue;
2852	}
2853	len = cmd->softc->sc_sessions[cmd->session_num].hs_mlen;
2854	crypto_copyback(crp->crp_flags, crp->crp_buf,
2855	crd->crd_inject, len, macbuf);
2856	break;
2857	}
2858	}
2859
2860	if (cmd->src_map != cmd->dst_map)
2861	pci_unmap_buf(sc, &cmd->dst);
2862	pci_unmap_buf(sc, &cmd->src);
2863	kfree(cmd);
2864	crypto_done(crp);
2865	}
2866
2867	/*
2868	* 7811 PB3 rev/2 parts lock-up on burst writes to Group 0
2869	* and Group 1 registers; avoid conditions that could create
2870	* burst writes by doing a read in between the writes.
2871	*
2872	* NB: The read we interpose is always to the same register;
2873	* we do this because reading from an arbitrary (e.g. last)
2874	* register may not always work.
2875	*/
2876	static void
2877	hifn_write_reg_0(struct hifn_softc *sc, bus_size_t reg, u_int32_t val)
2878	{
2879	if (sc->sc_flags & HIFN_IS_7811) {
2880	if (sc->sc_bar0_lastreg == reg - 4)
2881	readl(sc->sc_bar0 + HIFN_0_PUCNFG);
2882	sc->sc_bar0_lastreg = reg;
2883	}
2884	writel(val, sc->sc_bar0 + reg);
2885	}
2886
2887	static void
2888	hifn_write_reg_1(struct hifn_softc *sc, bus_size_t reg, u_int32_t val)
2889	{
2890	if (sc->sc_flags & HIFN_IS_7811) {
2891	if (sc->sc_bar1_lastreg == reg - 4)
2892	readl(sc->sc_bar1 + HIFN_1_REVID);
2893	sc->sc_bar1_lastreg = reg;
2894	}
2895	writel(val, sc->sc_bar1 + reg);
2896	}
2897
2898
2899	static struct pci_device_id hifn_pci_tbl[] = {
2900	{ PCI_VENDOR_HIFN, PCI_PRODUCT_HIFN_7951,
2901	PCI_ANY_ID, PCI_ANY_ID, 0, 0, },
2902	{ PCI_VENDOR_HIFN, PCI_PRODUCT_HIFN_7955,
2903	PCI_ANY_ID, PCI_ANY_ID, 0, 0, },
2904	{ PCI_VENDOR_HIFN, PCI_PRODUCT_HIFN_7956,
2905	PCI_ANY_ID, PCI_ANY_ID, 0, 0, },
2906	{ PCI_VENDOR_NETSEC, PCI_PRODUCT_NETSEC_7751,
2907	PCI_ANY_ID, PCI_ANY_ID, 0, 0, },
2908	{ PCI_VENDOR_INVERTEX, PCI_PRODUCT_INVERTEX_AEON,
2909	PCI_ANY_ID, PCI_ANY_ID, 0, 0, },
2910	{ PCI_VENDOR_HIFN, PCI_PRODUCT_HIFN_7811,
2911	PCI_ANY_ID, PCI_ANY_ID, 0, 0, },
2912	/*
2913	* Other vendors share this PCI ID as well, such as
2914	* http://www.powercrypt.com, and obviously they also
2915	* use the same key.
2916	*/
2917	{ PCI_VENDOR_HIFN, PCI_PRODUCT_HIFN_7751,
2918	PCI_ANY_ID, PCI_ANY_ID, 0, 0, },
2919	{ 0, 0, 0, 0, 0, 0, }
2920	};
2921	MODULE_DEVICE_TABLE(pci, hifn_pci_tbl);
2922
2923	static struct pci_driver hifn_driver = {
2924	.name = "hifn",
2925	.id_table = hifn_pci_tbl,
2926	.probe = hifn_probe,
2927	.remove = hifn_remove,
2928	/* add PM stuff here one day */
2929	};
2930
2931	static int __init hifn_init (void)
2932	{
2933	struct hifn_softc *sc = NULL;
2934	int rc;
2935
2936	DPRINTF("%s(%p)\n", __FUNCTION__, hifn_init);
2937
2938	rc = pci_register_driver(&hifn_driver);
2939	pci_register_driver_compat(&hifn_driver, rc);
2940
2941	return rc;
2942	}
2943
2944	static void __exit hifn_exit (void)
2945	{
2946	pci_unregister_driver(&hifn_driver);
2947	}
2948
2949	module_init(hifn_init);
2950	module_exit(hifn_exit);
2951
2952	MODULE_LICENSE("BSD");
2953	MODULE_AUTHOR("David McCullough <david_mccullough@mcafee.com>");
2954	MODULE_DESCRIPTION("OCF driver for hifn PCI crypto devices");
2955

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