Root/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvLib.c

1/*******************************************************************************
2Copyright (C) Marvell International Ltd. and its affiliates
3
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12********************************************************************************
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15If you received this File from Marvell and you have entered into a commercial
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19********************************************************************************
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41    * Redistributions of source code must retain the above copyright notice,
42        this list of conditions and the following disclaimer.
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52THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
53ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
54WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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56ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
57(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
58LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
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60(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
61SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
62
63*******************************************************************************/
64
65
66/* includes */
67#include "mvCommon.h"
68#include "mvCtrlEnvLib.h"
69#include "ctrlEnv/sys/mvCpuIf.h"
70
71#if defined(MV_INCLUDE_PEX)
72#include "pex/mvPex.h"
73#include "ctrlEnv/sys/mvSysPex.h"
74#endif
75
76#if defined(MV_INCLUDE_GIG_ETH)
77#include "ctrlEnv/sys/mvSysGbe.h"
78#endif
79
80#if defined(MV_INCLUDE_XOR)
81#include "ctrlEnv/sys/mvSysXor.h"
82#endif
83
84#if defined(MV_INCLUDE_SATA)
85#include "ctrlEnv/sys/mvSysSata.h"
86#endif
87
88#if defined(MV_INCLUDE_USB)
89#include "ctrlEnv/sys/mvSysUsb.h"
90#endif
91
92#if defined(MV_INCLUDE_AUDIO)
93#include "ctrlEnv/sys/mvSysAudio.h"
94#endif
95
96#if defined(MV_INCLUDE_CESA)
97#include "ctrlEnv/sys/mvSysCesa.h"
98#endif
99
100#if defined(MV_INCLUDE_TS)
101#include "ctrlEnv/sys/mvSysTs.h"
102#endif
103
104/* defines */
105#ifdef MV_DEBUG
106    #define DB(x) x
107#else
108    #define DB(x)
109#endif
110
111/*******************************************************************************
112* mvCtrlEnvInit - Initialize Marvell controller environment.
113*
114* DESCRIPTION:
115* This function get environment information and initialize controller
116* internal/external environment. For example
117* 1) MPP settings according to board MPP macros.
118* NOTE: It is the user responsibility to shut down all DMA channels
119* in device and disable controller sub units interrupts during
120* boot process.
121*
122* INPUT:
123* None.
124*
125* OUTPUT:
126* None.
127*
128* RETURN:
129* None.
130*
131*******************************************************************************/
132MV_STATUS mvCtrlEnvInit(MV_VOID)
133{
134        MV_U32 mppGroup;
135    MV_U32 devId;
136    MV_U32 boardId;
137    MV_U32 i;
138    MV_U32 maxMppGrp = 1;
139    MV_U32 mppVal = 0;
140    MV_U32 bootVal = 0;
141    MV_U32 mppGroupType = 0;
142    MV_U32 mppGroup1[][3] = MPP_GROUP_1_TYPE;
143    MV_U32 mppGroup2[][3] = MPP_GROUP_2_TYPE;
144
145    devId = mvCtrlModelGet();
146    boardId= mvBoardIdGet();
147
148    switch(devId){
149        case MV_6281_DEV_ID:
150            maxMppGrp = MV_6281_MPP_MAX_GROUP;
151            break;
152        case MV_6192_DEV_ID:
153            maxMppGrp = MV_6192_MPP_MAX_GROUP;
154            break;
155        case MV_6190_DEV_ID:
156            maxMppGrp = MV_6190_MPP_MAX_GROUP;
157            break;
158        case MV_6180_DEV_ID:
159            maxMppGrp = MV_6180_MPP_MAX_GROUP;
160            break;
161    }
162    
163    /* MPP Init */
164    /* We split mpp init to 3 phases:
165     * 1. We init mpp[19:0] from the board info. mpp[23:20] will be over write
166     * in phase 2.
167     * 2. We detect the mpp group type and according the mpp values [35:20].
168     * 3. We detect the mpp group type and according the mpp values [49:36].
169     */
170    /* Mpp phase 1 mpp[19:0] */
171    /* Read MPP group from board level and assign to MPP register */
172    for (mppGroup = 0; mppGroup < 3; mppGroup++)
173    {
174        mppVal = mvBoardMppGet(mppGroup);
175        if (mppGroup == 0)
176        {
177            bootVal = MV_REG_READ(mvCtrlMppRegGet(mppGroup));
178            if (mvCtrlIsBootFromSPI())
179            {
180            mppVal &= ~0xffff;
181            bootVal &= 0xffff;
182            mppVal |= bootVal;
183            }
184            else if (mvCtrlIsBootFromSPIUseNAND())
185            {
186            mppVal &= ~0xf0000000;
187            bootVal &= 0xf0000000;
188            mppVal |= bootVal;
189            }
190            else if (mvCtrlIsBootFromNAND())
191            {
192            mppVal &= ~0xffffff;
193            bootVal &= 0xffffff;
194            mppVal |= bootVal;
195            }
196        }
197        
198        if (mppGroup == 2)
199        {
200            bootVal = MV_REG_READ(mvCtrlMppRegGet(mppGroup));
201            if (mvCtrlIsBootFromNAND())
202            {
203            mppVal &= ~0xff00;
204            bootVal &= 0xff00;
205            mppVal |= bootVal;
206            }
207        }
208
209        MV_REG_WRITE(mvCtrlMppRegGet(mppGroup), mppVal);
210    }
211
212    /* Identify MPPs group */
213    mvBoardMppGroupIdUpdate();
214
215    /* Update MPPs mux relevent only on Marvell DB */
216    if ((boardId == DB_88F6281A_BP_ID) ||
217        (boardId == DB_88F6180A_BP_ID))
218        mvBoardMppMuxSet();
219
220    mppGroupType = mvBoardMppGroupTypeGet(MV_BOARD_MPP_GROUP_1);
221
222    /* Mpp phase 2 */
223    /* Read MPP group from board level and assign to MPP register */
224    if (devId != MV_6180_DEV_ID)
225    {
226        i = 0;
227        for (mppGroup = 2; mppGroup < 5; mppGroup++)
228        {
229            if ((mppGroupType == MV_BOARD_OTHER) ||
230                (boardId == RD_88F6281A_ID) ||
231                (boardId == RD_88F6192A_ID) ||
232                (boardId == RD_88F6190A_ID) ||
233                (boardId == RD_88F6281A_PCAC_ID) ||
234                (boardId == SHEEVA_PLUG_ID))
235                mppVal = mvBoardMppGet(mppGroup);
236            else
237            {
238                mppVal = mppGroup1[mppGroupType][i];
239                i++;
240            }
241    
242            /* Group 2 is shared mpp[23:16] */
243            if (mppGroup == 2)
244            {
245                bootVal = MV_REG_READ(mvCtrlMppRegGet(mppGroup));
246                mppVal &= ~0xffff;
247                bootVal &= 0xffff;
248                mppVal |= bootVal;
249            }
250    
251            MV_REG_WRITE(mvCtrlMppRegGet(mppGroup), mppVal);
252        }
253    }
254
255    if ((devId == MV_6192_DEV_ID) || (devId == MV_6190_DEV_ID))
256        return MV_OK;
257     
258    /* Mpp phase 3 */
259    mppGroupType = mvBoardMppGroupTypeGet(MV_BOARD_MPP_GROUP_2);
260    /* Read MPP group from board level and assign to MPP register */
261    i = 0;
262    for (mppGroup = 4; mppGroup < 7; mppGroup++)
263    {
264        if ((mppGroupType == MV_BOARD_OTHER) ||
265            (boardId == RD_88F6281A_ID) ||
266            (boardId == RD_88F6281A_PCAC_ID) ||
267            (boardId == SHEEVA_PLUG_ID))
268            mppVal = mvBoardMppGet(mppGroup);
269        else
270        {
271            mppVal = mppGroup2[mppGroupType][i];
272            i++;
273        }
274
275        /* Group 4 is shared mpp[35:32] */
276        if (mppGroup == 4)
277        {
278            bootVal = MV_REG_READ(mvCtrlMppRegGet(mppGroup));
279            mppVal &= ~0xffff;
280            bootVal &= 0xffff;
281            mppVal |= bootVal;
282        }
283
284        MV_REG_WRITE(mvCtrlMppRegGet(mppGroup), mppVal);
285    }
286    /* Update SSCG configuration register*/
287    if(mvBoardIdGet() == DB_88F6281A_BP_ID || mvBoardIdGet() == DB_88F6192A_BP_ID ||
288       mvBoardIdGet() == DB_88F6190A_BP_ID || mvBoardIdGet() == DB_88F6180A_BP_ID)
289        MV_REG_WRITE(0x100d8, 0x53);
290
291    return MV_OK;
292}
293
294/*******************************************************************************
295* mvCtrlMppRegGet - return reg address of mpp group
296*
297* DESCRIPTION:
298*
299* INPUT:
300* mppGroup - MPP group.
301*
302* OUTPUT:
303* None.
304*
305* RETURN:
306* MV_U32 - Register address.
307*
308*******************************************************************************/
309MV_U32 mvCtrlMppRegGet(MV_U32 mppGroup)
310{
311        MV_U32 ret;
312
313        switch(mppGroup){
314                case (0): ret = MPP_CONTROL_REG0;
315                                break;
316                case (1): ret = MPP_CONTROL_REG1;
317                                break;
318                case (2): ret = MPP_CONTROL_REG2;
319                                break;
320                case (3): ret = MPP_CONTROL_REG3;
321                                break;
322                case (4): ret = MPP_CONTROL_REG4;
323                                break;
324                case (5): ret = MPP_CONTROL_REG5;
325                                break;
326                case (6): ret = MPP_CONTROL_REG6;
327                                break;
328                default: ret = MPP_CONTROL_REG0;
329                                break;
330        }
331        return ret;
332}
333#if defined(MV_INCLUDE_PEX)
334/*******************************************************************************
335* mvCtrlPexMaxIfGet - Get Marvell controller number of PEX interfaces.
336*
337* DESCRIPTION:
338* This function returns Marvell controller number of PEX interfaces.
339*
340* INPUT:
341* None.
342*
343* OUTPUT:
344* None.
345*
346* RETURN:
347* Marvell controller number of PEX interfaces. If controller
348* ID is undefined the function returns '0'.
349*
350*******************************************************************************/
351MV_U32 mvCtrlPexMaxIfGet(MV_VOID)
352{
353
354    return MV_PEX_MAX_IF;
355}
356#endif
357
358#if defined(MV_INCLUDE_GIG_ETH)
359/*******************************************************************************
360* mvCtrlEthMaxPortGet - Get Marvell controller number of etherent ports.
361*
362* DESCRIPTION:
363* This function returns Marvell controller number of etherent port.
364*
365* INPUT:
366* None.
367*
368* OUTPUT:
369* None.
370*
371* RETURN:
372* Marvell controller number of etherent port.
373*
374*******************************************************************************/
375MV_U32 mvCtrlEthMaxPortGet(MV_VOID)
376{
377    MV_U32 devId;
378    
379    devId = mvCtrlModelGet();
380
381    switch(devId){
382        case MV_6281_DEV_ID:
383            return MV_6281_ETH_MAX_PORTS;
384            break;
385        case MV_6192_DEV_ID:
386            return MV_6192_ETH_MAX_PORTS;
387            break;
388        case MV_6190_DEV_ID:
389            return MV_6190_ETH_MAX_PORTS;
390            break;
391        case MV_6180_DEV_ID:
392            return MV_6180_ETH_MAX_PORTS;
393            break;
394    }
395    return 0;
396
397}
398#endif
399
400#if defined(MV_INCLUDE_XOR)
401/*******************************************************************************
402* mvCtrlXorMaxChanGet - Get Marvell controller number of XOR channels.
403*
404* DESCRIPTION:
405* This function returns Marvell controller number of XOR channels.
406*
407* INPUT:
408* None.
409*
410* OUTPUT:
411* None.
412*
413* RETURN:
414* Marvell controller number of XOR channels.
415*
416*******************************************************************************/
417MV_U32 mvCtrlXorMaxChanGet(MV_VOID)
418{
419    return MV_XOR_MAX_CHAN;
420}
421#endif
422
423#if defined(MV_INCLUDE_USB)
424/*******************************************************************************
425* mvCtrlUsbHostMaxGet - Get number of Marvell Usb controllers
426*
427* DESCRIPTION:
428*
429* INPUT:
430* None.
431*
432* OUTPUT:
433* None.
434*
435* RETURN:
436* returns number of Marvell USB controllers.
437*
438*******************************************************************************/
439MV_U32 mvCtrlUsbMaxGet(void)
440{
441    return MV_USB_MAX_PORTS;
442}
443#endif
444
445
446#if defined(MV_INCLUDE_NAND)
447/*******************************************************************************
448* mvCtrlNandSupport - Return if this controller has integrated NAND flash support
449*
450* DESCRIPTION:
451*
452* INPUT:
453* None.
454*
455* OUTPUT:
456* None.
457*
458* RETURN:
459* MV_TRUE if NAND is supported and MV_FALSE otherwise
460*
461*******************************************************************************/
462MV_U32 mvCtrlNandSupport(MV_VOID)
463{
464    MV_U32 devId;
465    
466    devId = mvCtrlModelGet();
467
468    switch(devId){
469        case MV_6281_DEV_ID:
470            return MV_6281_NAND;
471            break;
472        case MV_6192_DEV_ID:
473            return MV_6192_NAND;
474            break;
475        case MV_6190_DEV_ID:
476            return MV_6190_NAND;
477            break;
478        case MV_6180_DEV_ID:
479            return MV_6180_NAND;
480            break;
481    }
482    return 0;
483
484}
485#endif
486
487#if defined(MV_INCLUDE_SDIO)
488/*******************************************************************************
489* mvCtrlSdioSupport - Return if this controller has integrated SDIO flash support
490*
491* DESCRIPTION:
492*
493* INPUT:
494* None.
495*
496* OUTPUT:
497* None.
498*
499* RETURN:
500* MV_TRUE if SDIO is supported and MV_FALSE otherwise
501*
502*******************************************************************************/
503MV_U32 mvCtrlSdioSupport(MV_VOID)
504{
505    MV_U32 devId;
506    
507    devId = mvCtrlModelGet();
508
509    switch(devId){
510        case MV_6281_DEV_ID:
511            return MV_6281_SDIO;
512            break;
513        case MV_6192_DEV_ID:
514            return MV_6192_SDIO;
515            break;
516        case MV_6190_DEV_ID:
517            return MV_6190_SDIO;
518            break;
519        case MV_6180_DEV_ID:
520            return MV_6180_SDIO;
521            break;
522    }
523    return 0;
524
525}
526#endif
527
528#if defined(MV_INCLUDE_TS)
529/*******************************************************************************
530* mvCtrlTsSupport - Return if this controller has integrated TS flash support
531*
532* DESCRIPTION:
533*
534* INPUT:
535* None.
536*
537* OUTPUT:
538* None.
539*
540* RETURN:
541* MV_TRUE if TS is supported and MV_FALSE otherwise
542*
543*******************************************************************************/
544MV_U32 mvCtrlTsSupport(MV_VOID)
545{
546    MV_U32 devId;
547    
548    devId = mvCtrlModelGet();
549
550    switch(devId){
551        case MV_6281_DEV_ID:
552            return MV_6281_TS;
553            break;
554        case MV_6192_DEV_ID:
555            return MV_6192_TS;
556            break;
557        case MV_6190_DEV_ID:
558            return MV_6190_TS;
559            break;
560        case MV_6180_DEV_ID:
561            return MV_6180_TS;
562            break;
563    }
564    return 0;
565}
566#endif
567
568#if defined(MV_INCLUDE_AUDIO)
569/*******************************************************************************
570* mvCtrlAudioSupport - Return if this controller has integrated AUDIO flash support
571*
572* DESCRIPTION:
573*
574* INPUT:
575* None.
576*
577* OUTPUT:
578* None.
579*
580* RETURN:
581* MV_TRUE if AUDIO is supported and MV_FALSE otherwise
582*
583*******************************************************************************/
584MV_U32 mvCtrlAudioSupport(MV_VOID)
585{
586    MV_U32 devId;
587    
588    devId = mvCtrlModelGet();
589
590    switch(devId){
591        case MV_6281_DEV_ID:
592            return MV_6281_AUDIO;
593            break;
594        case MV_6192_DEV_ID:
595            return MV_6192_AUDIO;
596            break;
597        case MV_6190_DEV_ID:
598            return MV_6190_AUDIO;
599            break;
600        case MV_6180_DEV_ID:
601            return MV_6180_AUDIO;
602            break;
603    }
604    return 0;
605
606}
607#endif
608
609#if defined(MV_INCLUDE_TDM)
610/*******************************************************************************
611* mvCtrlTdmSupport - Return if this controller has integrated TDM flash support
612*
613* DESCRIPTION:
614*
615* INPUT:
616* None.
617*
618* OUTPUT:
619* None.
620*
621* RETURN:
622* MV_TRUE if TDM is supported and MV_FALSE otherwise
623*
624*******************************************************************************/
625MV_U32 mvCtrlTdmSupport(MV_VOID)
626{
627    MV_U32 devId;
628    
629    devId = mvCtrlModelGet();
630
631    switch(devId){
632        case MV_6281_DEV_ID:
633            return MV_6281_TDM;
634            break;
635        case MV_6192_DEV_ID:
636            return MV_6192_TDM;
637            break;
638        case MV_6190_DEV_ID:
639            return MV_6190_TDM;
640            break;
641        case MV_6180_DEV_ID:
642            return MV_6180_TDM;
643            break;
644    }
645    return 0;
646
647}
648#endif
649
650/*******************************************************************************
651* mvCtrlModelGet - Get Marvell controller device model (Id)
652*
653* DESCRIPTION:
654* This function returns 16bit describing the device model (ID) as defined
655* in PCI Device and Vendor ID configuration register offset 0x0.
656*
657* INPUT:
658* None.
659*
660* OUTPUT:
661* None.
662*
663* RETURN:
664* 16bit desscribing Marvell controller ID
665*
666*******************************************************************************/
667MV_U16 mvCtrlModelGet(MV_VOID)
668{
669    MV_U32 devId;
670    
671    devId = MV_REG_READ(CHIP_BOND_REG);
672    devId &= PCKG_OPT_MASK;
673
674    switch(devId){
675        case 2:
676            return MV_6281_DEV_ID;
677            break;
678    case 1:
679            if (((MV_REG_READ(PEX_CFG_DIRECT_ACCESS(0,PEX_DEVICE_AND_VENDOR_ID))& 0xffff0000) >> 16)
680                 == MV_6190_DEV_ID)
681                return MV_6190_DEV_ID;
682            else
683                return MV_6192_DEV_ID;
684            break;
685        case 0:
686            return MV_6180_DEV_ID;
687            break;
688    }
689
690    return 0;
691}
692/*******************************************************************************
693* mvCtrlRevGet - Get Marvell controller device revision number
694*
695* DESCRIPTION:
696* This function returns 8bit describing the device revision as defined
697* in PCI Express Class Code and Revision ID Register.
698*
699* INPUT:
700* None.
701*
702* OUTPUT:
703* None.
704*
705* RETURN:
706* 8bit desscribing Marvell controller revision number
707*
708*******************************************************************************/
709MV_U8 mvCtrlRevGet(MV_VOID)
710{
711    MV_U8 revNum;
712#if defined(MV_INCLUDE_CLK_PWR_CNTRL)
713    /* Check pex power state */
714    MV_U32 pexPower;
715    pexPower = mvCtrlPwrClckGet(PEX_UNIT_ID,0);
716    if (pexPower == MV_FALSE)
717        mvCtrlPwrClckSet(PEX_UNIT_ID, 0, MV_TRUE);
718#endif
719    revNum = (MV_U8)MV_REG_READ(PEX_CFG_DIRECT_ACCESS(0,PCI_CLASS_CODE_AND_REVISION_ID));
720#if defined(MV_INCLUDE_CLK_PWR_CNTRL)
721    /* Return to power off state */
722    if (pexPower == MV_FALSE)
723        mvCtrlPwrClckSet(PEX_UNIT_ID, 0, MV_FALSE);
724#endif
725    return ((revNum & PCCRIR_REVID_MASK) >> PCCRIR_REVID_OFFS);
726}
727
728/*******************************************************************************
729* mvCtrlNameGet - Get Marvell controller name
730*
731* DESCRIPTION:
732* This function returns a string describing the device model and revision.
733*
734* INPUT:
735* None.
736*
737* OUTPUT:
738* pNameBuff - Buffer to contain device name string. Minimum size 30 chars.
739*
740* RETURN:
741*
742* MV_ERROR if informantion can not be read.
743*******************************************************************************/
744MV_STATUS mvCtrlNameGet(char *pNameBuff)
745{
746    mvOsSPrintf (pNameBuff, "%s%x Rev %d", SOC_NAME_PREFIX,
747                mvCtrlModelGet(), mvCtrlRevGet());
748    
749    return MV_OK;
750}
751
752/*******************************************************************************
753* mvCtrlModelRevGet - Get Controller Model (Device ID) and Revision
754*
755* DESCRIPTION:
756* This function returns 32bit value describing both Device ID and Revision
757* as defined in PCI Express Device and Vendor ID Register and device revision
758* as defined in PCI Express Class Code and Revision ID Register.
759     
760*
761* INPUT:
762* None.
763*
764* OUTPUT:
765* None.
766*
767* RETURN:
768* 32bit describing both controller device ID and revision number
769*
770*******************************************************************************/
771MV_U32 mvCtrlModelRevGet(MV_VOID)
772{
773    return ((mvCtrlModelGet() << 16) | mvCtrlRevGet());
774}
775
776/*******************************************************************************
777* mvCtrlModelRevNameGet - Get Marvell controller name
778*
779* DESCRIPTION:
780* This function returns a string describing the device model and revision.
781*
782* INPUT:
783* None.
784*
785* OUTPUT:
786* pNameBuff - Buffer to contain device name string. Minimum size 30 chars.
787*
788* RETURN:
789*
790* MV_ERROR if informantion can not be read.
791*******************************************************************************/
792
793MV_STATUS mvCtrlModelRevNameGet(char *pNameBuff)
794{
795
796        switch (mvCtrlModelRevGet())
797        {
798        case MV_6281_A0_ID:
799                mvOsSPrintf (pNameBuff, "%s",MV_6281_A0_NAME);
800                break;
801        case MV_6192_A0_ID:
802                mvOsSPrintf (pNameBuff, "%s",MV_6192_A0_NAME);
803                break;
804        case MV_6180_A0_ID:
805                mvOsSPrintf (pNameBuff, "%s",MV_6180_A0_NAME);
806                break;
807        case MV_6190_A0_ID:
808                mvOsSPrintf (pNameBuff, "%s",MV_6190_A0_NAME);
809                break;
810        case MV_6281_A1_ID:
811                mvOsSPrintf (pNameBuff, "%s",MV_6281_A1_NAME);
812                break;
813        case MV_6192_A1_ID:
814                mvOsSPrintf (pNameBuff, "%s",MV_6192_A1_NAME);
815                break;
816        case MV_6180_A1_ID:
817                mvOsSPrintf (pNameBuff, "%s",MV_6180_A1_NAME);
818                break;
819        case MV_6190_A1_ID:
820                mvOsSPrintf (pNameBuff, "%s",MV_6190_A1_NAME);
821                break;
822        default:
823                mvCtrlNameGet(pNameBuff);
824                break;
825        }
826
827        return MV_OK;
828}
829
830
831/*******************************************************************************
832* ctrlWinOverlapTest - Test address windows for overlaping.
833*
834* DESCRIPTION:
835* This function checks the given two address windows for overlaping.
836*
837* INPUT:
838* pAddrWin1 - Address window 1.
839* pAddrWin2 - Address window 2.
840*
841* OUTPUT:
842* None.
843*
844* RETURN:
845*
846* MV_TRUE if address window overlaps, MV_FALSE otherwise.
847*******************************************************************************/
848MV_STATUS ctrlWinOverlapTest(MV_ADDR_WIN *pAddrWin1, MV_ADDR_WIN *pAddrWin2)
849{
850    MV_U32 winBase1, winBase2;
851    MV_U32 winTop1, winTop2;
852    
853    /* check if we have overflow than 4G*/
854    if (((0xffffffff - pAddrWin1->baseLow) < pAddrWin1->size-1)||
855       ((0xffffffff - pAddrWin2->baseLow) < pAddrWin2->size-1))
856    {
857        return MV_TRUE;
858    }
859
860    winBase1 = pAddrWin1->baseLow;
861    winBase2 = pAddrWin2->baseLow;
862    winTop1 = winBase1 + pAddrWin1->size-1;
863    winTop2 = winBase2 + pAddrWin2->size-1;
864
865    
866    if (((winBase1 <= winTop2 ) && ( winTop2 <= winTop1)) ||
867        ((winBase1 <= winBase2) && (winBase2 <= winTop1)))
868    {
869        return MV_TRUE;
870    }
871    else
872    {
873        return MV_FALSE;
874    }
875}
876
877/*******************************************************************************
878* ctrlWinWithinWinTest - Test address windows for overlaping.
879*
880* DESCRIPTION:
881* This function checks the given win1 boundries is within
882* win2 boundries.
883*
884* INPUT:
885* pAddrWin1 - Address window 1.
886* pAddrWin2 - Address window 2.
887*
888* OUTPUT:
889* None.
890*
891* RETURN:
892*
893* MV_TRUE if found win1 inside win2, MV_FALSE otherwise.
894*******************************************************************************/
895MV_STATUS ctrlWinWithinWinTest(MV_ADDR_WIN *pAddrWin1, MV_ADDR_WIN *pAddrWin2)
896{
897    MV_U32 winBase1, winBase2;
898    MV_U32 winTop1, winTop2;
899    
900    winBase1 = pAddrWin1->baseLow;
901    winBase2 = pAddrWin2->baseLow;
902    winTop1 = winBase1 + pAddrWin1->size -1;
903    winTop2 = winBase2 + pAddrWin2->size -1;
904    
905    if (((winBase1 >= winBase2 ) && ( winBase1 <= winTop2)) ||
906        ((winTop1 >= winBase2) && (winTop1 <= winTop2)))
907    {
908        return MV_TRUE;
909    }
910    else
911    {
912        return MV_FALSE;
913    }
914}
915
916static const char* cntrlName[] = TARGETS_NAME_ARRAY;
917
918/*******************************************************************************
919* mvCtrlTargetNameGet - Get Marvell controller target name
920*
921* DESCRIPTION:
922* This function convert the trget enumeration to string.
923*
924* INPUT:
925* None.
926*
927* OUTPUT:
928* None.
929*
930* RETURN:
931* Target name (const MV_8 *)
932*******************************************************************************/
933const MV_8* mvCtrlTargetNameGet( MV_TARGET target )
934{
935
936    if (target >= MAX_TARGETS)
937    {
938        return "target unknown";
939    }
940
941    return cntrlName[target];
942}
943
944/*******************************************************************************
945* mvCtrlAddrDecShow - Print the Controller units address decode map.
946*
947* DESCRIPTION:
948* This function the Controller units address decode map.
949*
950* INPUT:
951* None.
952*
953* OUTPUT:
954* None.
955*
956* RETURN:
957* None.
958*
959*******************************************************************************/
960MV_VOID mvCtrlAddrDecShow(MV_VOID)
961{
962    mvCpuIfAddDecShow();
963    mvAhbToMbusAddDecShow();
964#if defined(MV_INCLUDE_PEX)
965    mvPexAddrDecShow();
966#endif
967#if defined(MV_INCLUDE_USB)
968        mvUsbAddrDecShow();
969#endif
970#if defined(MV_INCLUDE_GIG_ETH)
971    mvEthAddrDecShow();
972#endif
973#if defined(MV_INCLUDE_XOR)
974    mvXorAddrDecShow();
975#endif
976#if defined(MV_INCLUDE_SATA)
977    mvSataAddrDecShow();
978#endif
979#if defined(MV_INCLUDE_AUDIO)
980    mvAudioAddrDecShow();
981#endif
982#if defined(MV_INCLUDE_TS)
983    mvTsuAddrDecShow();
984#endif
985}
986
987/*******************************************************************************
988* ctrlSizeToReg - Extract size value for register assignment.
989*
990* DESCRIPTION:
991* Address decode size parameter must be programed from LSB to MSB as
992* sequence of 1's followed by sequence of 0's. The number of 1's
993* specifies the size of the window in 64 KB granularity (e.g. a
994* value of 0x00ff specifies 256x64k = 16 MB).
995* This function extract the size value from the size parameter according
996* to given aligment paramter. For example for size 0x1000000 (16MB) and
997* aligment 0x10000 (64KB) the function will return 0x00FF.
998*
999* INPUT:
1000* size - Size.
1001* alignment - Size alignment. Note that alignment must be power of 2!
1002*
1003* OUTPUT:
1004* None.
1005*
1006* RETURN:
1007* 32bit describing size register value correspond to size parameter.
1008* If value is '-1' size parameter or aligment are invalid.
1009*******************************************************************************/
1010MV_U32 ctrlSizeToReg(MV_U32 size, MV_U32 alignment)
1011{
1012    MV_U32 retVal;
1013
1014    /* Check size parameter alignment */
1015    if ((0 == size) || (MV_IS_NOT_ALIGN(size, alignment)))
1016    {
1017        DB(mvOsPrintf("ctrlSizeToReg: ERR. Size is zero or not aligned.\n"));
1018        return -1;
1019    }
1020    
1021    /* Take out the "alignment" portion out of the size parameter */
1022    alignment--; /* Now the alignmet is a sequance of '1' (e.g. 0xffff) */
1023                    /* and size is 0x1000000 (16MB) for example */
1024    while(alignment & 1) /* Check that alignmet LSB is set */
1025    {
1026        size = (size >> 1); /* If LSB is set, move 'size' one bit to right */
1027        alignment = (alignment >> 1);
1028    }
1029    
1030    /* If after the alignment first '0' was met we still have '1' in */
1031    /* it then aligment is invalid (not power of 2) */
1032    if (alignment)
1033    {
1034        DB(mvOsPrintf("ctrlSizeToReg: ERR. Alignment parameter 0x%x invalid.\n",
1035            (MV_U32)alignment));
1036        return -1;
1037    }
1038
1039    /* Now the size is shifted right according to aligment: 0x0100 */
1040    size--; /* Now the size is a sequance of '1': 0x00ff */
1041    
1042    retVal = size ;
1043    
1044    /* Check that LSB to MSB is sequence of 1's followed by sequence of 0's */
1045    while(size & 1) /* Check that LSB is set */
1046    {
1047        size = (size >> 1); /* If LSB is set, move one bit to the right */
1048    }
1049
1050    if (size) /* Sequance of 1's is over. Check that we have no other 1's */
1051    {
1052        DB(mvOsPrintf("ctrlSizeToReg: ERR. Size parameter 0x%x invalid.\n",
1053                                                                        size));
1054        return -1;
1055    }
1056    
1057    return retVal;
1058    
1059}
1060
1061/*******************************************************************************
1062* ctrlRegToSize - Extract size value from register value.
1063*
1064* DESCRIPTION:
1065* This function extract a size value from the register size parameter
1066* according to given aligment paramter. For example for register size
1067* value 0xff and aligment 0x10000 the function will return 0x01000000.
1068*
1069* INPUT:
1070* regSize - Size as in register format. See ctrlSizeToReg.
1071* alignment - Size alignment. Note that alignment must be power of 2!
1072*
1073* OUTPUT:
1074* None.
1075*
1076* RETURN:
1077* 32bit describing size.
1078* If value is '-1' size parameter or aligment are invalid.
1079*******************************************************************************/
1080MV_U32 ctrlRegToSize(MV_U32 regSize, MV_U32 alignment)
1081{
1082       MV_U32 temp;
1083
1084    /* Check that LSB to MSB is sequence of 1's followed by sequence of 0's */
1085    temp = regSize; /* Now the size is a sequance of '1': 0x00ff */
1086    
1087    while(temp & 1) /* Check that LSB is set */
1088    {
1089        temp = (temp >> 1); /* If LSB is set, move one bit to the right */
1090    }
1091
1092    if (temp) /* Sequance of 1's is over. Check that we have no other 1's */
1093    {
1094        DB(mvOsPrintf("ctrlRegToSize: ERR. Size parameter 0x%x invalid.\n",
1095                    regSize));
1096           return -1;
1097    }
1098    
1099
1100    /* Check that aligment is a power of two */
1101    temp = alignment - 1;/* Now the alignmet is a sequance of '1' (0xffff) */
1102                    
1103    while(temp & 1) /* Check that alignmet LSB is set */
1104    {
1105        temp = (temp >> 1); /* If LSB is set, move 'size' one bit to right */
1106    }
1107    
1108    /* If after the 'temp' first '0' was met we still have '1' in 'temp' */
1109    /* then 'temp' is invalid (not power of 2) */
1110    if (temp)
1111    {
1112        DB(mvOsPrintf("ctrlSizeToReg: ERR. Alignment parameter 0x%x invalid.\n",
1113                    alignment));
1114        return -1;
1115    }
1116
1117    regSize++; /* Now the size is 0x0100 */
1118
1119    /* Add in the "alignment" portion to the register size parameter */
1120    alignment--; /* Now the alignmet is a sequance of '1' (e.g. 0xffff) */
1121
1122    while(alignment & 1) /* Check that alignmet LSB is set */
1123    {
1124        regSize = (regSize << 1); /* LSB is set, move 'size' one bit left */
1125        alignment = (alignment >> 1);
1126    }
1127        
1128    return regSize;
1129}
1130
1131
1132/*******************************************************************************
1133* ctrlSizeRegRoundUp - Round up given size
1134*
1135* DESCRIPTION:
1136* This function round up a given size to a size that fits the
1137* restrictions of size format given an aligment parameter.
1138* to given aligment paramter. For example for size parameter 0xa1000 and
1139* aligment 0x1000 the function will return 0xFF000.
1140*
1141* INPUT:
1142* size - Size.
1143* alignment - Size alignment. Note that alignment must be power of 2!
1144*
1145* OUTPUT:
1146* None.
1147*
1148* RETURN:
1149* 32bit describing size value correspond to size in register.
1150*******************************************************************************/
1151MV_U32 ctrlSizeRegRoundUp(MV_U32 size, MV_U32 alignment)
1152{
1153    MV_U32 msbBit = 0;
1154    MV_U32 retSize;
1155    
1156    /* Check if size parameter is already comply with restriction */
1157    if (!(-1 == ctrlSizeToReg(size, alignment)))
1158    {
1159        return size;
1160    }
1161    
1162    while(size)
1163    {
1164        size = (size >> 1);
1165        msbBit++;
1166    }
1167
1168    retSize = (1 << msbBit);
1169    
1170    if (retSize < alignment)
1171    {
1172        return alignment;
1173    }
1174    else
1175    {
1176        return retSize;
1177    }
1178}
1179/*******************************************************************************
1180* mvCtrlSysRstLengthCounterGet - Return number of milliseconds the reset button
1181* was pressed and clear counter
1182*
1183* DESCRIPTION:
1184*
1185* INPUT:
1186*
1187* OUTPUT:
1188*
1189* RETURN: number of milliseconds the reset button was pressed
1190*******************************************************************************/
1191MV_U32 mvCtrlSysRstLengthCounterGet(MV_VOID)
1192{
1193    static volatile MV_U32 Count = 0;
1194
1195    if(!Count) {
1196        Count = (MV_REG_READ(SYSRST_LENGTH_COUNTER_REG) & SLCR_COUNT_MASK);
1197        Count = (Count / (MV_BOARD_REFCLK_25MHZ / 1000));
1198        /* clear counter for next boot */
1199        MV_REG_BIT_SET(SYSRST_LENGTH_COUNTER_REG, SLCR_CLR_MASK);
1200    }
1201
1202    DB(mvOsPrintf("mvCtrlSysRstLengthCounterGet: Reset button was pressed for %u milliseconds\n", Count));
1203
1204    return Count;
1205}
1206
1207MV_BOOL mvCtrlIsBootFromSPI(MV_VOID)
1208{
1209    MV_U32 satr = 0;
1210    satr = MV_REG_READ(MPP_SAMPLE_AT_RESET);
1211    if(mvCtrlModelGet() == MV_6180_DEV_ID)
1212    {
1213        if (MSAR_BOOT_MODE_6180(satr) == MSAR_BOOT_SPI_WITH_BOOTROM_6180)
1214            return MV_TRUE;
1215        else
1216            return MV_FALSE;
1217    }
1218    satr = satr & MSAR_BOOT_MODE_MASK;
1219    if (satr == MSAR_BOOT_SPI_WITH_BOOTROM)
1220        return MV_TRUE;
1221    else
1222        return MV_FALSE;
1223}
1224
1225MV_BOOL mvCtrlIsBootFromSPIUseNAND(MV_VOID)
1226{
1227    MV_U32 satr = 0;
1228    if(mvCtrlModelGet() == MV_6180_DEV_ID)
1229        return MV_FALSE;
1230    satr = MV_REG_READ(MPP_SAMPLE_AT_RESET);
1231    satr = satr & MSAR_BOOT_MODE_MASK;
1232    
1233    if (satr == MSAR_BOOT_SPI_USE_NAND_WITH_BOOTROM)
1234        return MV_TRUE;
1235    else
1236        return MV_FALSE;
1237}
1238
1239MV_BOOL mvCtrlIsBootFromNAND(MV_VOID)
1240{
1241    MV_U32 satr = 0;
1242    satr = MV_REG_READ(MPP_SAMPLE_AT_RESET);
1243    if(mvCtrlModelGet() == MV_6180_DEV_ID)
1244    {
1245        if (MSAR_BOOT_MODE_6180(satr) == MSAR_BOOT_NAND_WITH_BOOTROM_6180)
1246            return MV_TRUE;
1247        else
1248            return MV_FALSE;
1249    }
1250    satr = satr & MSAR_BOOT_MODE_MASK;
1251    if ((satr == MSAR_BOOT_NAND_WITH_BOOTROM))
1252        return MV_TRUE;
1253    else
1254        return MV_FALSE;
1255}
1256
1257#if defined(MV_INCLUDE_CLK_PWR_CNTRL)
1258/*******************************************************************************
1259* mvCtrlPwrSaveOn - Set Power save mode
1260*
1261* DESCRIPTION:
1262*
1263* INPUT:
1264*
1265* OUTPUT:
1266*
1267* RETURN:
1268*******************************************************************************/
1269MV_VOID mvCtrlPwrSaveOn(MV_VOID)
1270{
1271    unsigned long old,temp;
1272    /* Disable int */
1273    __asm__ __volatile__("mrs %0, cpsr\n"
1274                 "orr %1, %0, #0xc0\n"
1275                 "msr cpsr_c, %1"
1276                 : "=r" (old), "=r" (temp)
1277                 :
1278                 : "memory");
1279
1280    /* Set SoC in power save */
1281    MV_REG_BIT_SET(POWER_MNG_CTRL_REG, BIT11);
1282    /* Wait for int */
1283    __asm__ __volatile__("mcr p15, 0, r0, c7, c0, 4");
1284
1285    /* Enabled int */
1286    __asm__ __volatile__("msr cpsr_c, %0"
1287                 :
1288                 : "r" (old)
1289                 : "memory");
1290}
1291
1292
1293
1294/*******************************************************************************
1295* mvCtrlPwrSaveOff - Go out of power save mode
1296*
1297* DESCRIPTION:
1298*
1299* INPUT:
1300*
1301* OUTPUT:
1302*
1303* RETURN:
1304*******************************************************************************/
1305MV_VOID mvCtrlPwrSaveOff(MV_VOID)
1306{
1307    unsigned long old,temp;
1308    /* Disable int */
1309    __asm__ __volatile__("mrs %0, cpsr\n"
1310                 "orr %1, %0, #0xc0\n"
1311                 "msr cpsr_c, %1"
1312                 : "=r" (old), "=r" (temp)
1313                 :
1314                 : "memory");
1315
1316    /* Set SoC in power save */
1317    MV_REG_BIT_RESET(POWER_MNG_CTRL_REG, BIT11);
1318    /* Wait for int */
1319    __asm__ __volatile__("mcr p15, 0, r0, c7, c0, 4");
1320
1321    /* Enabled int */
1322    __asm__ __volatile__("msr cpsr_c, %0"
1323                 :
1324                 : "r" (old)
1325                 : "memory");
1326}
1327
1328/*******************************************************************************
1329* mvCtrlPwrClckSet - Set Power State for specific Unit
1330*
1331* DESCRIPTION:
1332*
1333* INPUT:
1334*
1335* OUTPUT:
1336*
1337* RETURN:
1338*******************************************************************************/
1339MV_VOID mvCtrlPwrClckSet(MV_UNIT_ID unitId, MV_U32 index, MV_BOOL enable)
1340{
1341    switch (unitId)
1342    {
1343#if defined(MV_INCLUDE_PEX)
1344    case PEX_UNIT_ID:
1345        if (enable == MV_FALSE)
1346        {
1347            MV_REG_BIT_RESET(POWER_MNG_CTRL_REG, PMC_PEXSTOPCLOCK_MASK);
1348        }
1349        else
1350        {
1351            MV_REG_BIT_SET(POWER_MNG_CTRL_REG, PMC_PEXSTOPCLOCK_MASK);
1352        }
1353        break;
1354#endif
1355#if defined(MV_INCLUDE_GIG_ETH)
1356    case ETH_GIG_UNIT_ID:
1357        if (enable == MV_FALSE)
1358        {
1359            MV_REG_BIT_RESET(POWER_MNG_CTRL_REG, PMC_GESTOPCLOCK_MASK(index));
1360        }
1361        else
1362        {
1363            MV_REG_BIT_SET(POWER_MNG_CTRL_REG, PMC_GESTOPCLOCK_MASK(index));
1364        }
1365        break;
1366#endif
1367#if defined(MV_INCLUDE_INTEG_SATA)
1368    case SATA_UNIT_ID:
1369        if (enable == MV_FALSE)
1370        {
1371            MV_REG_BIT_RESET(POWER_MNG_CTRL_REG, PMC_SATASTOPCLOCK_MASK(index));
1372        }
1373        else
1374        {
1375            MV_REG_BIT_SET(POWER_MNG_CTRL_REG, PMC_SATASTOPCLOCK_MASK(index));
1376        }
1377        break;
1378#endif
1379#if defined(MV_INCLUDE_CESA)
1380    case CESA_UNIT_ID:
1381        if (enable == MV_FALSE)
1382        {
1383            MV_REG_BIT_RESET(POWER_MNG_CTRL_REG, PMC_SESTOPCLOCK_MASK);
1384        }
1385        else
1386        {
1387            MV_REG_BIT_SET(POWER_MNG_CTRL_REG, PMC_SESTOPCLOCK_MASK);
1388        }
1389        break;
1390#endif
1391#if defined(MV_INCLUDE_USB)
1392    case USB_UNIT_ID:
1393        if (enable == MV_FALSE)
1394        {
1395            MV_REG_BIT_RESET(POWER_MNG_CTRL_REG, PMC_USBSTOPCLOCK_MASK);
1396        }
1397        else
1398        {
1399            MV_REG_BIT_SET(POWER_MNG_CTRL_REG, PMC_USBSTOPCLOCK_MASK);
1400        }
1401        break;
1402#endif
1403#if defined(MV_INCLUDE_AUDIO)
1404    case AUDIO_UNIT_ID:
1405        if (enable == MV_FALSE)
1406        {
1407            MV_REG_BIT_RESET(POWER_MNG_CTRL_REG, PMC_AUDIOSTOPCLOCK_MASK);
1408        }
1409        else
1410        {
1411            MV_REG_BIT_SET(POWER_MNG_CTRL_REG, PMC_AUDIOSTOPCLOCK_MASK);
1412        }
1413        break;
1414#endif
1415#if defined(MV_INCLUDE_TS)
1416    case TS_UNIT_ID:
1417        if (enable == MV_FALSE)
1418        {
1419            MV_REG_BIT_RESET(POWER_MNG_CTRL_REG, PMC_TSSTOPCLOCK_MASK);
1420        }
1421        else
1422        {
1423            MV_REG_BIT_SET(POWER_MNG_CTRL_REG, PMC_TSSTOPCLOCK_MASK);
1424        }
1425        break;
1426#endif
1427#if defined(MV_INCLUDE_SDIO)
1428    case SDIO_UNIT_ID:
1429        if (enable == MV_FALSE)
1430        {
1431            MV_REG_BIT_RESET(POWER_MNG_CTRL_REG, PMC_SDIOSTOPCLOCK_MASK);
1432        }
1433        else
1434        {
1435            MV_REG_BIT_SET(POWER_MNG_CTRL_REG, PMC_SDIOSTOPCLOCK_MASK);
1436        }
1437        break;
1438#endif
1439#if defined(MV_INCLUDE_TDM)
1440    case TDM_UNIT_ID:
1441        if (enable == MV_FALSE)
1442        {
1443            MV_REG_BIT_RESET(POWER_MNG_CTRL_REG, PMC_TDMSTOPCLOCK_MASK);
1444        }
1445        else
1446        {
1447            MV_REG_BIT_SET(POWER_MNG_CTRL_REG, PMC_TDMSTOPCLOCK_MASK);
1448        }
1449        break;
1450#endif
1451
1452    default:
1453
1454        break;
1455
1456    }
1457}
1458
1459/*******************************************************************************
1460* mvCtrlPwrClckGet - Get Power State of specific Unit
1461*
1462* DESCRIPTION:
1463*
1464* INPUT:
1465*
1466* OUTPUT:
1467*
1468* RETURN:
1469******************************************************************************/
1470MV_BOOL mvCtrlPwrClckGet(MV_UNIT_ID unitId, MV_U32 index)
1471{
1472    MV_U32 reg = MV_REG_READ(POWER_MNG_CTRL_REG);
1473    MV_BOOL state = MV_TRUE;
1474
1475    switch (unitId)
1476    {
1477#if defined(MV_INCLUDE_PEX)
1478    case PEX_UNIT_ID:
1479        if ((reg & PMC_PEXSTOPCLOCK_MASK) == PMC_PEXSTOPCLOCK_STOP)
1480        {
1481            state = MV_FALSE;
1482        }
1483        else state = MV_TRUE;
1484
1485        break;
1486#endif
1487#if defined(MV_INCLUDE_GIG_ETH)
1488    case ETH_GIG_UNIT_ID:
1489        if ((reg & PMC_GESTOPCLOCK_MASK(index)) == PMC_GESTOPCLOCK_STOP(index))
1490        {
1491            state = MV_FALSE;
1492        }
1493        else state = MV_TRUE;
1494        break;
1495#endif
1496#if defined(MV_INCLUDE_SATA)
1497    case SATA_UNIT_ID:
1498        if ((reg & PMC_SATASTOPCLOCK_MASK(index)) == PMC_SATASTOPCLOCK_STOP(index))
1499        {
1500            state = MV_FALSE;
1501        }
1502        else state = MV_TRUE;
1503        break;
1504#endif
1505#if defined(MV_INCLUDE_CESA)
1506    case CESA_UNIT_ID:
1507        if ((reg & PMC_SESTOPCLOCK_MASK) == PMC_SESTOPCLOCK_STOP)
1508        {
1509            state = MV_FALSE;
1510        }
1511        else state = MV_TRUE;
1512        break;
1513#endif
1514#if defined(MV_INCLUDE_USB)
1515    case USB_UNIT_ID:
1516        if ((reg & PMC_USBSTOPCLOCK_MASK) == PMC_USBSTOPCLOCK_STOP)
1517        {
1518            state = MV_FALSE;
1519        }
1520        else state = MV_TRUE;
1521        break;
1522#endif
1523#if defined(MV_INCLUDE_AUDIO)
1524    case AUDIO_UNIT_ID:
1525        if ((reg & PMC_AUDIOSTOPCLOCK_MASK) == PMC_AUDIOSTOPCLOCK_STOP)
1526        {
1527            state = MV_FALSE;
1528        }
1529        else state = MV_TRUE;
1530        break;
1531#endif
1532#if defined(MV_INCLUDE_TS)
1533    case TS_UNIT_ID:
1534        if ((reg & PMC_TSSTOPCLOCK_MASK) == PMC_TSSTOPCLOCK_STOP)
1535        {
1536            state = MV_FALSE;
1537        }
1538        else state = MV_TRUE;
1539        break;
1540#endif
1541#if defined(MV_INCLUDE_SDIO)
1542    case SDIO_UNIT_ID:
1543        if ((reg & PMC_SDIOSTOPCLOCK_MASK)== PMC_SDIOSTOPCLOCK_STOP)
1544        {
1545            state = MV_FALSE;
1546        }
1547        else state = MV_TRUE;
1548        break;
1549#endif
1550#if defined(MV_INCLUDE_TDM)
1551    case TDM_UNIT_ID:
1552        if ((reg & PMC_TDMSTOPCLOCK_MASK) == PMC_TDMSTOPCLOCK_STOP)
1553        {
1554            state = MV_FALSE;
1555        }
1556        else state = MV_TRUE;
1557        break;
1558#endif
1559
1560    default:
1561        state = MV_TRUE;
1562        break;
1563    }
1564
1565
1566    return state;
1567}
1568/*******************************************************************************
1569* mvCtrlPwrMemSet - Set Power State for memory on specific Unit
1570*
1571* DESCRIPTION:
1572*
1573* INPUT:
1574*
1575* OUTPUT:
1576*
1577* RETURN:
1578*******************************************************************************/
1579MV_VOID mvCtrlPwrMemSet(MV_UNIT_ID unitId, MV_U32 index, MV_BOOL enable)
1580{
1581    switch (unitId)
1582    {
1583#if defined(MV_INCLUDE_PEX)
1584    case PEX_UNIT_ID:
1585        if (enable == MV_FALSE)
1586        {
1587            MV_REG_BIT_SET(POWER_MNG_MEM_CTRL_REG, PMC_PEXSTOPMEM_MASK);
1588        }
1589        else
1590        {
1591            MV_REG_BIT_RESET(POWER_MNG_MEM_CTRL_REG, PMC_PEXSTOPMEM_MASK);
1592        }
1593        break;
1594#endif
1595#if defined(MV_INCLUDE_GIG_ETH)
1596    case ETH_GIG_UNIT_ID:
1597        if (enable == MV_FALSE)
1598        {
1599            MV_REG_BIT_SET(POWER_MNG_MEM_CTRL_REG, PMC_GESTOPMEM_MASK(index));
1600        }
1601        else
1602        {
1603            MV_REG_BIT_RESET(POWER_MNG_MEM_CTRL_REG, PMC_GESTOPMEM_MASK(index));
1604        }
1605        break;
1606#endif
1607#if defined(MV_INCLUDE_INTEG_SATA)
1608    case SATA_UNIT_ID:
1609        if (enable == MV_FALSE)
1610        {
1611            MV_REG_BIT_SET(POWER_MNG_MEM_CTRL_REG, PMC_SATASTOPMEM_MASK(index));
1612        }
1613        else
1614        {
1615            MV_REG_BIT_RESET(POWER_MNG_MEM_CTRL_REG, PMC_SATASTOPMEM_MASK(index));
1616        }
1617        break;
1618#endif
1619#if defined(MV_INCLUDE_CESA)
1620    case CESA_UNIT_ID:
1621        if (enable == MV_FALSE)
1622        {
1623            MV_REG_BIT_SET(POWER_MNG_MEM_CTRL_REG, PMC_SESTOPMEM_MASK);
1624        }
1625        else
1626        {
1627            MV_REG_BIT_RESET(POWER_MNG_MEM_CTRL_REG, PMC_SESTOPMEM_MASK);
1628        }
1629        break;
1630#endif
1631#if defined(MV_INCLUDE_USB)
1632    case USB_UNIT_ID:
1633        if (enable == MV_FALSE)
1634        {
1635            MV_REG_BIT_SET(POWER_MNG_MEM_CTRL_REG, PMC_USBSTOPMEM_MASK);
1636        }
1637        else
1638        {
1639            MV_REG_BIT_RESET(POWER_MNG_MEM_CTRL_REG, PMC_USBSTOPMEM_MASK);
1640        }
1641        break;
1642#endif
1643#if defined(MV_INCLUDE_AUDIO)
1644    case AUDIO_UNIT_ID:
1645        if (enable == MV_FALSE)
1646        {
1647            MV_REG_BIT_SET(POWER_MNG_MEM_CTRL_REG, PMC_AUDIOSTOPMEM_MASK);
1648        }
1649        else
1650        {
1651            MV_REG_BIT_RESET(POWER_MNG_MEM_CTRL_REG, PMC_AUDIOSTOPMEM_MASK);
1652        }
1653        break;
1654#endif
1655#if defined(MV_INCLUDE_XOR)
1656    case XOR_UNIT_ID:
1657        if (enable == MV_FALSE)
1658        {
1659            MV_REG_BIT_SET(POWER_MNG_MEM_CTRL_REG, PMC_XORSTOPMEM_MASK(index));
1660        }
1661        else
1662        {
1663            MV_REG_BIT_RESET(POWER_MNG_MEM_CTRL_REG, PMC_XORSTOPMEM_MASK(index));
1664        }
1665        break;
1666#endif
1667    default:
1668
1669        break;
1670
1671    }
1672}
1673
1674/*******************************************************************************
1675* mvCtrlPwrMemGet - Get Power State of memory on specific Unit
1676*
1677* DESCRIPTION:
1678*
1679* INPUT:
1680*
1681* OUTPUT:
1682*
1683* RETURN:
1684******************************************************************************/
1685MV_BOOL mvCtrlPwrMemGet(MV_UNIT_ID unitId, MV_U32 index)
1686{
1687    MV_U32 reg = MV_REG_READ(POWER_MNG_MEM_CTRL_REG);
1688    MV_BOOL state = MV_TRUE;
1689
1690    switch (unitId)
1691    {
1692#if defined(MV_INCLUDE_PEX)
1693    case PEX_UNIT_ID:
1694        if ((reg & PMC_PEXSTOPMEM_MASK) == PMC_PEXSTOPMEM_STOP)
1695        {
1696            state = MV_FALSE;
1697        }
1698        else state = MV_TRUE;
1699
1700        break;
1701#endif
1702#if defined(MV_INCLUDE_GIG_ETH)
1703    case ETH_GIG_UNIT_ID:
1704        if ((reg & PMC_GESTOPMEM_MASK(index)) == PMC_GESTOPMEM_STOP(index))
1705        {
1706            state = MV_FALSE;
1707        }
1708        else state = MV_TRUE;
1709        break;
1710#endif
1711#if defined(MV_INCLUDE_SATA)
1712    case SATA_UNIT_ID:
1713        if ((reg & PMC_SATASTOPMEM_MASK(index)) == PMC_SATASTOPMEM_STOP(index))
1714        {
1715            state = MV_FALSE;
1716        }
1717        else state = MV_TRUE;
1718        break;
1719#endif
1720#if defined(MV_INCLUDE_CESA)
1721    case CESA_UNIT_ID:
1722        if ((reg & PMC_SESTOPMEM_MASK) == PMC_SESTOPMEM_STOP)
1723        {
1724            state = MV_FALSE;
1725        }
1726        else state = MV_TRUE;
1727        break;
1728#endif
1729#if defined(MV_INCLUDE_USB)
1730    case USB_UNIT_ID:
1731        if ((reg & PMC_USBSTOPMEM_MASK) == PMC_USBSTOPMEM_STOP)
1732        {
1733            state = MV_FALSE;
1734        }
1735        else state = MV_TRUE;
1736        break;
1737#endif
1738#if defined(MV_INCLUDE_AUDIO)
1739    case AUDIO_UNIT_ID:
1740        if ((reg & PMC_AUDIOSTOPMEM_MASK) == PMC_AUDIOSTOPMEM_STOP)
1741        {
1742            state = MV_FALSE;
1743        }
1744        else state = MV_TRUE;
1745        break;
1746#endif
1747#if defined(MV_INCLUDE_XOR)
1748    case XOR_UNIT_ID:
1749        if ((reg & PMC_XORSTOPMEM_MASK(index)) == PMC_XORSTOPMEM_STOP(index))
1750        {
1751            state = MV_FALSE;
1752        }
1753        else state = MV_TRUE;
1754        break;
1755#endif
1756
1757    default:
1758        state = MV_TRUE;
1759        break;
1760    }
1761
1762
1763    return state;
1764}
1765#else
1766MV_VOID mvCtrlPwrClckSet(MV_UNIT_ID unitId, MV_U32 index, MV_BOOL enable) {return;}
1767MV_BOOL mvCtrlPwrClckGet(MV_UNIT_ID unitId, MV_U32 index) {return MV_TRUE;}
1768#endif /* #if defined(MV_INCLUDE_CLK_PWR_CNTRL) */
1769
1770
1771/*******************************************************************************
1772* mvMPPConfigToSPI - Change MPP[3:0] configuration to SPI mode
1773*
1774* DESCRIPTION:
1775*
1776* INPUT:
1777*
1778* OUTPUT:
1779*
1780* RETURN:
1781******************************************************************************/
1782MV_VOID mvMPPConfigToSPI(MV_VOID)
1783{
1784    MV_U32 mppVal = 0;
1785    MV_U32 bootVal = 0;
1786
1787    if(!mvCtrlIsBootFromSPIUseNAND())
1788        return;
1789    mppVal = 0x00002220; /* Set MPP [3:1] to SPI mode */
1790    bootVal = MV_REG_READ(mvCtrlMppRegGet(0));
1791    bootVal &= 0xffff000f;
1792        mppVal |= bootVal;
1793    
1794    MV_REG_WRITE(mvCtrlMppRegGet(0), mppVal);
1795}
1796
1797
1798/*******************************************************************************
1799* mvMPPConfigToDefault - Change MPP[7:0] configuration to default configuration
1800*
1801* DESCRIPTION:
1802*
1803* INPUT:
1804*
1805* OUTPUT:
1806*
1807* RETURN:
1808******************************************************************************/
1809MV_VOID mvMPPConfigToDefault(MV_VOID)
1810{
1811    MV_U32 mppVal = 0;
1812    MV_U32 bootVal = 0;
1813
1814    if(!mvCtrlIsBootFromSPIUseNAND())
1815        return;
1816    mppVal = mvBoardMppGet(0);
1817    bootVal = MV_REG_READ(mvCtrlMppRegGet(0));
1818    mppVal &= ~0xffff000f;
1819    bootVal &= 0xffff000f;
1820        mppVal |= bootVal;
1821    
1822    MV_REG_WRITE(mvCtrlMppRegGet(0), mppVal);
1823}
1824
1825
1826

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