| 1 | /******************************************************************************* |
| 2 | Copyright (C) Marvell International Ltd. and its affiliates |
| 3 | |
| 4 | This software file (the "File") is owned and distributed by Marvell |
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| 11 | |
| 12 | ******************************************************************************** |
| 13 | Marvell Commercial License Option |
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| 15 | If you received this File from Marvell and you have entered into a commercial |
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| 18 | |
| 19 | ******************************************************************************** |
| 20 | Marvell GPL License Option |
| 21 | |
| 22 | If you received this File from Marvell, you may opt to use, redistribute and/or |
| 23 | modify this File in accordance with the terms and conditions of the General |
| 24 | Public License Version 2, June 1991 (the "GPL License"), a copy of which is |
| 25 | available along with the File in the license.txt file or by writing to the Free |
| 26 | Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or |
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| 28 | |
| 29 | THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED |
| 30 | WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY |
| 31 | DISCLAIMED. The GPL License provides additional details about this warranty |
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| 33 | ******************************************************************************** |
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| 37 | modify this File under the following licensing terms. |
| 38 | Redistribution and use in source and binary forms, with or without modification, |
| 39 | are permitted provided that the following conditions are met: |
| 40 | |
| 41 | * Redistributions of source code must retain the above copyright notice, |
| 42 | this list of conditions and the following disclaimer. |
| 43 | |
| 44 | * Redistributions in binary form must reproduce the above copyright |
| 45 | notice, this list of conditions and the following disclaimer in the |
| 46 | documentation and/or other materials provided with the distribution. |
| 47 | |
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| 50 | specific prior written permission. |
| 51 | |
| 52 | THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND |
| 53 | ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED |
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| 56 | ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES |
| 57 | (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; |
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| 60 | (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS |
| 61 | SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| 62 | |
| 63 | *******************************************************************************/ |
| 64 | |
| 65 | #ifndef __INCmvCtrlEnvRegsh |
| 66 | #define __INCmvCtrlEnvRegsh |
| 67 | |
| 68 | #ifdef __cplusplus |
| 69 | extern "C" { |
| 70 | #endif /* __cplusplus */ |
| 71 | |
| 72 | /* CV Support */ |
| 73 | #define PEX0_MEM0 PEX0_MEM |
| 74 | #define PCI0_MEM0 PEX0_MEM |
| 75 | |
| 76 | /* Controller revision info */ |
| 77 | #define PCI_CLASS_CODE_AND_REVISION_ID 0x008 |
| 78 | #define PCCRIR_REVID_OFFS 0 /* Revision ID */ |
| 79 | #define PCCRIR_REVID_MASK (0xff << PCCRIR_REVID_OFFS) |
| 80 | |
| 81 | /* Controler environment registers offsets */ |
| 82 | |
| 83 | /* Power Managment Control */ |
| 84 | #define POWER_MNG_MEM_CTRL_REG 0x20118 |
| 85 | |
| 86 | #define PMC_GESTOPMEM_OFFS(port) ((port)? 13 : 0) |
| 87 | #define PMC_GESTOPMEM_MASK(port) (1 << PMC_GESTOPMEM_OFFS(port)) |
| 88 | #define PMC_GESTOPMEM_EN(port) (0 << PMC_GESTOPMEM_OFFS(port)) |
| 89 | #define PMC_GESTOPMEM_STOP(port) (1 << PMC_GESTOPMEM_OFFS(port)) |
| 90 | |
| 91 | #define PMC_PEXSTOPMEM_OFFS 1 |
| 92 | #define PMC_PEXSTOPMEM_MASK (1 << PMC_PEXSTOPMEM_OFFS) |
| 93 | #define PMC_PEXSTOPMEM_EN (0 << PMC_PEXSTOPMEM_OFFS) |
| 94 | #define PMC_PEXSTOPMEM_STOP (1 << PMC_PEXSTOPMEM_OFFS) |
| 95 | |
| 96 | #define PMC_USBSTOPMEM_OFFS 2 |
| 97 | #define PMC_USBSTOPMEM_MASK (1 << PMC_USBSTOPMEM_OFFS) |
| 98 | #define PMC_USBSTOPMEM_EN (0 << PMC_USBSTOPMEM_OFFS) |
| 99 | #define PMC_USBSTOPMEM_STOP (1 << PMC_USBSTOPMEM_OFFS) |
| 100 | |
| 101 | #define PMC_DUNITSTOPMEM_OFFS 3 |
| 102 | #define PMC_DUNITSTOPMEM_MASK (1 << PMC_DUNITSTOPMEM_OFFS) |
| 103 | #define PMC_DUNITSTOPMEM_EN (0 << PMC_DUNITSTOPMEM_OFFS) |
| 104 | #define PMC_DUNITSTOPMEM_STOP (1 << PMC_DUNITSTOPMEM_OFFS) |
| 105 | |
| 106 | #define PMC_RUNITSTOPMEM_OFFS 4 |
| 107 | #define PMC_RUNITSTOPMEM_MASK (1 << PMC_RUNITSTOPMEM_OFFS) |
| 108 | #define PMC_RUNITSTOPMEM_EN (0 << PMC_RUNITSTOPMEM_OFFS) |
| 109 | #define PMC_RUNITSTOPMEM_STOP (1 << PMC_RUNITSTOPMEM_OFFS) |
| 110 | |
| 111 | #define PMC_XORSTOPMEM_OFFS(port) (5+(port*2)) |
| 112 | #define PMC_XORSTOPMEM_MASK(port) (1 << PMC_XORSTOPMEM_OFFS(port)) |
| 113 | #define PMC_XORSTOPMEM_EN(port) (0 << PMC_XORSTOPMEM_OFFS(port)) |
| 114 | #define PMC_XORSTOPMEM_STOP(port) (1 << PMC_XORSTOPMEM_OFFS(port)) |
| 115 | |
| 116 | #define PMC_SATASTOPMEM_OFFS(port) (6+(port*5)) |
| 117 | #define PMC_SATASTOPMEM_MASK(port) (1 << PMC_SATASTOPMEM_OFFS(port)) |
| 118 | #define PMC_SATASTOPMEM_EN(port) (0 << PMC_SATASTOPMEM_OFFS(port)) |
| 119 | #define PMC_SATASTOPMEM_STOP(port) (1 << PMC_SATASTOPMEM_OFFS(port)) |
| 120 | |
| 121 | #define PMC_SESTOPMEM_OFFS 8 |
| 122 | #define PMC_SESTOPMEM_MASK (1 << PMC_SESTOPMEM_OFFS) |
| 123 | #define PMC_SESTOPMEM_EN (0 << PMC_SESTOPMEM_OFFS) |
| 124 | #define PMC_SESTOPMEM_STOP (1 << PMC_SESTOPMEM_OFFS) |
| 125 | |
| 126 | #define PMC_AUDIOSTOPMEM_OFFS 9 |
| 127 | #define PMC_AUDIOSTOPMEM_MASK (1 << PMC_AUDIOSTOPMEM_OFFS) |
| 128 | #define PMC_AUDIOSTOPMEM_EN (0 << PMC_AUDIOSTOPMEM_OFFS) |
| 129 | #define PMC_AUDIOSTOPMEM_STOP (1 << PMC_AUDIOSTOPMEM_OFFS) |
| 130 | |
| 131 | #define POWER_MNG_CTRL_REG 0x2011C |
| 132 | |
| 133 | #define PMC_GESTOPCLOCK_OFFS(port) ((port)? 19 : 0) |
| 134 | #define PMC_GESTOPCLOCK_MASK(port) (1 << PMC_GESTOPCLOCK_OFFS(port)) |
| 135 | #define PMC_GESTOPCLOCK_EN(port) (1 << PMC_GESTOPCLOCK_OFFS(port)) |
| 136 | #define PMC_GESTOPCLOCK_STOP(port) (0 << PMC_GESTOPCLOCK_OFFS(port)) |
| 137 | |
| 138 | #define PMC_PEXPHYSTOPCLOCK_OFFS 1 |
| 139 | #define PMC_PEXPHYSTOPCLOCK_MASK (1 << PMC_PEXPHYSTOPCLOCK_OFFS) |
| 140 | #define PMC_PEXPHYSTOPCLOCK_EN (1 << PMC_PEXPHYSTOPCLOCK_OFFS) |
| 141 | #define PMC_PEXPHYSTOPCLOCK_STOP (0 << PMC_PEXPHYSTOPCLOCK_OFFS) |
| 142 | |
| 143 | #define PMC_PEXSTOPCLOCK_OFFS 2 |
| 144 | #define PMC_PEXSTOPCLOCK_MASK (1 << PMC_PEXSTOPCLOCK_OFFS) |
| 145 | #define PMC_PEXSTOPCLOCK_EN (1 << PMC_PEXSTOPCLOCK_OFFS) |
| 146 | #define PMC_PEXSTOPCLOCK_STOP (0 << PMC_PEXSTOPCLOCK_OFFS) |
| 147 | |
| 148 | #define PMC_USBSTOPCLOCK_OFFS 3 |
| 149 | #define PMC_USBSTOPCLOCK_MASK (1 << PMC_USBSTOPCLOCK_OFFS) |
| 150 | #define PMC_USBSTOPCLOCK_EN (1 << PMC_USBSTOPCLOCK_OFFS) |
| 151 | #define PMC_USBSTOPCLOCK_STOP (0 << PMC_USBSTOPCLOCK_OFFS) |
| 152 | |
| 153 | #define PMC_SDIOSTOPCLOCK_OFFS 4 |
| 154 | #define PMC_SDIOSTOPCLOCK_MASK (1 << PMC_SDIOSTOPCLOCK_OFFS) |
| 155 | #define PMC_SDIOSTOPCLOCK_EN (1 << PMC_SDIOSTOPCLOCK_OFFS) |
| 156 | #define PMC_SDIOSTOPCLOCK_STOP (0 << PMC_SDIOSTOPCLOCK_OFFS) |
| 157 | |
| 158 | #define PMC_TSSTOPCLOCK_OFFS 5 |
| 159 | #define PMC_TSSTOPCLOCK_MASK (1 << PMC_TSSTOPCLOCK_OFFS) |
| 160 | #define PMC_TSSTOPCLOCK_EN (1 << PMC_TSSTOPCLOCK_OFFS) |
| 161 | #define PMC_TSSTOPCLOCK_STOP (0 << PMC_TSSTOPCLOCK_OFFS) |
| 162 | |
| 163 | #define PMC_AUDIOSTOPCLOCK_OFFS 9 |
| 164 | #define PMC_AUDIOSTOPCLOCK_MASK (1 << PMC_AUDIOSTOPCLOCK_OFFS) |
| 165 | #define PMC_AUDIOSTOPCLOCK_EN (1 << PMC_AUDIOSTOPCLOCK_OFFS) |
| 166 | #define PMC_AUDIOSTOPCLOCK_STOP (0 << PMC_AUDIOSTOPCLOCK_OFFS) |
| 167 | |
| 168 | #define PMC_POWERSAVE_OFFS 11 |
| 169 | #define PMC_POWERSAVE_MASK (1 << PMC_POWERSAVE_OFFS) |
| 170 | #define PMC_POWERSAVE_EN (1 << PMC_POWERSAVE_OFFS) |
| 171 | #define PMC_POWERSAVE_STOP (0 << PMC_POWERSAVE_OFFS) |
| 172 | |
| 173 | |
| 174 | |
| 175 | |
| 176 | #define PMC_SATASTOPCLOCK_OFFS(port) (14+(port)) |
| 177 | #define PMC_SATASTOPCLOCK_MASK(port) (1 << PMC_SATASTOPCLOCK_OFFS(port)) |
| 178 | #define PMC_SATASTOPCLOCK_EN(port) (1 << PMC_SATASTOPCLOCK_OFFS(port)) |
| 179 | #define PMC_SATASTOPCLOCK_STOP(port) (0 << PMC_SATASTOPCLOCK_OFFS(port)) |
| 180 | |
| 181 | #define PMC_SESTOPCLOCK_OFFS 17 |
| 182 | #define PMC_SESTOPCLOCK_MASK (1 << PMC_SESTOPCLOCK_OFFS) |
| 183 | #define PMC_SESTOPCLOCK_EN (1 << PMC_SESTOPCLOCK_OFFS) |
| 184 | #define PMC_SESTOPCLOCK_STOP (0 << PMC_SESTOPCLOCK_OFFS) |
| 185 | |
| 186 | #define PMC_TDMSTOPCLOCK_OFFS 20 |
| 187 | #define PMC_TDMSTOPCLOCK_MASK (1 << PMC_TDMSTOPCLOCK_OFFS) |
| 188 | #define PMC_TDMSTOPCLOCK_EN (1 << PMC_TDMSTOPCLOCK_OFFS) |
| 189 | #define PMC_TDMSTOPCLOCK_STOP (0 << PMC_TDMSTOPCLOCK_OFFS) |
| 190 | |
| 191 | |
| 192 | /* Controler environment registers offsets */ |
| 193 | #define MPP_CONTROL_REG0 0x10000 |
| 194 | #define MPP_CONTROL_REG1 0x10004 |
| 195 | #define MPP_CONTROL_REG2 0x10008 |
| 196 | #define MPP_CONTROL_REG3 0x1000C |
| 197 | #define MPP_CONTROL_REG4 0x10010 |
| 198 | #define MPP_CONTROL_REG5 0x10014 |
| 199 | #define MPP_CONTROL_REG6 0x10018 |
| 200 | #define MPP_SAMPLE_AT_RESET 0x10030 |
| 201 | #define CHIP_BOND_REG 0x10034 |
| 202 | #define SYSRST_LENGTH_COUNTER_REG 0x10050 |
| 203 | #define SLCR_COUNT_OFFS 0 |
| 204 | #define SLCR_COUNT_MASK (0x1FFFFFFF << SLCR_COUNT_OFFS) |
| 205 | #define SLCR_CLR_OFFS 31 |
| 206 | #define SLCR_CLR_MASK (1 << SLCR_CLR_OFFS) |
| 207 | #define PCKG_OPT_MASK 0x3 |
| 208 | #define MPP_OUTPUT_DRIVE_REG 0x100E0 |
| 209 | #define MPP_RGMII0_OUTPUT_DRIVE_OFFS 7 |
| 210 | #define MPP_3_3_RGMII0_OUTPUT_DRIVE (0x0 << MPP_RGMII0_OUTPUT_DRIVE_OFFS) |
| 211 | #define MPP_1_8_RGMII0_OUTPUT_DRIVE (0x1 << MPP_RGMII0_OUTPUT_DRIVE_OFFS) |
| 212 | #define MPP_RGMII1_OUTPUT_DRIVE_OFFS 15 |
| 213 | #define MPP_3_3_RGMII1_OUTPUT_DRIVE (0x0 << MPP_RGMII1_OUTPUT_DRIVE_OFFS) |
| 214 | #define MPP_1_8_RGMII1_OUTPUT_DRIVE (0x1 << MPP_RGMII1_OUTPUT_DRIVE_OFFS) |
| 215 | |
| 216 | #define MSAR_BOOT_MODE_OFFS 12 |
| 217 | #define MSAR_BOOT_MODE_MASK (0x7 << MSAR_BOOT_MODE_OFFS) |
| 218 | #define MSAR_BOOT_NAND_WITH_BOOTROM (0x5 << MSAR_BOOT_MODE_OFFS) |
| 219 | #define MSAR_BOOT_SPI_WITH_BOOTROM (0x4 << MSAR_BOOT_MODE_OFFS) |
| 220 | #define MSAR_BOOT_SPI_USE_NAND_WITH_BOOTROM (0x2 << MSAR_BOOT_MODE_OFFS) |
| 221 | |
| 222 | #define MSAR_BOOT_MODE_6180(X) (((X & 0x3000) >> 12) | \ |
| 223 | ((X & 0x2) << 1)) |
| 224 | #define MSAR_BOOT_SPI_WITH_BOOTROM_6180 0x1 |
| 225 | #define MSAR_BOOT_NAND_WITH_BOOTROM_6180 0x5 |
| 226 | |
| 227 | #define MSAR_TCLCK_OFFS 21 |
| 228 | #define MSAR_TCLCK_MASK (0x1 << MSAR_TCLCK_OFFS) |
| 229 | #define MSAR_TCLCK_166 (0x1 << MSAR_TCLCK_OFFS) |
| 230 | #define MSAR_TCLCK_200 (0x0 << MSAR_TCLCK_OFFS) |
| 231 | |
| 232 | |
| 233 | #define MSAR_CPUCLCK_EXTRACT(X) (((X & 0x2) >> 1) | ((X & 0x400000) >> 21) | \ |
| 234 | ((X & 0x18) >> 1)) |
| 235 | |
| 236 | #define MSAR_CPUCLCK_OFFS_6180 2 |
| 237 | #define MSAR_CPUCLCK_MASK_6180 (0x7 << MSAR_CPUCLCK_OFFS_6180) |
| 238 | |
| 239 | #define MSAR_DDRCLCK_RTIO_OFFS 5 |
| 240 | #define MSAR_DDRCLCK_RTIO_MASK (0xF << MSAR_DDRCLCK_RTIO_OFFS) |
| 241 | |
| 242 | #define MSAR_L2CLCK_EXTRACT(X) (((X & 0x600) >> 9) | ((X & 0x80000) >> 17)) |
| 243 | |
| 244 | #ifndef MV_ASMLANGUAGE |
| 245 | /* CPU clock for 6281,6192 0->Resereved */ |
| 246 | #define MV_CPU_CLCK_TBL { 0, 0, 0, 0, \ |
| 247 | 600000000, 0, 800000000, 1000000000, \ |
| 248 | 0, 1200000000, 0, 0, \ |
| 249 | 1500000000, 0, 0, 0} |
| 250 | |
| 251 | /* DDR clock RATIO for 6281,6192 {0,0}->Reserved */ |
| 252 | #define MV_DDR_CLCK_RTIO_TBL {\ |
| 253 | {0, 0}, {0, 0}, {2, 1}, {0, 0}, \ |
| 254 | {3, 1}, {0, 0}, {4, 1}, {9, 2}, \ |
| 255 | {5, 1}, {6, 1}, {0, 0}, {0, 0}, \ |
| 256 | {0, 0}, {0, 0}, {0, 0}, {0, 0} \ |
| 257 | } |
| 258 | |
| 259 | /* L2 clock RATIO for 6281,6192 {1,1}->Reserved */ |
| 260 | #define MV_L2_CLCK_RTIO_TBL {\ |
| 261 | {0, 0}, {2, 1}, {0, 0}, {3, 1}, \ |
| 262 | {0, 0}, {0, 0}, {0, 0}, {0, 0} \ |
| 263 | } |
| 264 | |
| 265 | /* 6180 have different clk reset sampling */ |
| 266 | /* ARM CPU, DDR, L2 clock for 6180 {0,0,0}->Reserved */ |
| 267 | #define MV_CPU6180_DDR_L2_CLCK_TBL { \ |
| 268 | {0, 0, 0 },\ |
| 269 | {0, 0, 0 },\ |
| 270 | {0, 0, 0 },\ |
| 271 | {0, 0, 0 },\ |
| 272 | {0, 0, 0 },\ |
| 273 | {600000000, 200000000, 300000000 },\ |
| 274 | {800000000, 200000000, 400000000 },\ |
| 275 | {0, 0, 0 }\ |
| 276 | } |
| 277 | |
| 278 | |
| 279 | |
| 280 | /* These macros help units to identify a target Mbus Arbiter group */ |
| 281 | #define MV_TARGET_IS_DRAM(target) \ |
| 282 | ((target >= SDRAM_CS0) && (target <= SDRAM_CS3)) |
| 283 | |
| 284 | #define MV_TARGET_IS_PEX0(target) \ |
| 285 | ((target >= PEX0_MEM) && (target <= PEX0_IO)) |
| 286 | |
| 287 | #define MV_TARGET_IS_PEX1(target) 0 |
| 288 | |
| 289 | #define MV_TARGET_IS_PEX(target) (MV_TARGET_IS_PEX0(target) || MV_TARGET_IS_PEX1(target)) |
| 290 | |
| 291 | #define MV_TARGET_IS_DEVICE(target) \ |
| 292 | ((target >= DEVICE_CS0) && (target <= DEVICE_CS3)) |
| 293 | |
| 294 | #define MV_PCI_DRAM_BAR_TO_DRAM_TARGET(bar) 0 |
| 295 | |
| 296 | #define MV_TARGET_IS_AS_BOOT(target) ((target) == (sampleAtResetTargetArray[ \ |
| 297 | (mvCtrlModelGet() == MV_6180_DEV_ID)? MSAR_BOOT_MODE_6180 \ |
| 298 | (MV_REG_READ(MPP_SAMPLE_AT_RESET)):((MV_REG_READ(MPP_SAMPLE_AT_RESET)\ |
| 299 | & MSAR_BOOT_MODE_MASK) >> MSAR_BOOT_MODE_OFFS)])) |
| 300 | |
| 301 | |
| 302 | #define MV_CHANGE_BOOT_CS(target) (((target) == DEV_BOOCS)?\ |
| 303 | sampleAtResetTargetArray[(mvCtrlModelGet() == MV_6180_DEV_ID)? \ |
| 304 | MSAR_BOOT_MODE_6180(MV_REG_READ(MPP_SAMPLE_AT_RESET)): \ |
| 305 | ((MV_REG_READ(MPP_SAMPLE_AT_RESET) & MSAR_BOOT_MODE_MASK)\ |
| 306 | >> MSAR_BOOT_MODE_OFFS)]:(target)) |
| 307 | |
| 308 | #define TCLK_TO_COUNTER_RATIO 1 /* counters running in Tclk */ |
| 309 | |
| 310 | #define BOOT_TARGETS_NAME_ARRAY { \ |
| 311 | TBL_TERM, \ |
| 312 | TBL_TERM, \ |
| 313 | BOOT_ROM_CS, \ |
| 314 | TBL_TERM, \ |
| 315 | BOOT_ROM_CS, \ |
| 316 | BOOT_ROM_CS, \ |
| 317 | TBL_TERM, \ |
| 318 | TBL_TERM \ |
| 319 | } |
| 320 | |
| 321 | #define BOOT_TARGETS_NAME_ARRAY_6180 { \ |
| 322 | TBL_TERM, \ |
| 323 | BOOT_ROM_CS, \ |
| 324 | TBL_TERM, \ |
| 325 | TBL_TERM, \ |
| 326 | TBL_TERM, \ |
| 327 | BOOT_ROM_CS, \ |
| 328 | TBL_TERM, \ |
| 329 | TBL_TERM \ |
| 330 | } |
| 331 | |
| 332 | |
| 333 | /* For old competability */ |
| 334 | #define DEVICE_CS0 NFLASH_CS |
| 335 | #define DEVICE_CS1 SPI_CS |
| 336 | #define DEVICE_CS2 BOOT_ROM_CS |
| 337 | #define DEVICE_CS3 DEV_BOOCS |
| 338 | #define MV_BOOTDEVICE_INDEX 0 |
| 339 | |
| 340 | #define START_DEV_CS DEV_CS0 |
| 341 | #define DEV_TO_TARGET(dev) ((dev) + DEVICE_CS0) |
| 342 | |
| 343 | #define PCI_IF0_MEM0 PEX0_MEM |
| 344 | #define PCI_IF0_IO PEX0_IO |
| 345 | |
| 346 | |
| 347 | /* This enumerator defines the Marvell controller target ID */ |
| 348 | typedef enum _mvTargetId |
| 349 | { |
| 350 | DRAM_TARGET_ID = 0 , /* Port 0 -> DRAM interface */ |
| 351 | DEV_TARGET_ID = 1, /* Port 1 -> Nand/SPI */ |
| 352 | PEX0_TARGET_ID = 4 , /* Port 4 -> PCI Express0 */ |
| 353 | CRYPT_TARGET_ID = 3 , /* Port 3 --> Crypto Engine */ |
| 354 | SAGE_TARGET_ID = 12 , /* Port 12 -> SAGE Unit */ |
| 355 | MAX_TARGETS_ID |
| 356 | }MV_TARGET_ID; |
| 357 | |
| 358 | |
| 359 | /* This enumerator described the possible Controller paripheral targets. */ |
| 360 | /* Controller peripherals are designated memory/IO address spaces that the */ |
| 361 | /* controller can access. They are also refered as "targets" */ |
| 362 | typedef enum _mvTarget |
| 363 | { |
| 364 | TBL_TERM = -1, /* none valid target, used as targets list terminator*/ |
| 365 | SDRAM_CS0, /* SDRAM chip select 0 */ |
| 366 | SDRAM_CS1, /* SDRAM chip select 1 */ |
| 367 | SDRAM_CS2, /* SDRAM chip select 2 */ |
| 368 | SDRAM_CS3, /* SDRAM chip select 3 */ |
| 369 | PEX0_MEM, /* PCI Express 0 Memory */ |
| 370 | PEX0_IO, /* PCI Express 0 IO */ |
| 371 | INTER_REGS, /* Internal registers */ |
| 372 | NFLASH_CS, /* NFLASH_CS */ |
| 373 | SPI_CS, /* SPI_CS */ |
| 374 | BOOT_ROM_CS, /* BOOT_ROM_CS */ |
| 375 | DEV_BOOCS, /* DEV_BOOCS */ |
| 376 | CRYPT_ENG, /* Crypto Engine */ |
| 377 | #ifdef MV_INCLUDE_SAGE |
| 378 | SAGE_UNIT, /* SAGE Unit */ |
| 379 | #endif |
| 380 | MAX_TARGETS |
| 381 | |
| 382 | }MV_TARGET; |
| 383 | |
| 384 | #define TARGETS_DEF_ARRAY { \ |
| 385 | {0x0E, DRAM_TARGET_ID }, /* SDRAM_CS0 */ \ |
| 386 | {0x0D, DRAM_TARGET_ID }, /* SDRAM_CS1 */ \ |
| 387 | {0x0B, DRAM_TARGET_ID }, /* SDRAM_CS0 */ \ |
| 388 | {0x07, DRAM_TARGET_ID }, /* SDRAM_CS1 */ \ |
| 389 | {0xE8, PEX0_TARGET_ID }, /* PEX0_MEM */ \ |
| 390 | {0xE0, PEX0_TARGET_ID }, /* PEX0_IO */ \ |
| 391 | {0xFF, 0xFF }, /* INTER_REGS */ \ |
| 392 | {0x2F, DEV_TARGET_ID }, /* NFLASH_CS */ \ |
| 393 | {0x1E, DEV_TARGET_ID }, /* SPI_CS */ \ |
| 394 | {0x1D, DEV_TARGET_ID }, /* BOOT_ROM_CS */ \ |
| 395 | {0x1E, DEV_TARGET_ID }, /* DEV_BOOCS */ \ |
| 396 | {0x01, CRYPT_TARGET_ID}, /* CRYPT_ENG */ \ |
| 397 | {0x00, SAGE_TARGET_ID } \ |
| 398 | } |
| 399 | |
| 400 | |
| 401 | #define TARGETS_NAME_ARRAY { \ |
| 402 | "SDRAM_CS0", /* SDRAM_CS0 */ \ |
| 403 | "SDRAM_CS1", /* SDRAM_CS1 */ \ |
| 404 | "SDRAM_CS2", /* SDRAM_CS2 */ \ |
| 405 | "SDRAM_CS3", /* SDRAM_CS3 */ \ |
| 406 | "PEX0_MEM", /* PEX0_MEM */ \ |
| 407 | "PEX0_IO", /* PEX0_IO */ \ |
| 408 | "INTER_REGS", /* INTER_REGS */ \ |
| 409 | "NFLASH_CS", /* NFLASH_CS */ \ |
| 410 | "SPI_CS", /* SPI_CS */ \ |
| 411 | "BOOT_ROM_CS", /* BOOT_ROM_CS */ \ |
| 412 | "DEV_BOOTCS", /* DEV_BOOCS */ \ |
| 413 | "CRYPT_ENG", /* CRYPT_ENG */ \ |
| 414 | "SAGE_UNIT" /* SAGE_UNIT */ \ |
| 415 | } |
| 416 | #endif /* MV_ASMLANGUAGE */ |
| 417 | |
| 418 | |
| 419 | #endif |
| 420 | |
