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| 62 | |
| 63 | *******************************************************************************/ |
| 64 | |
| 65 | #define MV_ASMLANGUAGE |
| 66 | #include "mvOsAsm.h" |
| 67 | #include "mvDeviceId.h" |
| 68 | #include "mvCtrlEnvRegs.h" |
| 69 | #include "mvCpuIfRegs.h" |
| 70 | #include "mvCtrlEnvAsm.h" |
| 71 | |
| 72 | |
| 73 | /******************************************************************************* |
| 74 | * mvCpuIfPreInit - Make early initialization of CPU interface. |
| 75 | * |
| 76 | * DESCRIPTION: |
| 77 | * The function will initialize the CPU interface parameters that must |
| 78 | * be initialize before any BUS activity towards the DDR interface, |
| 79 | * which means it must be executed from ROM. Because of that, the function |
| 80 | * is implemented in assembly code. |
| 81 | * The function configure the following CPU config register parameters: |
| 82 | * 1) CPU2MbusLTickDrv |
| 83 | * 2) CPU2MbusLTickSample. |
| 84 | * NOTE: This function must be called AFTER the internal register |
| 85 | * base is modified to INTER_REGS_BASE. |
| 86 | * |
| 87 | * INPUT: |
| 88 | * None. |
| 89 | * |
| 90 | * OUTPUT: |
| 91 | * None. |
| 92 | * |
| 93 | * RETURN: |
| 94 | * None. |
| 95 | * |
| 96 | * r11 holds return function address. |
| 97 | *******************************************************************************/ |
| 98 | #define MV88F6281_PCKG_OPT 2 |
| 99 | #define MV88F6192_PCKG_OPT 1 |
| 100 | #define MV88F6180_PCKG_OPT 0 |
| 101 | |
| 102 | .globl _mvCpuIfPreInit |
| 103 | _mvCpuIfPreInit: |
| 104 | |
| 105 | mov r11, LR /* Save link register */ |
| 106 | |
| 107 | /* Read device ID */ |
| 108 | MV_CTRL_MODEL_GET_ASM(r4, r5); |
| 109 | |
| 110 | /* goto calcConfigReg if device is 6281 */ |
| 111 | ldr r5, =MV88F6281_PCKG_OPT |
| 112 | cmp r4, r5 |
| 113 | beq calcConfigReg |
| 114 | |
| 115 | /* goto calcConfigReg if device is 6192/6190 */ |
| 116 | ldr r5, =MV88F6192_PCKG_OPT |
| 117 | cmp r4, r5 |
| 118 | beq calcConfigReg |
| 119 | |
| 120 | /* Else 6180 */ |
| 121 | /* Get the "sample on reset" register */ |
| 122 | MV_REG_READ_ASM (r4, r5, MPP_SAMPLE_AT_RESET) |
| 123 | ldr r5, =MSAR_CPUCLCK_MASK_6180 |
| 124 | and r5, r4, r5 |
| 125 | mov r5, r5, lsr #MSAR_CPUCLCK_OFFS_6180 |
| 126 | |
| 127 | ldr r4, =CPU_2_MBUSL_DDR_CLK_1x3 |
| 128 | cmp r5, #CPU_2_DDR_CLK_1x3_1 |
| 129 | beq setConfigReg |
| 130 | |
| 131 | ldr r4, =CPU_2_MBUSL_DDR_CLK_1x4 |
| 132 | cmp r5, #CPU_2_DDR_CLK_1x4_1 |
| 133 | beq setConfigReg |
| 134 | b setConfigReg |
| 135 | |
| 136 | calcConfigReg: |
| 137 | /* Get the "sample on reset" register */ |
| 138 | MV_REG_READ_ASM (r4, r5, MPP_SAMPLE_AT_RESET) |
| 139 | ldr r5, =MSAR_DDRCLCK_RTIO_MASK |
| 140 | and r5, r4, r5 |
| 141 | mov r5, r5, lsr #MSAR_DDRCLCK_RTIO_OFFS |
| 142 | |
| 143 | ldr r4, =CPU_2_MBUSL_DDR_CLK_1x3 |
| 144 | cmp r5, #CPU_2_DDR_CLK_1x3 |
| 145 | beq setConfigReg |
| 146 | |
| 147 | ldr r4, =CPU_2_MBUSL_DDR_CLK_1x4 |
| 148 | cmp r5, #CPU_2_DDR_CLK_1x4 |
| 149 | beq setConfigReg |
| 150 | |
| 151 | /* Else */ |
| 152 | ldr r4, =0 |
| 153 | |
| 154 | setConfigReg: |
| 155 | /* Read CPU Config register */ |
| 156 | MV_REG_READ_ASM (r7, r5, CPU_CONFIG_REG) |
| 157 | ldr r5, =~(CCR_CPU_2_MBUSL_TICK_DRV_MASK | CCR_CPU_2_MBUSL_TICK_SMPL_MASK) |
| 158 | and r7, r7, r5 /* Clear register fields */ |
| 159 | orr r7, r7, r4 /* Set the values according to the findings */ |
| 160 | MV_REG_WRITE_ASM (r7, r5, CPU_CONFIG_REG) |
| 161 | |
| 162 | done: |
| 163 | mov PC, r11 /* r11 is saved link register */ |
| 164 | |
