Root/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/cpu/mvCpuCntrs.h

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28#ifndef __mvCpuCntrs_h__
29#define __mvCpuCntrs_h__
30
31#include "mvTypes.h"
32#include "mvOs.h"
33
34
35#define MV_CPU_CNTRS_NUM 4
36#define MV_CPU_CNTRS_OPS_NUM 32
37
38typedef enum
39{
40    MV_CPU_CNTRS_INVALID = 0,
41    MV_CPU_CNTRS_CYCLES,
42    MV_CPU_CNTRS_ICACHE_READ_MISS,
43    MV_CPU_CNTRS_DCACHE_ACCESS,
44    MV_CPU_CNTRS_DCACHE_READ_MISS,
45    MV_CPU_CNTRS_DCACHE_READ_HIT,
46    MV_CPU_CNTRS_DCACHE_WRITE_MISS,
47    MV_CPU_CNTRS_DCACHE_WRITE_HIT,
48    MV_CPU_CNTRS_DTLB_MISS,
49    MV_CPU_CNTRS_TLB_MISS,
50    MV_CPU_CNTRS_ITLB_MISS,
51    MV_CPU_CNTRS_INSTRUCTIONS,
52    MV_CPU_CNTRS_SINGLE_ISSUE,
53    MV_CPU_CNTRS_MMU_READ_LATENCY,
54    MV_CPU_CNTRS_MMU_READ_BEAT,
55    MV_CPU_CNTRS_BRANCH_RETIRED,
56    MV_CPU_CNTRS_BRANCH_TAKEN,
57    MV_CPU_CNTRS_BRANCH_PREDICT_MISS,
58    MV_CPU_CNTRS_BRANCH_PREDICT_COUNT,
59    MV_CPU_CNTRS_WB_FULL_CYCLES,
60    MV_CPU_CNTRS_WB_WRITE_LATENCY,
61    MV_CPU_CNTRS_WB_WRITE_BEAT,
62    MV_CPU_CNTRS_ICACHE_READ_LATENCY,
63    MV_CPU_CNTRS_ICACHE_READ_BEAT,
64    MV_CPU_CNTRS_DCACHE_READ_LATENCY,
65    MV_CPU_CNTRS_DCACHE_READ_BEAT,
66    MV_CPU_CNTRS_DCACHE_WRITE_LATENCY,
67    MV_CPU_CNTRS_DCACHE_WRITE_BEAT,
68    MV_CPU_CNTRS_LDM_STM_HOLD,
69    MV_CPU_CNTRS_IS_HOLD,
70    MV_CPU_CNTRS_DATA_WRITE_ACCESS,
71    MV_CPU_CNTRS_DATA_READ_ACCESS,
72    MV_CPU_CNTRS_BIU_SIMULT_ACCESS,
73    MV_CPU_CNTRS_BIU_ANY_ACCESS,
74
75} MV_CPU_CNTRS_OPS;
76
77typedef struct
78{
79    char name[16];
80    MV_CPU_CNTRS_OPS operation;
81    int opIdx;
82    MV_U32 overhead;
83    
84} MV_CPU_CNTRS_ENTRY;
85
86
87typedef struct
88{
89    char name[16];
90    MV_U32 num_of_measurements;
91    MV_U32 avg_sample_count;
92    MV_U64 counters_before[MV_CPU_CNTRS_NUM];
93    MV_U64 counters_after[MV_CPU_CNTRS_NUM];
94    MV_U64 counters_sum[MV_CPU_CNTRS_NUM];
95
96} MV_CPU_CNTRS_EVENT;
97
98extern MV_CPU_CNTRS_ENTRY mvCpuCntrsTbl[MV_CPU_CNTRS_NUM];
99
100
101MV_STATUS mvCpuCntrsProgram(int counter, MV_CPU_CNTRS_OPS op,
102                                      char* name, MV_U32 overhead);
103void mvCpuCntrsInit(void);
104MV_CPU_CNTRS_EVENT* mvCpuCntrsEventCreate(char* name, MV_U32 print_threshold);
105void mvCpuCntrsEventDelete(MV_CPU_CNTRS_EVENT* event);
106void mvCpuCntrsReset(void);
107void mvCpuCntrsShow(MV_CPU_CNTRS_EVENT* pEvent);
108void mvCpuCntrsEventClear(MV_CPU_CNTRS_EVENT* pEvent);
109
110/* internal */
111void program_counter(int counter, int op);
112
113static INLINE MV_U64 mvCpuCntrsRead(const int counter)
114{
115    MV_U32 low = 0, high = 0;
116    MV_U32 ll = 0;
117    
118    switch(counter)
119    {
120        case 0:
121            MV_ASM ("mcr p15, 0, %0, c15, c12, 0" : : "r" (ll));
122            MV_ASM ("mrc p15, 0, %0, c15, c13, 0" : "=r" (low));
123            MV_ASM ("mrc p15, 0, %0, c15, c13, 1" : "=r" (high));
124         break;
125
126        case 1:
127            MV_ASM ("mcr p15, 0, %0, c15, c12, 1" : : "r" (ll));
128            MV_ASM ("mrc p15, 0, %0, c15, c13, 2" : "=r" (low));
129            MV_ASM ("mrc p15, 0, %0, c15, c13, 3" : "=r" (high));
130         break;
131
132        case 2:
133            MV_ASM ("mcr p15, 0, %0, c15, c12, 2" : : "r" (ll));
134            MV_ASM ("mrc p15, 0, %0, c15, c13, 4" : "=r" (low));
135            MV_ASM ("mrc p15, 0, %0, c15, c13, 5" : "=r" (high));
136         break;
137
138        case 3:
139            MV_ASM ("mcr p15, 0, %0, c15, c12, 3" : : "r" (ll));
140            MV_ASM ("mrc p15, 0, %0, c15, c13, 6" : "=r" (low));
141            MV_ASM ("mrc p15, 0, %0, c15, c13, 7" : "=r" (high));
142         break;
143
144        default:
145            mvOsPrintf("mv_cpu_cntrs_read: bad counter number (%d)\n", counter);
146    }
147    program_counter(counter, mvCpuCntrsTbl[counter].opIdx);
148    return (((MV_U64)high << 32 ) | low);
149
150}
151
152
153static INLINE void mvCpuCntrsReadBefore(MV_CPU_CNTRS_EVENT* pEvent)
154{
155#if 0
156    int i;
157
158    /* order is important - we want to measure the cycle count last here! */
159    for(i=0; i<MV_CPU_CNTRS_NUM; i++)
160        pEvent->counters_before[i] = mvCpuCntrsRead(i);
161#else
162    pEvent->counters_before[1] = mvCpuCntrsRead(1);
163    pEvent->counters_before[3] = mvCpuCntrsRead(3);
164    pEvent->counters_before[0] = mvCpuCntrsRead(0);
165    pEvent->counters_before[2] = mvCpuCntrsRead(2);
166#endif
167}
168
169static INLINE void mvCpuCntrsReadAfter(MV_CPU_CNTRS_EVENT* pEvent)
170{
171    int i;
172
173#if 0
174    /* order is important - we want to measure the cycle count first here! */
175    for(i=0; i<MV_CPU_CNTRS_NUM; i++)
176        pEvent->counters_after[i] = mvCpuCntrsRead(i);
177#else
178    pEvent->counters_after[2] = mvCpuCntrsRead(2);
179    pEvent->counters_after[0] = mvCpuCntrsRead(0);
180    pEvent->counters_after[3] = mvCpuCntrsRead(3);
181    pEvent->counters_after[1] = mvCpuCntrsRead(1);
182#endif
183
184    for(i=0; i<MV_CPU_CNTRS_NUM; i++)
185    {
186        pEvent->counters_sum[i] += (pEvent->counters_after[i] - pEvent->counters_before[i]);
187    }
188    pEvent->num_of_measurements++;
189}
190
191
192#ifdef CONFIG_MV_CPU_PERF_CNTRS
193
194#define MV_CPU_CNTRS_READ(counter) mvCpuCntrsRead(counter)
195
196#define MV_CPU_CNTRS_START(event) mvCpuCntrsReadBefore(event)
197
198#define MV_CPU_CNTRS_STOP(event) mvCpuCntrsReadAfter(event)
199            
200#define MV_CPU_CNTRS_SHOW(event) mvCpuCntrsShow(event)
201
202#else
203
204#define MV_CPU_CNTRS_READ(counter)
205#define MV_CPU_CNTRS_START(event)
206#define MV_CPU_CNTRS_STOP(event)
207#define MV_CPU_CNTRS_SHOW(event)
208
209#endif /* CONFIG_MV_CPU_PERF_CNTRS */
210
211
212#endif /* __mvCpuCntrs_h__ */
213
214

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