Root/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDramIfConfig.S

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63*******************************************************************************/
64
65/*******************************************************************************
66* mvDramIfBasicAsm.s
67*
68* DESCRIPTION:
69* Memory full detection and best timing configuration is done in
70* C code. C runtime environment requires a stack. This module API
71* initialize DRAM interface chip select 0 for basic functionality for
72* the use of stack.
73* The module API assumes DRAM information is stored in I2C EEPROM reside
74* in a given I2C address MV_BOARD_DIMM0_I2C_ADDR. The I2C EEPROM
75* internal data structure is assumed to be orgenzied in common DRAM
76* vendor SPD structure.
77* NOTE: DFCDL values are assumed to be already initialized prior to
78* this module API activity.
79*
80*
81* DEPENDENCIES:
82* None.
83*
84*******************************************************************************/
85
86/* includes */
87#define MV_ASMLANGUAGE
88#include "mvOsAsm.h"
89#include "mvSysHwConfig.h"
90#include "mvDramIfRegs.h"
91#include "mvDramIfConfig.h"
92#include "mvCpuIfRegs.h"
93#include "pex/mvPexRegs.h"
94#include "pci/mvPciRegs.h"
95#include "mvCtrlEnvSpec.h"
96#include "mvCtrlEnvAsm.h"
97#include "cpu/mvCpuArm.h"
98#include "mvCommon.h"
99
100/* defines */
101
102/* locals */
103.data
104.globl _mvDramIfConfig
105
106.text
107
108/*******************************************************************************
109* _mvDramIfConfig - Basic DRAM interface initialization.
110*
111* DESCRIPTION:
112* The function will initialize the following DRAM parameters using the
113* values prepared by mvDramIfDetect routine. Values are located
114* in predefined registers.
115*
116* INPUT:
117* None.
118*
119* OUTPUT:
120* None.
121*
122* RETURN:
123* None.
124*
125*******************************************************************************/
126
127_mvDramIfConfig:
128
129        /* Save register on stack */
130    cmp sp, #0
131    beq no_stack_s
132save_on_stack:
133        stmdb sp!, {r1, r2, r3, r4, r7, r11}
134no_stack_s:
135
136    /* 1) Write to SDRAM coniguration register */
137        ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG1)
138        ldr r4, [r1]
139        ldr r1, =(INTER_REGS_BASE + SDRAM_CONFIG_REG)
140        str r4, [r1]
141
142    /* 2) Write Dunit control low register */
143        ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG3)
144        ldr r4, [r1]
145        ldr r1, =(INTER_REGS_BASE + SDRAM_DUNIT_CTRL_REG)
146        str r4, [r1]
147
148        /* 3) Write SDRAM address control register */
149        ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG4)
150        ldr r4, [r1]
151        ldr r1, =(INTER_REGS_BASE + SDRAM_ADDR_CTRL_REG)
152        str r4, [r1]
153
154        /* 4) Write SDRAM bank 0 size register */
155        ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG0)
156        ldr r4, [r1]
157        ldr r1, =(INTER_REGS_BASE + SDRAM_SIZE_REG(0))
158        str r4, [r1]
159
160        /* 5) Write SDRAM open pages control register */
161        ldr r1, =(INTER_REGS_BASE + SDRAM_OPEN_PAGE_CTRL_REG)
162        ldr r4, =SDRAM_OPEN_PAGES_CTRL_REG_DV
163        str r4, [r1]
164
165        /* 6) Write SDRAM timing Low register */
166        ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG5)
167        ldr r4, [r1]
168        ldr r1, =(INTER_REGS_BASE + SDRAM_TIMING_CTRL_LOW_REG)
169        str r4, [r1]
170
171        /* 7) Write SDRAM timing High register */
172        ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG6)
173        ldr r4, [r1]
174        ldr r1, =(INTER_REGS_BASE + SDRAM_TIMING_CTRL_HIGH_REG)
175        str r4, [r1]
176
177        /* 8) Write SDRAM mode register */
178        /* The CPU must not attempt to change the SDRAM Mode register setting */
179        /* prior to DRAM controller completion of the DRAM initialization */
180        /* sequence. To guarantee this restriction, it is recommended that */
181        /* the CPU sets the SDRAM Operation register to NOP command, performs */
182        /* read polling until the register is back in Normal operation value, */
183        /* and then sets SDRAM Mode register to it’s new value. */
184
185    /* 8.1 write 'nop' to SDRAM operation */
186        mov r4, #0x5 /* 'NOP' command */
187        MV_REG_WRITE_ASM(r4, r1, SDRAM_OPERATION_REG)
188
189        /* 8.2 poll SDRAM operation. Make sure its back to normal operation */
190_sdramOpPoll1:
191        ldr r4, [r1]
192        cmp r4, #0 /* '0' = Normal SDRAM Mode */
193        bne _sdramOpPoll1
194
195        /* 8.3 Now its safe to write new value to SDRAM Mode register */
196        ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG2)
197        ldr r4, [r1]
198        ldr r1, =(INTER_REGS_BASE + SDRAM_MODE_REG)
199        str r4, [r1]
200
201        /* 8.4 Make the Dunit write the DRAM its new mode */
202        mov r4, #0x3 /* Mode Register Set command */
203        MV_REG_WRITE_ASM (r4, r1, SDRAM_OPERATION_REG)
204
205        /* 8.5 poll SDRAM operation. Make sure its back to normal operation */
206_sdramOpPoll2:
207        ldr r4, [r1]
208        cmp r4, #0 /* '0' = Normal SDRAM Mode */
209        bne _sdramOpPoll2
210
211#ifndef DB_FPGA
212        /* Config DDR2 registers (Extended mode, ODTs and pad calibration) */
213        MV_REG_READ_ASM (r4, r1, SDRAM_CONFIG_REG)
214        tst r4, #SDRAM_DTYPE_DDR2
215        beq _extModeODTEnd
216#endif /* DB_FPGA */
217
218        /* 9) Write SDRAM Extended mode register This operation should be */
219        /* done for each memory bank */
220        /* write 'nop' to SDRAM operation */
221        mov r4, #0x5 /* 'NOP' command */
222        MV_REG_WRITE_ASM (r4, r1, SDRAM_OPERATION_REG)
223
224        /* poll SDRAM operation. Make sure its back to normal operation */
225_sdramOpPoll3:
226        ldr r4, [r1]
227        cmp r4, #0 /* '0' = Normal SDRAM Mode */
228        bne _sdramOpPoll3
229
230        /* Now its safe to write new value to SDRAM Extended Mode register */
231        ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG10)
232        ldr r4, [r1]
233        ldr r1, =(INTER_REGS_BASE + SDRAM_EXTENDED_MODE_REG)
234        str r4, [r1]
235
236        /* Go over each of the Banks */
237        ldr r3, =0 /* r3 = DRAM bank Num */
238
239extModeLoop:
240        /* Set the SDRAM Operation Control to each of the DRAM banks */
241        mov r2, r3 /* Do not swap the bank counter value */
242        MV_REG_WRITE_ASM (r2, r1, SDRAM_OPERATION_CTRL_REG)
243
244        /* Make the Dunit write the DRAM its new mode */
245        mov r4, #0x4 /* Extended Mode Register Set command */
246        MV_REG_WRITE_ASM (r4, r1, SDRAM_OPERATION_REG)
247
248        /* poll SDRAM operation. Make sure its back to normal operation */
249_sdramOpPoll4:
250        ldr r4, [r1]
251        cmp r4, #0 /* '0' = Normal SDRAM Mode */
252        bne _sdramOpPoll4
253#ifndef DB_FPGA
254        add r3, r3, #1
255        cmp r3, #4 /* 4 = Number of banks */
256        bne extModeLoop
257
258extModeEnd:
259        /* Config DDR2 On Die Termination (ODT) registers */
260        /* Write SDRAM DDR2 ODT control low register */
261        ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG7)
262        ldr r4, [r1]
263        ldr r1, =(INTER_REGS_BASE + DDR2_SDRAM_ODT_CTRL_LOW_REG)
264        str r4, [r1]
265
266        /* Write SDRAM DDR2 ODT control high register */
267        ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG8)
268        ldr r4, [r1]
269        ldr r1, =(INTER_REGS_BASE + DDR2_SDRAM_ODT_CTRL_HIGH_REG)
270        str r4, [r1]
271
272        /* Write SDRAM DDR2 Dunit ODT control register */
273        ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG9)
274        ldr r4, [r1]
275        ldr r1, =(INTER_REGS_BASE + DDR2_DUNIT_ODT_CONTROL_REG)
276        str r4, [r1]
277
278#endif /* DB_FPGA */
279_extModeODTEnd:
280#ifndef DB_FPGA
281        /* Implement Guideline (GL# MEM-2) P_CAL Automatic Calibration */
282        /* Does Not Work for Address/Control and Data Pads. */
283        /* Relevant for: 88F5181-A1/B0 and 88F5281-A0 */
284
285    /* Read device ID */
286    MV_CTRL_MODEL_GET_ASM(r3, r1);
287        /* Read device revision */
288    MV_CTRL_REV_GET_ASM(r2, r1);
289
290    /* Continue if OrionN */
291        ldr r1, =MV_5180_DEV_ID
292        cmp r3, r1
293        bne 1f
294        b glMem2End
2951:
296        /* Continue if Orion1 and device revision B1 */
297        ldr r1, =MV_5181_DEV_ID
298        cmp r3, r1
299        bne 1f
300
301        cmp r2, #MV_5181_B1_REV
302        bge glMem2End
303        b glMem2Start
3041:
305
306        /* Orion NAS */
307        ldr r1, =MV_5182_DEV_ID
308        cmp r3, r1
309        beq glMem2Start
310
311        /* Orion NAS */
312        ldr r1, =MV_5082_DEV_ID
313        cmp r3, r1
314        beq glMem2Start
315
316        /* Orion Shark */
317        ldr r1, =MV_8660_DEV_ID
318        cmp r3, r1
319        beq glMem2Start
320
321    b glMem2End
322
323glMem2Start:
324
325        /* DDR SDRAM Address/Control Pads Calibration */
326        MV_REG_READ_ASM (r3, r1, SDRAM_ADDR_CTRL_PADS_CAL_REG)
327
328        /* Set Bit [31] to make the register writable */
329        orr r2, r3, #SDRAM_WR_EN
330
331        MV_REG_WRITE_ASM (r2, r1, SDRAM_ADDR_CTRL_PADS_CAL_REG)
332
333        bic r3, r3, #SDRAM_WR_EN /* Make register read-only */
334        bic r3, r3, #SDRAM_TUNE_EN /* Disable auto calibration */
335        bic r3, r3, #SDRAM_DRVN_MASK /* Clear r1[5:0]<DrvN> */
336        bic r3, r3, #SDRAM_DRVP_MASK /* Clear r1[11:6]<DrvP> */
337
338        /* Get the final N locked value of driving strength [22:17] */
339        mov r1, r3
340        mov r1, r1, LSL #9
341        mov r1, r1, LSR #26 /* r1[5:0]<DrvN> = r3[22:17]<LockN> */
342        orr r1, r1, r1, LSL #6 /* r1[11:6]<DrvP> = r1[5:0]<DrvN> */
343
344        /* Write to both <DrvN> bits [5:0] and <DrvP> bits [11:6] */
345        orr r3, r3, r1
346
347        MV_REG_WRITE_ASM (r3, r1, SDRAM_ADDR_CTRL_PADS_CAL_REG)
348
349
350        /* DDR SDRAM Data Pads Calibration */
351        MV_REG_READ_ASM (r3, r1, SDRAM_DATA_PADS_CAL_REG)
352
353        /* Set Bit [31] to make the register writable */
354        orr r2, r3, #SDRAM_WR_EN
355
356        MV_REG_WRITE_ASM (r2, r1, SDRAM_DATA_PADS_CAL_REG)
357
358        bic r3, r3, #SDRAM_WR_EN /* Make register read-only */
359        bic r3, r3, #SDRAM_TUNE_EN /* Disable auto calibration */
360        bic r3, r3, #SDRAM_DRVN_MASK /* Clear r1[5:0]<DrvN> */
361        bic r3, r3, #SDRAM_DRVP_MASK /* Clear r1[11:6]<DrvP> */
362
363        /* Get the final N locked value of driving strength [22:17] */
364        mov r1, r3
365        mov r1, r1, LSL #9
366        mov r1, r1, LSR #26
367        orr r1, r1, r1, LSL #6 /* r1[5:0] = r3[22:17]<LockN> */
368
369        /* Write to both <DrvN> bits [5:0] and <DrvP> bits [11:6] */
370        orr r3, r3, r1
371
372        MV_REG_WRITE_ASM (r3, r1, SDRAM_DATA_PADS_CAL_REG)
373
374glMem2End:
375
376
377        /* Implement Guideline (GL# MEM-3) Drive Strength Value */
378        /* Relevant for: 88F5181-A1/B0/B1, 88F5281-A0/B0/C/D, 88F5182, */
379    /* 88F5082, 88F5181L, 88F6082/L, 88F6183, 88F6183L */
380
381        /* Get SDRAM Config value */
382        MV_REG_READ_ASM (r2, r1, SDRAM_CONFIG_REG)
383
384        /* Get DIMM type */
385        tst r2, #SDRAM_DTYPE_DDR2
386        beq ddr1StrengthVal
387
388ddr2StrengthVal:
389        ldr r4, =DDR2_ADDR_CTRL_PAD_STRENGTH_TYPICAL_DV
390        ldr r2, =DDR2_DATA_PAD_STRENGTH_TYPICAL_DV
391        b setDrvStrength
392ddr1StrengthVal:
393        ldr r4, =DDR1_ADDR_CTRL_PAD_STRENGTH_TYPICAL_DV
394        ldr r2, =DDR1_DATA_PAD_STRENGTH_TYPICAL_DV
395
396setDrvStrength:
397        /* DDR SDRAM Address/Control Pads Calibration */
398        MV_REG_READ_ASM (r3, r1, SDRAM_ADDR_CTRL_PADS_CAL_REG)
399
400        orr r3, r3, #SDRAM_WR_EN /* Make register writeable */
401
402        MV_REG_WRITE_ASM (r3, r1, SDRAM_ADDR_CTRL_PADS_CAL_REG)
403        HTOLL(r3,r1)
404
405        bic r3, r3, #SDRAM_WR_EN /* Make register read-only */
406        bic r3, r3, #SDRAM_PRE_DRIVER_STRENGTH_MASK
407        orr r3, r4, r3 /* Set default value for DDR */
408
409        MV_REG_WRITE_ASM (r3, r1, SDRAM_ADDR_CTRL_PADS_CAL_REG)
410
411
412        /* DDR SDRAM Data Pads Calibration */
413        MV_REG_READ_ASM (r3, r1, SDRAM_DATA_PADS_CAL_REG)
414
415        orr r3, r3, #SDRAM_WR_EN /* Make register writeable */
416
417        MV_REG_WRITE_ASM (r3, r1, SDRAM_DATA_PADS_CAL_REG)
418        HTOLL(r3,r1)
419
420        bic r3, r3, #SDRAM_WR_EN /* Make register read-only */
421        bic r3, r3, #SDRAM_PRE_DRIVER_STRENGTH_MASK
422        orr r3, r2, r3 /* Set default value for DDR */
423
424        MV_REG_WRITE_ASM (r3, r1, SDRAM_DATA_PADS_CAL_REG)
425
426#if !defined(MV_88W8660) && !defined(MV_88F6183) && !defined(MV_88F6183L)
427        /* Implement Guideline (GL# MEM-4) DQS Reference Delay Tuning */
428        /* Relevant for: 88F5181-A1/B0/B1 and 88F5281-A0/B0/C/D, 88F5182 */
429    /* 88F5082, 88F5181L, 88F6082/L */
430                
431    /* Calc the absolute address of the _cpuARMDDRCLK[] in the boot flash */
432    ldr r7, = _cpuARMDDRCLK
433    ldr r4, =_start
434    sub r7, r7, r4
435    add r7, r7, #CFG_MONITOR_BASE
436
437        /* Get the "sample on reset" register for the DDR frequancy */
438        MV_REG_READ_ASM (r4, r1, MPP_SAMPLE_AT_RESET)
439        ldr r1, =MSAR_ARMDDRCLCK_MASK
440        and r1, r4, r1
441#if 0 /* YOTAM TO BE FIX */
442    mov r1, r1, LSR #MSAR_ARMDDRCLCK_OFFS
443#endif
444
445    /* Read device ID */
446    MV_CTRL_MODEL_GET_ASM(r3, r2);
447
448        /* Continue if TC90 */
449        ldr r2, =MV_1281_DEV_ID
450        cmp r3, r2
451        beq armClkMsb
452
453        /* Continue if Orion2 */
454        ldr r2, =MV_5281_DEV_ID
455        cmp r3, r2
456#if 0 /* YOTAM TO BE FIX */
457        bne 1f
458#endif
459
460armClkMsb:
461#if 0 /* YOTAM TO BE FIX */
462    tst r4, #MSAR_ARMDDRCLCK_H_MASK
463        beq 1f
464        orr r1, r1, #BIT4
4651:
466    ldr r4, =MV_CPU_ARM_CLK_ELM_SIZE
467    mul r1, r4, r1
468    add r7, r7, r1
469    add r7, r7, #MV_CPU_ARM_CLK_DDR_OFF
470    ldr r1, [r7]
471#endif
472
473        /* Get SDRAM Config value */
474        MV_REG_READ_ASM (r2, r4, SDRAM_CONFIG_REG)
475
476        /* Get DIMM type */
477        tst r2, #SDRAM_DTYPE_DDR2
478        beq ddr1FtdllVal
479
480ddr2FtdllVal:
481        ldr r2, =MV_5281_DEV_ID
482        cmp r3, r2
483    bne 2f
484        MV_CTRL_REV_GET_ASM(r3, r2)
485        cmp r3, #MV_5281_D0_REV
486        beq orin2_d0_ddr2_ftdll_val
487        cmp r3, #MV_5281_D1_REV
488        beq orin2_d1_ddr2_ftdll_val
489        cmp r3, #MV_5281_D2_REV
490        beq orin2_d1_ddr2_ftdll_val
491    b ddr2_default_val
492
493/* Set Orion 2 D1 ftdll values for DDR2 */
494orin2_d1_ddr2_ftdll_val:
495    ldr r4, =FTDLL_DDR2_250MHZ_5281_D1
496    ldr r7, =_250MHz
497        cmp r1, r7
498        beq setFtdllReg
499        ldr r4, =FTDLL_DDR2_200MHZ_5281_D1
500    ldr r7, =_200MHz
501        cmp r1, r7
502        beq setFtdllReg
503        ldr r4, =FTDLL_DDR2_166MHZ_5281_D0
504    ldr r7, =_166MHz
505        cmp r1, r7
506        beq setFtdllReg
507    b ddr2_default_val
508
509/* Set Orion 2 D0 ftdll values for DDR2 */
510orin2_d0_ddr2_ftdll_val:
511    ldr r4, =FTDLL_DDR2_250MHZ_5281_D0
512    ldr r7, =_250MHz
513        cmp r1, r7
514        beq setFtdllReg
515        ldr r4, =FTDLL_DDR2_200MHZ_5281_D0
516    ldr r7, =_200MHz
517        cmp r1, r7
518        beq setFtdllReg
519        ldr r4, =FTDLL_DDR2_166MHZ_5281_D0
520    ldr r7, =_166MHz
521        cmp r1, r7
522        beq setFtdllReg
523    b ddr2_default_val
5242:
525        ldr r2, =MV_5182_DEV_ID
526        cmp r3, r2
527    bne 3f
528
529/* Set Orion nas ftdll values for DDR2 */
530orin_nas_ftdll_val:
531        ldr r4, =FTDLL_DDR2_166MHZ_5182
532    ldr r7, =_166MHz
533        cmp r1, r7
534        beq setFtdllReg
535
536/* default values for all other devices */
5373:
538ddr2_default_val:
539        ldr r4, =FTDLL_DDR2_250MHZ
540    ldr r7, =_250MHz
541        cmp r1, r7
542        beq setFtdllReg
543        ldr r4, =FTDLL_DDR2_200MHZ
544    ldr r7, =_200MHz
545        cmp r1, r7
546        beq setFtdllReg
547        ldr r4, =FTDLL_DDR2_166MHZ
548    ldr r7, =_166MHz
549        cmp r1, r7
550        beq setFtdllReg
551        ldr r4, =FTDLL_DDR2_133MHZ
552    ldr r7, =_133MHz
553        cmp r1, r7
554        beq setFtdllReg
555        ldr r4, =0
556        b setFtdllReg
557
558ddr1FtdllVal:
559        ldr r2, =MV_5281_DEV_ID
560        cmp r3, r2
561    bne 2f
562        MV_CTRL_REV_GET_ASM(r3, r2)
563        cmp r3, #MV_5281_D0_REV
564        bge orin2_ddr1_ftdll_val
565    b ddr1_default_val
566
567/* Set Orion 2 D0 and above ftdll values for DDR1 */
568orin2_ddr1_ftdll_val:
569        ldr r4, =FTDLL_DDR1_200MHZ_5281_D0
570    ldr r7, =_200MHz
571        cmp r1, r7
572        beq setFtdllReg
573        ldr r4, =FTDLL_DDR1_166MHZ_5281_D0
574    ldr r7, =_166MHz
575        cmp r1, r7
576        beq setFtdllReg
577    b ddr1_default_val
5782:
579        ldr r2, =MV_5181_DEV_ID
580        cmp r3, r2
581    bne 3f
582        MV_CTRL_REV_GET_ASM(r3, r2)
583        cmp r3, #MV_5181_B1_REV
584        bge orin1_ddr1_ftdll_val
585    b ddr1_default_val
586
587/* Set Orion 1 ftdll values for DDR1 */
588orin1_ddr1_ftdll_val:
589        ldr r4, =FTDLL_DDR1_166MHZ_5181_B1
590    ldr r7, =_166MHz
591        cmp r1, r7
592        beq setFtdllReg
5933:
594ddr1_default_val:
595        ldr r4, =FTDLL_DDR1_133MHZ
596    ldr r7, =_133MHz
597        cmp r1, r7
598        beq setFtdllReg
599
600        ldr r4, =FTDLL_DDR1_166MHZ
601    ldr r7, =_166MHz
602        cmp r1, r7
603        beq setFtdllReg
604
605        ldr r4, =FTDLL_DDR1_200MHZ
606    ldr r7, =_200MHz
607        cmp r1, r7
608        beq setFtdllReg
609
610        ldr r4, =0
611
612setFtdllReg:
613
614        MV_REG_WRITE_ASM (r4, r1, SDRAM_FTDLL_CONFIG_REG)
615        HTOLL(r4,r1)
616        bic r4, r4, #1
617        MV_REG_WRITE_ASM (r4, r1, SDRAM_FTDLL_CONFIG_REG)
618
619#endif /* !defined(MV_88W8660) && !defined(MV_88F6183) && !defined(MV_88F6183L) */
620#endif /* DB_FPGA */
621
622restoreTmpRegs:
623        /* Restore the registers we used to save the DDR detect values */
624
625        ldr r4, =DRAM_BUF_REG0_DV
626        MV_REG_WRITE_ASM (r4, r1, DRAM_BUF_REG0)
627
628        ldr r4, =DRAM_BUF_REG1_DV
629        MV_REG_WRITE_ASM (r4, r1, DRAM_BUF_REG1)
630
631        ldr r4, =DRAM_BUF_REG2_DV
632        MV_REG_WRITE_ASM (r4, r1, DRAM_BUF_REG2)
633
634        ldr r4, =DRAM_BUF_REG3_DV
635        MV_REG_WRITE_ASM (r4, r1, DRAM_BUF_REG3)
636
637        ldr r4, =DRAM_BUF_REG4_DV
638        MV_REG_WRITE_ASM (r4, r1, DRAM_BUF_REG4)
639
640        ldr r4, =DRAM_BUF_REG5_DV
641        MV_REG_WRITE_ASM (r4, r1, DRAM_BUF_REG5)
642
643        ldr r4, =DRAM_BUF_REG6_DV
644        MV_REG_WRITE_ASM (r4, r1, DRAM_BUF_REG6)
645
646        ldr r4, =DRAM_BUF_REG7_DV
647        MV_REG_WRITE_ASM (r4, r1, DRAM_BUF_REG7)
648
649        ldr r4, =DRAM_BUF_REG8_DV
650        MV_REG_WRITE_ASM (r4, r1, DRAM_BUF_REG8)
651
652        ldr r4, =DRAM_BUF_REG9_DV
653        MV_REG_WRITE_ASM (r4, r1, DRAM_BUF_REG9)
654
655        ldr r4, =DRAM_BUF_REG10_DV
656        MV_REG_WRITE_ASM (r4, r1, DRAM_BUF_REG10)
657
658
659        /* Restore registers */
660        /* Save register on stack */
661    cmp sp, #0
662    beq no_stack_l
663load_from_stack:
664        ldmia sp!, {r1, r2, r3, r4, r7, r11}
665no_stack_l:
666
667        mov pc, lr
668
669

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