| 1 | /******************************************************************************* |
| 2 | Copyright (C) Marvell International Ltd. and its affiliates |
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| 24 | Public License Version 2, June 1991 (the "GPL License"), a copy of which is |
| 25 | available along with the File in the license.txt file or by writing to the Free |
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| 38 | Redistribution and use in source and binary forms, with or without modification, |
| 39 | are permitted provided that the following conditions are met: |
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| 41 | * Redistributions of source code must retain the above copyright notice, |
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| 44 | * Redistributions in binary form must reproduce the above copyright |
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| 62 | |
| 63 | *******************************************************************************/ |
| 64 | |
| 65 | |
| 66 | #ifndef __INCmvDramIfh |
| 67 | #define __INCmvDramIfh |
| 68 | |
| 69 | #ifdef __cplusplus |
| 70 | extern "C" { |
| 71 | #endif /* __cplusplus */ |
| 72 | |
| 73 | /* includes */ |
| 74 | #include "ddr2/mvDramIfRegs.h" |
| 75 | #include "ddr2/mvDramIfConfig.h" |
| 76 | #include "ctrlEnv/mvCtrlEnvLib.h" |
| 77 | |
| 78 | /* defines */ |
| 79 | /* DRAM Timing parameters */ |
| 80 | #define SDRAM_TWR 15 /* ns tWr */ |
| 81 | #define SDRAM_TRFC_64_512M_AT_200MHZ 70 /* ns tRfc for dens 64-512 @ 200MHz */ |
| 82 | #define SDRAM_TRFC_64_512M 75 /* ns tRfc for dens 64-512 */ |
| 83 | #define SDRAM_TRFC_1G 120 /* ns tRfc for dens 1GB */ |
| 84 | #define SDRAM_TR2R_CYC 1 /* cycle for tR2r */ |
| 85 | |
| 86 | #define CAL_AUTO_DETECT 0 /* Do not force CAS latancy (mvDramIfDetect) */ |
| 87 | #define ECC_DISABLE 1 /* Force ECC to Disable */ |
| 88 | #define ECC_ENABLE 0 /* Force ECC to ENABLE */ |
| 89 | /* typedefs */ |
| 90 | |
| 91 | /* enumeration for memory types */ |
| 92 | typedef enum _mvMemoryType |
| 93 | { |
| 94 | MEM_TYPE_SDRAM, |
| 95 | MEM_TYPE_DDR1, |
| 96 | MEM_TYPE_DDR2 |
| 97 | }MV_MEMORY_TYPE; |
| 98 | |
| 99 | /* enumeration for DDR2 supported CAS Latencies */ |
| 100 | typedef enum _mvDimmDdr2Cas |
| 101 | { |
| 102 | DDR2_CL_3 = 0x08, |
| 103 | DDR2_CL_4 = 0x10, |
| 104 | DDR2_CL_5 = 0x20, |
| 105 | DDR2_CL_6 = 0x40, |
| 106 | DDR2_CL_FAULT |
| 107 | } MV_DIMM_DDR2_CAS; |
| 108 | |
| 109 | |
| 110 | typedef struct _mvDramBankInfo |
| 111 | { |
| 112 | MV_MEMORY_TYPE memoryType; /* DDR1, DDR2 or SDRAM */ |
| 113 | |
| 114 | /* DIMM dimensions */ |
| 115 | MV_U32 numOfRowAddr; |
| 116 | MV_U32 numOfColAddr; |
| 117 | MV_U32 dataWidth; |
| 118 | MV_U32 errorCheckType; /* ECC , PARITY..*/ |
| 119 | MV_U32 sdramWidth; /* 4,8,16 or 32 */ |
| 120 | MV_U32 errorCheckDataWidth; /* 0 - no, 1 - Yes */ |
| 121 | MV_U32 burstLengthSupported; |
| 122 | MV_U32 numOfBanksOnEachDevice; |
| 123 | MV_U32 suportedCasLatencies; |
| 124 | MV_U32 refreshInterval; |
| 125 | |
| 126 | /* DIMM timing parameters */ |
| 127 | MV_U32 minCycleTimeAtMaxCasLatPs; |
| 128 | MV_U32 minCycleTimeAtMaxCasLatMinus1Ps; |
| 129 | MV_U32 minCycleTimeAtMaxCasLatMinus2Ps; |
| 130 | MV_U32 minRowPrechargeTime; |
| 131 | MV_U32 minRowActiveToRowActive; |
| 132 | MV_U32 minRasToCasDelay; |
| 133 | MV_U32 minRasPulseWidth; |
| 134 | MV_U32 minWriteRecoveryTime; /* DDR2 only */ |
| 135 | MV_U32 minWriteToReadCmdDelay; /* DDR2 only */ |
| 136 | MV_U32 minReadToPrechCmdDelay; /* DDR2 only */ |
| 137 | MV_U32 minRefreshToActiveCmd; /* DDR2 only */ |
| 138 | |
| 139 | /* Parameters calculated from the extracted DIMM information */ |
| 140 | MV_U32 size; |
| 141 | MV_U32 deviceDensity; /* 16,64,128,256 or 512 Mbit */ |
| 142 | MV_U32 numberOfDevices; |
| 143 | |
| 144 | /* DIMM attributes (MV_TRUE for yes) */ |
| 145 | MV_BOOL registeredAddrAndControlInputs; |
| 146 | MV_BOOL registeredDQMBinputs; |
| 147 | |
| 148 | }MV_DRAM_BANK_INFO; |
| 149 | |
| 150 | #include "ddr2/spd/mvSpd.h" |
| 151 | |
| 152 | /* mvDramIf.h API list */ |
| 153 | MV_VOID mvDramIfBasicAsmInit(MV_VOID); |
| 154 | MV_STATUS mvDramIfDetect(MV_U32 forcedCl, MV_BOOL eccDisable); |
| 155 | MV_VOID _mvDramIfConfig(int entryNum); |
| 156 | |
| 157 | MV_U32 mvDramIfBankSizeGet(MV_U32 bankNum); |
| 158 | MV_U32 mvDramIfBankBaseGet(MV_U32 bankNum); |
| 159 | MV_U32 mvDramIfSizeGet(MV_VOID); |
| 160 | MV_U32 mvDramIfCalGet(void); |
| 161 | MV_STATUS mvDramIfSingleBitErrThresholdSet(MV_U32 threshold); |
| 162 | MV_VOID mvDramIfSelfRefreshSet(void); |
| 163 | void mvDramIfShow(void); |
| 164 | MV_U32 mvDramIfGetFirstCS(void); |
| 165 | MV_U32 mvDramIfGetCSorder(MV_U32 csOrder ); |
| 166 | MV_U32 mvDramCsSizeGet(MV_U32 csNum); |
| 167 | |
| 168 | #ifdef __cplusplus |
| 169 | } |
| 170 | #endif /* __cplusplus */ |
| 171 | |
| 172 | #endif /* __INCmvDramIfh */ |
| 173 | |
