| 1 | /******************************************************************************* |
| 2 | Copyright (C) Marvell International Ltd. and its affiliates |
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| 4 | This software file (the "File") is owned and distributed by Marvell |
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| 12 | ******************************************************************************** |
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| 24 | Public License Version 2, June 1991 (the "GPL License"), a copy of which is |
| 25 | available along with the File in the license.txt file or by writing to the Free |
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| 29 | THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED |
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| 38 | Redistribution and use in source and binary forms, with or without modification, |
| 39 | are permitted provided that the following conditions are met: |
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| 41 | * Redistributions of source code must retain the above copyright notice, |
| 42 | this list of conditions and the following disclaimer. |
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| 44 | * Redistributions in binary form must reproduce the above copyright |
| 45 | notice, this list of conditions and the following disclaimer in the |
| 46 | documentation and/or other materials provided with the distribution. |
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| 62 | |
| 63 | *******************************************************************************/ |
| 64 | |
| 65 | |
| 66 | #ifndef __INCmvDramIfConfigh |
| 67 | #define __INCmvDramIfConfigh |
| 68 | |
| 69 | #ifdef __cplusplus |
| 70 | extern "C" { |
| 71 | #endif /* __cplusplus */ |
| 72 | |
| 73 | /* includes */ |
| 74 | |
| 75 | /* defines */ |
| 76 | |
| 77 | /* registers defaults values */ |
| 78 | |
| 79 | #define SDRAM_CONFIG_DV (SDRAM_SRMODE_DRAM | BIT25 | BIT30) |
| 80 | |
| 81 | #define SDRAM_DUNIT_CTRL_LOW_DDR2_DV \ |
| 82 | (SDRAM_SRCLK_KEPT | \ |
| 83 | SDRAM_CLK1DRV_NORMAL | \ |
| 84 | (BIT28 | BIT29)) |
| 85 | |
| 86 | #define SDRAM_ADDR_CTRL_DV 2 |
| 87 | |
| 88 | #define SDRAM_TIMING_CTRL_LOW_REG_DV \ |
| 89 | ((0x2 << SDRAM_TRCD_OFFS) | \ |
| 90 | (0x2 << SDRAM_TRP_OFFS) | \ |
| 91 | (0x1 << SDRAM_TWR_OFFS) | \ |
| 92 | (0x0 << SDRAM_TWTR_OFFS) | \ |
| 93 | (0x5 << SDRAM_TRAS_OFFS) | \ |
| 94 | (0x1 << SDRAM_TRRD_OFFS)) |
| 95 | |
| 96 | /* Note: value of 0 in register means one cycle, 1 means two and so on */ |
| 97 | #define SDRAM_TIMING_CTRL_HIGH_REG_DV \ |
| 98 | ((0x0 << SDRAM_TR2R_OFFS) | \ |
| 99 | (0x0 << SDRAM_TR2W_W2R_OFFS) | \ |
| 100 | (0x1 << SDRAM_TW2W_OFFS)) |
| 101 | |
| 102 | #define SDRAM_OPEN_PAGES_CTRL_REG_DV SDRAM_OPEN_PAGE_EN |
| 103 | |
| 104 | /* Presence Ctrl Low Ctrl High Dunit Ctrl Ext Mode */ |
| 105 | /* CS0 0x84210000 0x00000000 0x0000780F 0x00000440 */ |
| 106 | /* CS0+CS1 0x84210000 0x00000000 0x0000780F 0x00000440 */ |
| 107 | /* CS0+CS2 0x030C030C 0x00000000 0x0000740F 0x00000404 */ |
| 108 | /* CS0+CS1+CS2 0x030C030C 0x00000000 0x0000740F 0x00000404 */ |
| 109 | /* CS0+CS2+CS3 0x030C030C 0x00000000 0x0000740F 0x00000404 */ |
| 110 | /* CS0+CS1+CS2+CS3 0x030C030C 0x00000000 0x0000740F 0x00000404 */ |
| 111 | |
| 112 | #define DDR2_ODT_CTRL_LOW_CS0_CS1_DV 0x84210000 |
| 113 | #define DDR2_ODT_CTRL_HIGH_CS0_CS1_DV 0x00000000 |
| 114 | #define DDR2_DUNIT_ODT_CTRL_CS0_CS1_DV 0x0000E80F |
| 115 | #ifdef MV78XX0 |
| 116 | #define DDR_SDRAM_EXT_MODE_CS0_CS1_DV 0x00000040 |
| 117 | #else |
| 118 | #define DDR_SDRAM_EXT_MODE_CS0_CS1_DV 0x00000440 |
| 119 | #endif |
| 120 | |
| 121 | #define DDR2_ODT_CTRL_LOW_CS0_CS1_CS2_CS3_DV 0x030C030C |
| 122 | #define DDR2_ODT_CTRL_HIGH_CS0_CS1_CS2_CS3_DV 0x00000000 |
| 123 | #define DDR2_DUNIT_ODT_CTRL_CS0_CS1_CS2_CS3_DV 0x0000F40F |
| 124 | #ifdef MV78XX0 |
| 125 | #define DDR_SDRAM_EXT_MODE_CS0_CS1_CS2_CS3_DV 0x00000004 |
| 126 | #define DDR_SDRAM_EXT_MODE_FAST_CS0_CS1_CS2_CS3_DV 0x00000044 |
| 127 | #else |
| 128 | #define DDR_SDRAM_EXT_MODE_CS0_CS1_CS2_CS3_DV 0x00000404 |
| 129 | #define DDR_SDRAM_EXT_MODE_FAST_CS0_CS1_CS2_CS3_DV 0x00000444 |
| 130 | #endif |
| 131 | |
| 132 | /* DDR SDRAM Adderss/Control and Data Pads Calibration default values */ |
| 133 | #define DDR2_ADDR_CTRL_PAD_STRENGTH_TYPICAL_DV \ |
| 134 | (3 << SDRAM_PRE_DRIVER_STRENGTH_OFFS) |
| 135 | |
| 136 | #define DDR2_DATA_PAD_STRENGTH_TYPICAL_DV \ |
| 137 | (3 << SDRAM_PRE_DRIVER_STRENGTH_OFFS) |
| 138 | |
| 139 | /* DDR SDRAM Mode Register default value */ |
| 140 | #define DDR2_MODE_REG_DV (SDRAM_BURST_LEN_4 | SDRAM_WR_3_CYC) |
| 141 | /* DDR SDRAM Timing parameter default values */ |
| 142 | #define SDRAM_TIMING_CTRL_LOW_REG_DEFAULT 0x33136552 |
| 143 | #define SDRAM_TRFC_DEFAULT_VALUE 0x34 |
| 144 | #define SDRAM_TRFC_DEFAULT SDRAM_TRFC_DEFAULT_VALUE |
| 145 | #define SDRAM_TW2W_DEFALT (0x1 << SDRAM_TW2W_OFFS) |
| 146 | |
| 147 | #define SDRAM_TIMING_CTRL_HIGH_REG_DEFAULT (SDRAM_TRFC_DEFAULT | SDRAM_TW2W_DEFALT) |
| 148 | |
| 149 | #define SDRAM_FTDLL_REG_DEFAULT_LEFT 0x88C800 |
| 150 | #define SDRAM_FTDLL_REG_DEFAULT_RIGHT 0x88C800 |
| 151 | #define SDRAM_FTDLL_REG_DEFAULT_UP 0x88C800 |
| 152 | |
| 153 | #ifdef __cplusplus |
| 154 | } |
| 155 | #endif /* __cplusplus */ |
| 156 | |
| 157 | #endif /* __INCmvDramIfh */ |
| 158 | |
