| 1 | /******************************************************************************* |
| 2 | Copyright (C) Marvell International Ltd. and its affiliates |
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| 24 | Public License Version 2, June 1991 (the "GPL License"), a copy of which is |
| 25 | available along with the File in the license.txt file or by writing to the Free |
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| 62 | |
| 63 | *******************************************************************************/ |
| 64 | |
| 65 | #ifndef __INCmvDram |
| 66 | #define __INCmvDram |
| 67 | |
| 68 | #include "ddr2/mvDramIf.h" |
| 69 | #include "twsi/mvTwsi.h" |
| 70 | |
| 71 | #define MAX_DIMM_NUM 2 |
| 72 | #define SPD_SIZE 128 |
| 73 | |
| 74 | /* Dimm spd offsets */ |
| 75 | #define DIMM_MEM_TYPE 2 |
| 76 | #define DIMM_ROW_NUM 3 |
| 77 | #define DIMM_COL_NUM 4 |
| 78 | #define DIMM_MODULE_BANK_NUM 5 |
| 79 | #define DIMM_DATA_WIDTH 6 |
| 80 | #define DIMM_VOLT_IF 8 |
| 81 | #define DIMM_MIN_CC_AT_MAX_CAS 9 |
| 82 | #define DIMM_ERR_CHECK_TYPE 11 |
| 83 | #define DIMM_REFRESH_INTERVAL 12 |
| 84 | #define DIMM_SDRAM_WIDTH 13 |
| 85 | #define DIMM_ERR_CHECK_DATA_WIDTH 14 |
| 86 | #define DIMM_MIN_CLK_DEL 15 |
| 87 | #define DIMM_BURST_LEN_SUP 16 |
| 88 | #define DIMM_DEV_BANK_NUM 17 |
| 89 | #define DIMM_SUP_CAL 18 |
| 90 | #define DIMM_DDR2_TYPE_INFORMATION 20 /* DDR2 only */ |
| 91 | #define DIMM_BUF_ADDR_CONT_IN 21 |
| 92 | #define DIMM_MIN_CC_AT_MAX_CAS_MINUS1 23 |
| 93 | #define DIMM_MIN_CC_AT_MAX_CAS_MINUS2 25 |
| 94 | #define DIMM_MIN_ROW_PRECHARGE_TIME 27 |
| 95 | #define DIMM_MIN_ROW_ACTIVE_TO_ROW_ACTIVE 28 |
| 96 | #define DIMM_MIN_RAS_TO_CAS_DELAY 29 |
| 97 | #define DIMM_MIN_RAS_PULSE_WIDTH 30 |
| 98 | #define DIMM_BANK_DENSITY 31 |
| 99 | #define DIMM_MIN_WRITE_RECOVERY_TIME 36 |
| 100 | #define DIMM_MIN_WRITE_TO_READ_CMD_DELAY 37 |
| 101 | #define DIMM_MIN_READ_TO_PRECH_CMD_DELAY 38 |
| 102 | #define DIMM_MIN_REFRESH_TO_ACTIVATE_CMD 42 |
| 103 | #define DIMM_SPD_VERSION 62 |
| 104 | |
| 105 | /* Dimm Memory Type values */ |
| 106 | #define DIMM_MEM_TYPE_SDRAM 0x4 |
| 107 | #define DIMM_MEM_TYPE_DDR1 0x7 |
| 108 | #define DIMM_MEM_TYPE_DDR2 0x8 |
| 109 | |
| 110 | #define DIMM_MODULE_MANU_OFFS 64 |
| 111 | #define DIMM_MODULE_MANU_SIZE 8 |
| 112 | #define DIMM_MODULE_VEN_OFFS 73 |
| 113 | #define DIMM_MODULE_VEN_SIZE 25 |
| 114 | #define DIMM_MODULE_ID_OFFS 99 |
| 115 | #define DIMM_MODULE_ID_SIZE 18 |
| 116 | |
| 117 | /* enumeration for voltage levels. */ |
| 118 | typedef enum _mvDimmVoltageIf |
| 119 | { |
| 120 | TTL_5V_TOLERANT, |
| 121 | LVTTL, |
| 122 | HSTL_1_5V, |
| 123 | SSTL_3_3V, |
| 124 | SSTL_2_5V, |
| 125 | VOLTAGE_UNKNOWN, |
| 126 | } MV_DIMM_VOLTAGE_IF; |
| 127 | |
| 128 | |
| 129 | /* enumaration for SDRAM CAS Latencies. */ |
| 130 | typedef enum _mvDimmSdramCas |
| 131 | { |
| 132 | SD_CL_1 =1, |
| 133 | SD_CL_2, |
| 134 | SD_CL_3, |
| 135 | SD_CL_4, |
| 136 | SD_CL_5, |
| 137 | SD_CL_6, |
| 138 | SD_CL_7, |
| 139 | SD_FAULT |
| 140 | }MV_DIMM_SDRAM_CAS; |
| 141 | |
| 142 | |
| 143 | /* DIMM information structure */ |
| 144 | typedef struct _mvDimmInfo |
| 145 | { |
| 146 | MV_MEMORY_TYPE memoryType; /* DDR or SDRAM */ |
| 147 | |
| 148 | MV_U8 spdRawData[SPD_SIZE]; /* Content of SPD-EEPROM copied 1:1 */ |
| 149 | |
| 150 | /* DIMM dimensions */ |
| 151 | MV_U32 numOfRowAddr; |
| 152 | MV_U32 numOfColAddr; |
| 153 | MV_U32 numOfModuleBanks; |
| 154 | MV_U32 dataWidth; |
| 155 | MV_U32 errorCheckType; /* ECC , PARITY..*/ |
| 156 | MV_U32 sdramWidth; /* 4,8,16 or 32 */ |
| 157 | MV_U32 errorCheckDataWidth; /* 0 - no, 1 - Yes */ |
| 158 | MV_U32 burstLengthSupported; |
| 159 | MV_U32 numOfBanksOnEachDevice; |
| 160 | MV_U32 suportedCasLatencies; |
| 161 | MV_U32 refreshInterval; |
| 162 | MV_U32 dimmBankDensity; |
| 163 | MV_U32 dimmTypeInfo; /* DDR2 only */ |
| 164 | MV_U32 dimmAttributes; |
| 165 | |
| 166 | /* DIMM timing parameters */ |
| 167 | MV_U32 minCycleTimeAtMaxCasLatPs; |
| 168 | MV_U32 minCycleTimeAtMaxCasLatMinus1Ps; |
| 169 | MV_U32 minCycleTimeAtMaxCasLatMinus2Ps; |
| 170 | MV_U32 minRowPrechargeTime; |
| 171 | MV_U32 minRowActiveToRowActive; |
| 172 | MV_U32 minRasToCasDelay; |
| 173 | MV_U32 minRasPulseWidth; |
| 174 | MV_U32 minWriteRecoveryTime; /* DDR2 only */ |
| 175 | MV_U32 minWriteToReadCmdDelay; /* DDR2 only */ |
| 176 | MV_U32 minReadToPrechCmdDelay; /* DDR2 only */ |
| 177 | MV_U32 minRefreshToActiveCmd; /* DDR2 only */ |
| 178 | |
| 179 | /* Parameters calculated from the extracted DIMM information */ |
| 180 | MV_U32 size; /* 16,64,128,256 or 512 MByte in MB units */ |
| 181 | MV_U32 deviceDensity; /* 16,64,128,256 or 512 Mbit in MB units */ |
| 182 | MV_U32 numberOfDevices; |
| 183 | |
| 184 | } MV_DIMM_INFO; |
| 185 | |
| 186 | |
| 187 | MV_STATUS mvDramBankInfoGet(MV_U32 bankNum, MV_DRAM_BANK_INFO *pBankInfo); |
| 188 | MV_STATUS dimmSpdGet(MV_U32 dimmNum, MV_DIMM_INFO *pDimmInfo); |
| 189 | MV_VOID dimmSpdPrint(MV_U32 dimmNum); |
| 190 | MV_STATUS dimmSpdCpy(MV_VOID); |
| 191 | |
| 192 | #endif /* __INCmvDram */ |
| 193 | |
