Root/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/eth/mvEth.h

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63*******************************************************************************/
64
65/*******************************************************************************
66* mvEth.h - Header File for : Ethernet Controller
67*
68* DESCRIPTION:
69* This header file contains macros typedefs and function declaration for
70* Marvell Gigabit Ethernet Controllers.
71*
72* DEPENDENCIES:
73* None.
74*
75*******************************************************************************/
76
77#ifndef __mvEth_h__
78#define __mvEth_h__
79
80/* includes */
81#include "mvTypes.h"
82#include "mv802_3.h"
83#include "ctrlEnv/mvCtrlEnvLib.h"
84#include "ctrlEnv/mvCtrlEnvAddrDec.h"
85#include "eth/gbe/mvEthRegs.h"
86#include "mvSysHwConfig.h"
87
88/* defines */
89
90#define MV_ETH_EXTRA_FRAGS_NUM 2
91
92
93typedef enum
94{
95    MV_ETH_SPEED_AN,
96    MV_ETH_SPEED_10,
97    MV_ETH_SPEED_100,
98    MV_ETH_SPEED_1000
99    
100} MV_ETH_PORT_SPEED;
101
102typedef enum
103{
104    MV_ETH_DUPLEX_AN,
105    MV_ETH_DUPLEX_HALF,
106    MV_ETH_DUPLEX_FULL
107    
108} MV_ETH_PORT_DUPLEX;
109
110typedef enum
111{
112    MV_ETH_FC_AN_ADV_DIS,
113    MV_ETH_FC_AN_ADV_SYM,
114    MV_ETH_FC_DISABLE,
115    MV_ETH_FC_ENABLE
116
117} MV_ETH_PORT_FC;
118
119typedef enum
120{
121    MV_ETH_PRIO_FIXED = 0, /* Fixed priority mode */
122    MV_ETH_PRIO_WRR = 1 /* Weighted round robin priority mode */
123} MV_ETH_PRIO_MODE;
124
125/* Ethernet port specific infomation */
126typedef struct
127{
128    int maxRxPktSize;
129    int rxDefQ;
130    int rxBpduQ;
131    int rxArpQ;
132    int rxTcpQ;
133    int rxUdpQ;
134    int ejpMode;
135} MV_ETH_PORT_CFG;
136
137typedef struct
138{
139    int descrNum;
140} MV_ETH_RX_Q_CFG;
141
142typedef struct
143{
144    int descrNum;
145    MV_ETH_PRIO_MODE prioMode;
146    int quota;
147} MV_ETH_TX_Q_CFG;
148
149typedef struct
150{
151    int maxRxPktSize;
152    int rxDefQ;
153    int txDescrNum[MV_ETH_TX_Q_NUM];
154    int rxDescrNum[MV_ETH_RX_Q_NUM];
155    void *osHandle;
156} MV_ETH_PORT_INIT;
157
158typedef struct
159{
160    MV_BOOL isLinkUp;
161    MV_ETH_PORT_SPEED speed;
162    MV_ETH_PORT_DUPLEX duplex;
163    MV_ETH_PORT_FC flowControl;
164
165} MV_ETH_PORT_STATUS;
166
167typedef enum
168{
169    MV_ETH_DISABLE_HEADER_MODE = 0,
170    MV_ETH_ENABLE_HEADER_MODE_PRI_2_1 = 1,
171    MV_ETH_ENABLE_HEADER_MODE_PRI_DBNUM = 2,
172    MV_ETH_ENABLE_HEADER_MODE_PRI_SPID = 3
173} MV_ETH_HEADER_MODE;
174
175
176/* ethernet.h API list */
177void mvEthHalInit(void);
178void mvEthMemAttrGet(MV_BOOL* pIsSram, MV_BOOL* pIsSwCoher);
179
180/* Port Initalization routines */
181void* mvEthPortInit (int port, MV_ETH_PORT_INIT *pPortInit);
182void ethResetTxDescRing(void* pPortHndl, int queue);
183void ethResetRxDescRing(void* pPortHndl, int queue);
184
185void* mvEthPortHndlGet(int port);
186
187void mvEthPortFinish(void* pEthPortHndl);
188MV_STATUS mvEthPortDown(void* pEthPortHndl);
189MV_STATUS mvEthPortDisable(void* pEthPortHndl);
190MV_STATUS mvEthPortUp(void* pEthPortHndl);
191MV_STATUS mvEthPortEnable(void* pEthPortHndl);
192
193/* Port data flow routines */
194MV_PKT_INFO *mvEthPortForceTxDone(void* pEthPortHndl, int txQueue);
195MV_PKT_INFO *mvEthPortForceRx(void* pEthPortHndl, int rxQueue);
196
197/* Port Configuration routines */
198MV_STATUS mvEthDefaultsSet(void* pEthPortHndl);
199MV_STATUS mvEthMaxRxSizeSet(void* pPortHndl, int maxRxSize);
200
201/* Port RX MAC Filtering control routines */
202MV_U8 mvEthMcastCrc8Get(MV_U8* pAddr);
203MV_STATUS mvEthRxFilterModeSet(void* pPortHndl, MV_BOOL isPromisc);
204MV_STATUS mvEthMacAddrSet(void* pPortHandle, MV_U8* pMacAddr, int queue);
205MV_STATUS mvEthMcastAddrSet(void* pPortHandle, MV_U8 *pAddr, int queue);
206
207/* MIB Counters APIs */
208MV_U32 mvEthMibCounterRead(void* pPortHndl, unsigned int mibOffset,
209                               MV_U32* pHigh32);
210void mvEthMibCountersClear(void* pPortHandle);
211
212/* TX Scheduling configuration routines */
213MV_STATUS mvEthTxQueueConfig(void* pPortHandle, int txQueue,
214                               MV_ETH_PRIO_MODE txPrioMode, int txQuota);
215
216/* RX Dispatching configuration routines */
217MV_STATUS mvEthBpduRxQueue(void* pPortHandle, int bpduQueue);
218MV_STATUS mvEthVlanPrioRxQueue(void* pPortHandle, int vlanPrio, int vlanPrioQueue);
219MV_STATUS mvEthTosToRxqSet(void* pPortHandle, int tos, int rxq);
220int mvEthTosToRxqGet(void* pPortHandle, int tos);
221
222/* Speed, Duplex, FlowControl routines */
223MV_STATUS mvEthSpeedDuplexSet(void* pPortHandle, MV_ETH_PORT_SPEED speed,
224                                                   MV_ETH_PORT_DUPLEX duplex);
225
226MV_STATUS mvEthFlowCtrlSet(void* pPortHandle, MV_ETH_PORT_FC flowControl);
227
228#if (MV_ETH_VERSION >= 4)
229MV_STATUS mvEthEjpModeSet(void* pPortHandle, int mode);
230#endif /* (MV_ETH_VERSION >= 4) */
231
232void mvEthStatusGet(void* pPortHandle, MV_ETH_PORT_STATUS* pStatus);
233
234/* Marvell Header control */
235MV_STATUS mvEthHeaderModeSet(void* pPortHandle, MV_ETH_HEADER_MODE headerMode);
236
237/* PHY routines */
238void mvEthPhyAddrSet(void* pPortHandle, int phyAddr);
239int mvEthPhyAddrGet(void* pPortHandle);
240
241/* Power management routines */
242void mvEthPortPowerDown(int port);
243void mvEthPortPowerUp(int port);
244
245/******************** ETH PRIVATE ************************/
246
247/*#define UNCACHED_TX_BUFFERS*/
248/*#define UNCACHED_RX_BUFFERS*/
249
250
251/* Port attributes */
252/* Size of a Tx/Rx descriptor used in chain list data structure */
253#define ETH_RX_DESC_ALIGNED_SIZE 32
254#define ETH_TX_DESC_ALIGNED_SIZE 32
255
256#define TX_DISABLE_TIMEOUT_MSEC 1000
257#define RX_DISABLE_TIMEOUT_MSEC 1000
258#define TX_FIFO_EMPTY_TIMEOUT_MSEC 10000
259#define PORT_DISABLE_WAIT_TCLOCKS 5000
260
261/* Macros that save access to desc in order to find next desc pointer */
262#define RX_NEXT_DESC_PTR(pRxDescr, pQueueCtrl) \
263        ((pRxDescr) == (pQueueCtrl)->pLastDescr) ? \
264               (ETH_RX_DESC*)((pQueueCtrl)->pFirstDescr) : \
265               (ETH_RX_DESC*)(((MV_ULONG)(pRxDescr)) + ETH_RX_DESC_ALIGNED_SIZE)
266
267#define TX_NEXT_DESC_PTR(pTxDescr, pQueueCtrl) \
268        ((pTxDescr) == (pQueueCtrl)->pLastDescr) ? \
269               (ETH_TX_DESC*)((pQueueCtrl)->pFirstDescr) : \
270               (ETH_TX_DESC*)(((MV_ULONG)(pTxDescr)) + ETH_TX_DESC_ALIGNED_SIZE)
271
272#define RX_PREV_DESC_PTR(pRxDescr, pQueueCtrl) \
273        ((pRxDescr) == (pQueueCtrl)->pFirstDescr) ? \
274               (ETH_RX_DESC*)((pQueueCtrl)->pLastDescr) : \
275               (ETH_RX_DESC*)(((MV_ULONG)(pRxDescr)) - ETH_RX_DESC_ALIGNED_SIZE)
276
277#define TX_PREV_DESC_PTR(pTxDescr, pQueueCtrl) \
278        ((pTxDescr) == (pQueueCtrl)->pFirstDescr) ? \
279               (ETH_TX_DESC*)((pQueueCtrl)->pLastDescr) : \
280               (ETH_TX_DESC*)(((MV_ULONG)(pTxDescr)) - ETH_TX_DESC_ALIGNED_SIZE)
281
282
283/* Queue specific information */
284typedef struct
285{
286    void* pFirstDescr;
287    void* pLastDescr;
288    void* pCurrentDescr;
289    void* pUsedDescr;
290    int resource;
291    MV_BUF_INFO descBuf;
292} ETH_QUEUE_CTRL;
293
294
295/* Ethernet port specific infomation */
296typedef struct _ethPortCtrl
297{
298    int portNo;
299    ETH_QUEUE_CTRL rxQueue[MV_ETH_RX_Q_NUM]; /* Rx ring resource */
300    ETH_QUEUE_CTRL txQueue[MV_ETH_TX_Q_NUM]; /* Tx ring resource */
301
302    MV_ETH_PORT_CFG portConfig;
303    MV_ETH_RX_Q_CFG rxQueueConfig[MV_ETH_RX_Q_NUM];
304    MV_ETH_TX_Q_CFG txQueueConfig[MV_ETH_TX_Q_NUM];
305
306    /* Register images - For DP */
307    MV_U32 portTxQueueCmdReg; /* Port active Tx queues summary */
308    MV_U32 portRxQueueCmdReg; /* Port active Rx queues summary */
309
310    MV_STATE portState;
311
312    MV_U8 mcastCount[256];
313    MV_U32* hashPtr;
314    void *osHandle;
315} ETH_PORT_CTRL;
316
317/************** MACROs ****************/
318
319/* MACROs to Flush / Invalidate TX / RX Buffers */
320#if (ETHER_DRAM_COHER == MV_CACHE_COHER_SW) && !defined(UNCACHED_TX_BUFFERS)
321# define ETH_PACKET_CACHE_FLUSH(pAddr, size) \
322        mvOsCacheClear(NULL, (pAddr), (size)); \
323        /*CPU_PIPE_FLUSH;*/
324#else
325# define ETH_PACKET_CACHE_FLUSH(pAddr, size) \
326        mvOsIoVirtToPhy(NULL, (pAddr));
327#endif /* ETHER_DRAM_COHER == MV_CACHE_COHER_SW */
328
329#if ( (ETHER_DRAM_COHER == MV_CACHE_COHER_SW) && !defined(UNCACHED_RX_BUFFERS) )
330# define ETH_PACKET_CACHE_INVALIDATE(pAddr, size) \
331        mvOsCacheInvalidate (NULL, (pAddr), (size)); \
332        /*CPU_PIPE_FLUSH;*/
333#else
334# define ETH_PACKET_CACHE_INVALIDATE(pAddr, size)
335#endif /* ETHER_DRAM_COHER == MV_CACHE_COHER_SW && !UNCACHED_RX_BUFFERS */
336
337#ifdef ETH_DESCR_UNCACHED
338
339#define ETH_DESCR_FLUSH_INV(pPortCtrl, pDescr)
340#define ETH_DESCR_INV(pPortCtrl, pDescr)
341
342#else
343
344#define ETH_DESCR_FLUSH_INV(pPortCtrl, pDescr) \
345        mvOsCacheLineFlushInv(pPortCtrl->osHandle, (MV_ULONG)(pDescr))
346
347#define ETH_DESCR_INV(pPortCtrl, pDescr) \
348        mvOsCacheLineInv(pPortCtrl->osHandle, (MV_ULONG)(pDescr))
349
350#endif /* ETH_DESCR_UNCACHED */
351
352#include "eth/gbe/mvEthGbe.h"
353
354#endif /* __mvEth_h__ */
355
356
357

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