Root/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/pex/mvPexRegs.h

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63*******************************************************************************/
64
65#ifndef __INCPEXREGSH
66#define __INCPEXREGSH
67
68#ifdef __cplusplus
69extern "C" {
70#endif /* __cplusplus */
71
72/* defines */
73#define MAX_PEX_DEVICES 32
74#define MAX_PEX_FUNCS 8
75#define MAX_PEX_BUSSES 256
76
77
78
79/*********************************************************/
80/* PCI Express Configuration Cycles Generation Registers */
81/*********************************************************/
82
83#define PEX_CFG_ADDR_REG(pexIf) ((PEX_IF_BASE(pexIf)) + 0x18F8)
84#define PEX_CFG_DATA_REG(pexIf) ((PEX_IF_BASE(pexIf)) + 0x18FC)
85#define PEX_PHY_ACCESS_REG(pexIf) ((PEX_IF_BASE(pexIf)) + 0x1B00)
86/* PCI Express Configuration Address Register */
87/* PEX_CFG_ADDR_REG (PXCAR)*/
88
89#define PXCAR_REG_NUM_OFFS 2
90#define PXCAR_REG_NUM_MAX 0x3F
91#define PXCAR_REG_NUM_MASK (PXCAR_REG_NUM_MAX << PXCAR_REG_NUM_OFFS)
92#define PXCAR_FUNC_NUM_OFFS 8
93#define PXCAR_FUNC_NUM_MAX 0x7
94#define PXCAR_FUNC_NUM_MASK (PXCAR_FUNC_NUM_MAX << PXCAR_FUNC_NUM_OFFS)
95#define PXCAR_DEVICE_NUM_OFFS 11
96#define PXCAR_DEVICE_NUM_MAX 0x1F
97#define PXCAR_DEVICE_NUM_MASK (PXCAR_DEVICE_NUM_MAX << PXCAR_DEVICE_NUM_OFFS)
98#define PXCAR_BUS_NUM_OFFS 16
99#define PXCAR_BUS_NUM_MAX 0xFF
100#define PXCAR_BUS_NUM_MASK (PXCAR_BUS_NUM_MAX << PXCAR_BUS_NUM_OFFS)
101#define PXCAR_EXT_REG_NUM_OFFS 24
102#define PXCAR_EXT_REG_NUM_MAX 0xF
103
104/* in pci express register address is now the legacy register address (8 bits)
105with the new extended register address (more 4 bits) , below is the mask of
106the upper 4 bits of the full register address */
107
108#define PXCAR_REAL_EXT_REG_NUM_OFFS 8
109#define PXCAR_EXT_REG_NUM_MASK (PXCAR_EXT_REG_NUM_MAX << PXCAR_EXT_REG_NUM_OFFS)
110#define PXCAR_CONFIG_EN BIT31
111
112#define PXCAR_REAL_EXT_REG_NUM_OFFS 8
113#define PXCAR_REAL_EXT_REG_NUM_MASK (0xF << PXCAR_REAL_EXT_REG_NUM_OFFS)
114
115/* The traditional PCI spec defined 6-bit field to describe register offset.*/
116/* The new PCI Express extend the register offset by an extra 4-bits. */
117/* The below macro assign 10-bit register offset into the apprpreate */
118/* fields in the CFG_ADDR_REG */
119#define PXCAR_REG_OFFS_SET(regOffs) \
120 ( (regOff & PXCAR_REG_NUM_MASK) | \
121   ( ((regOff & PXCAR_REAL_EXT_REG_NUM_MASK) >> PXCAR_REAL_EXT_REG_NUM_OFFS) << PXCAR_EXT_REG_NUM_OFFS) )
122
123/***********************************/
124/* PCI Express Interrupt registers */
125/***********************************/
126#define PEX_CAUSE_REG(pexIf) ((PEX_IF_BASE(pexIf)) + 0x1900)
127#define PEX_MASK_REG(pexIf) ((PEX_IF_BASE(pexIf)) + 0x1910)
128
129#define PXICR_TX_REQ_IN_DLDOWN_ERR BIT0 /* Transmit request while field */
130                                          /* <DLDown> of the PCI Express */
131/* PCI Express Interrupt Cause */
132/* PEX_INT_CAUSE_REG (PXICR)*/
133/* PEX_INT_MASK_REG*/
134/*
135NOTE:All bits except bits[27:24] are Read/Write Clear only. A cause bit sets
136upon an error event occurrence. A write of 0 clears the bit. A write of 1 has
137no affect. Bits[24:27} are set and cleared upon reception of interrupt
138emulation messages.
139
140Mask bit per cause bit. If a bit is set to 1, the corresponding event is
141enabled. Mask does not affect setting of the Interrupt Cause register bits;
142it only affects the assertion of the interrupt .*/
143                                          
144
145#define PXICR_MDIS_CAUSE BIT1 /* Attempt to generate PCI transaction
146                                             while master is disabled */
147#define PXICR_ERR_WRTO_REG_CAUSE BIT3 /* Erroneous write attempt to
148                                             PCI Express internal register*/
149#define PXICR_HIT_DFLT_WIN_ERR BIT4 /* Hit Default Window Error */
150#define PXICR_RX_RAM_PAR_ERR BIT6 /* Rx RAM Parity Error */
151#define PXICR_TX_RAM_PAR_ERR BIT7 /* Tx RAM Parity Error */
152#define PXICR_COR_ERR_DET BIT8 /* Correctable Error Detected*/
153#define PXICR_NF_ERR_DET BIT9 /* Non-Fatal Error Detected*/
154#define PXICR_FERR_DET BIT10 /* Fatal Error Detected*/
155#define PXICR_DSTATE_CHANGE BIT11 /* Dstate Change Indication*/
156#define PXICR_BIST BIT12 /* PCI-Express BIST activated*/
157#define PXICR_FLW_CTRL_PROT BIT14 /* Flow Control Protocol Error */
158
159#define PXICR_RCV_UR_CA_ERR BIT15 /* Received UR or CA status. */
160#define PXICR_RCV_ERR_FATAL BIT16 /* Received ERR_FATAL message.*/
161#define PXICR_RCV_ERR_NON_FATAL BIT17 /* Received ERR_NONFATAL message*/
162#define PXICR_RCV_ERR_COR BIT18 /* Received ERR_COR message.*/
163#define PXICR_RCV_CRS BIT19 /* Received CRS completion status*/
164#define PXICR_SLV_HOT_RESET BIT20 /* Received Hot Reset Indication*/
165#define PXICR_SLV_DIS_LINK BIT21 /* Slave Disable Link Indication*/
166#define PXICR_SLV_LB BIT22 /* Slave Loopback Indication*/
167#define PXICR_LINK_FAIL BIT23 /* Link Failure indication.*/
168#define PXICR_RCV_INTA BIT24 /* IntA status.*/
169#define PXICR_RCV_INTB BIT25 /* IntB status.*/
170#define PXICR_RCV_INTC BIT26 /* IntC status.*/
171#define PXICR_RCV_INTD BIT27 /* IntD status.*/
172#define PXICR_RCV_PM_PME BIT28 /* Received PM_PME message. */
173
174
175/********************************************/
176/* PCI Express Control and Status Registers */
177/********************************************/
178#define PEX_CTRL_REG(pexIf) ((PEX_IF_BASE(pexIf)) + 0x1A00)
179#define PEX_STATUS_REG(pexIf) ((PEX_IF_BASE(pexIf)) + 0x1A04)
180#define PEX_COMPLT_TMEOUT_REG(pexIf) ((PEX_IF_BASE(pexIf)) + 0x1A10)
181#define PEX_PWR_MNG_EXT_REG(pexIf) ((PEX_IF_BASE(pexIf)) + 0x1A18)
182#define PEX_FLOW_CTRL_REG(pexIf) ((PEX_IF_BASE(pexIf)) + 0x1A20)
183#define PEX_ACK_TMR_4X_REG(pexIf) ((PEX_IF_BASE(pexIf)) + 0x1A30)
184#define PEX_ACK_TMR_1X_REG(pexIf) ((PEX_IF_BASE(pexIf)) + 0x1A40)
185#define PEX_TL_CTRL_REG(pexIf) ((PEX_IF_BASE(pexIf)) + 0x1AB0)
186
187
188#define PEX_RAM_PARITY_CTRL_REG(pexIf) ((PEX_IF_BASE(pexIf)) + 0x1A50)
189/* PCI Express Control Register */
190/* PEX_CTRL_REG (PXCR) */
191
192#define PXCR_CONF_LINK_OFFS 0
193#define PXCR_CONF_LINK_MASK (1 << PXCR_CONF_LINK_OFFS)
194#define PXCR_CONF_LINK_X4 (0 << PXCR_CONF_LINK_OFFS)
195#define PXCR_CONF_LINK_X1 (1 << PXCR_CONF_LINK_OFFS)
196#define PXCR_DEV_TYPE_CTRL_OFFS 1 /*PCI ExpressDevice Type Control*/
197#define PXCR_DEV_TYPE_CTRL_MASK BIT1
198#define PXCR_DEV_TYPE_CTRL_CMPLX (1 << PXCR_DEV_TYPE_CTRL_OFFS)
199#define PXCR_DEV_TYPE_CTRL_POINT (0 << PXCR_DEV_TYPE_CTRL_OFFS)
200#define PXCR_CFG_MAP_TO_MEM_EN BIT2 /* Configuration Header Mapping
201                                               to Memory Space Enable */
202
203#define PXCR_CFG_MAP_TO_MEM_EN BIT2 /* Configuration Header Mapping
204                                               to Memory Space Enable*/
205
206#define PXCR_RSRV1_OFFS 5
207#define PXCR_RSRV1_MASK (0x7 << PXCR_RSRV1_OFFS)
208#define PXCR_RSRV1_VAL (0x0 << PXCR_RSRV1_OFFS)
209
210#define PXCR_CONF_MAX_OUTSTND_OFFS 8 /*Maximum outstanding NP requests as a master*/
211#define PXCR_CONF_MAX_OUTSTND_MASK (0x3 << PXCR_CONF_MAX_OUTSTND_OFFS)
212
213
214#define PXCR_CONF_NFTS_OFFS 16 /*number of FTS Ordered-Sets*/
215#define PXCR_CONF_NFTS_MASK (0xff << PXCR_CONF_NFTS_OFFS)
216
217#define PXCR_CONF_MSTR_HOT_RESET BIT24 /*Master Hot-Reset.*/
218#define PXCR_CONF_MSTR_LB BIT26 /* Master Loopback */
219#define PXCR_CONF_MSTR_DIS_SCRMB BIT27 /* Master Disable Scrambling*/
220#define PXCR_CONF_DIRECT_DIS_SCRMB BIT28 /* Direct Disable Scrambling*/
221
222/* PCI Express Status Register */
223/* PEX_STATUS_REG (PXSR) */
224
225#define PXSR_DL_DOWN BIT0 /* DL_Down indication.*/
226
227#define PXSR_PEX_BUS_NUM_OFFS 8 /* Bus Number Indication */
228#define PXSR_PEX_BUS_NUM_MASK (0xff << PXSR_PEX_BUS_NUM_OFFS)
229
230#define PXSR_PEX_DEV_NUM_OFFS 16 /* Device Number Indication */
231#define PXSR_PEX_DEV_NUM_MASK (0x1f << PXSR_PEX_DEV_NUM_OFFS)
232
233#define PXSR_PEX_SLV_HOT_RESET BIT24 /* Slave Hot Reset Indication*/
234#define PXSR_PEX_SLV_DIS_LINK BIT25 /* Slave Disable Link Indication*/
235#define PXSR_PEX_SLV_LB BIT26 /* Slave Loopback Indication*/
236#define PXSR_PEX_SLV_DIS_SCRMB BIT27 /* Slave Disable Scrambling Indication*/
237
238
239/* PCI Express Completion Timeout Register */
240/* PEX_COMPLT_TMEOUT_REG (PXCTR)*/
241
242#define PXCTR_CMP_TO_THRSHLD_OFFS 0 /* Completion Timeout Threshold */
243#define PXCTR_CMP_TO_THRSHLD_MASK (0xffff << PXCTR_CMP_TO_THRSHLD_OFFS)
244
245/* PCI Express Power Management Extended Register */
246/* PEX_PWR_MNG_EXT_REG (PXPMER) */
247
248#define PXPMER_L1_ASPM_EN_OFFS 1
249#define PXPMER_L1_ASPM_EN_MASK (0x1 << PXPMER_L1_ASPM_EN_OFFS)
250
251/* PCI Express Flow Control Register */
252/* PEX_FLOW_CTRL_REG (PXFCR)*/
253
254#define PXFCR_PH_INIT_FC_OFFS 0 /*Posted Headers Flow Control Credit
255                                            Initial Value.*/
256#define PXFCR_PH_INIT_FC_MASK (0xff << PXFCR_PH_INIT_FC_OFFS)
257
258
259#define PXFCR_NPH_INIT_FC_OFFS 8 /* Classified Non-Posted Headers
260                                             Flow Control Credit Initial Value*/
261#define PXFCR_NPH_INIT_FC_MASK (0xff << PXFCR_NPH_INIT_FC_OFFS)
262
263#define PXFCR_CH_INIT_FC_OFFS 16 /* Completion Headers Flow Control
264                                              Credit Initial Value Infinite*/
265                                        
266#define PXFCR_CH_INIT_FC_MASK (0xff << PXFCR_CH_INIT_FC_OFFS)
267
268#define PXFCR_FC_UPDATE_TO_OFFS 24 /* Flow Control Update Timeout */
269#define PXFCR_FC_UPDATE_TO_MASK (0xff << PXFCR_FC_UPDATE_TO_OFFS)
270
271/* PCI Express Acknowledge Timers (4X) Register */
272/* PEX_ACK_TMR_4X_REG (PXAT4R) */
273#define PXAT1R_ACK_LAT_TOX4_OFFS 0 /* Ack Latency Timer Timeout Value */
274#define PXAT1R_ACK_LAT_TOX4_MASK (0xffff << PXAT4R_ACK_LAT_TOX1_OFFS)
275#define PXAT1R_ACK_RPLY_TOX4_OFFS 16 /* Ack Replay Timer Timeout Value */
276#define PXAT1R_ACK_RPLY_TOX4_MASK (0xffff << PXAT1R_ACK_RPLY_TOX1_OFFS)
277
278/* PCI Express Acknowledge Timers (1X) Register */
279/* PEX_ACK_TMR_1X_REG (PXAT1R) */
280
281#define PXAT1R_ACK_LAT_TOX1_OFFS 0 /* Acknowledge Latency Timer Timeout
282                                             Value for 1X Link*/
283#define PXAT1R_ACK_LAT_TOX1_MASK (0xffff << PXAT1R_ACK_LAT_TOX1_OFFS)
284
285#define PXAT1R_ACK_RPLY_TOX1_OFFS 16 /* Acknowledge Replay Timer Timeout
286                                              Value for 1X*/
287#define PXAT1R_ACK_RPLY_TOX1_MASK (0xffff << PXAT1R_ACK_RPLY_TOX1_OFFS)
288
289
290/* PCI Express TL Control Register */
291/* PEX_TL_CTRL_REG (PXTCR) */
292
293#define PXTCR_TX_CMP_BUFF_NO_OFFS 8 /*Number of completion buffers in Tx*/
294#define PXTCR_TX_CMP_BUFF_NO_MASK (0xf << PXTCR_TX_CMP_BUFF_NO_OFFS)
295
296/* PCI Express Debug MAC Control Register */
297/* PEX_DEBUG_MAC_CTRL_REG (PXDMCR) */
298
299#define PXDMCR_LINKUP BIT4
300
301
302
303/**********************************************/
304/* PCI Express Configuration Header Registers */
305/**********************************************/
306#define PEX_CFG_DIRECT_ACCESS(pexIf,cfgReg) ((PEX_IF_BASE(pexIf)) + (cfgReg))
307
308#define PEX_DEVICE_AND_VENDOR_ID 0x000
309#define PEX_STATUS_AND_COMMAND 0x004
310#define PEX_CLASS_CODE_AND_REVISION_ID 0x008
311#define PEX_BIST_HDR_TYPE_LAT_TMR_CACHE_LINE 0x00C
312#define PEX_MEMORY_BAR_BASE_ADDR(barNum) (0x010 + ((barNum) << 2))
313#define PEX_MV_BAR_BASE(barNum) (0x010 + (barNum) * 8)
314#define PEX_MV_BAR_BASE_HIGH(barNum) (0x014 + (barNum) * 8)
315#define PEX_BAR0_INTER_REG 0x010
316#define PEX_BAR0_INTER_REG_HIGH 0x014
317#define PEX_BAR1_REG 0x018
318#define PEX_BAR1_REG_HIGH 0x01C
319#define PEX_BAR2_REG 0x020
320#define PEX_BAR2_REG_HIGH 0x024
321
322#define PEX_SUBSYS_ID_AND_SUBSYS_VENDOR_ID 0x02C
323#define PEX_EXPANSION_ROM_BASE_ADDR_REG 0x030
324#define PEX_CAPABILTY_LIST_POINTER 0x034
325#define PEX_INTERRUPT_PIN_AND_LINE 0x03C
326
327/* capability list */
328#define PEX_POWER_MNG_CAPABILITY 0x040
329#define PEX_POWER_MNG_STATUS_CONTROL 0x044
330
331#define PEX_MSI_MESSAGE_CONTROL 0x050
332#define PEX_MSI_MESSAGE_ADDR 0x054
333#define PEX_MSI_MESSAGE_HIGH_ADDR 0x058
334#define PEX_MSI_MESSAGE_DATA 0x05C
335
336#define PEX_CAPABILITY_REG 0x60
337#define PEX_DEV_CAPABILITY_REG 0x64
338#define PEX_DEV_CTRL_STAT_REG 0x68
339#define PEX_LINK_CAPABILITY_REG 0x6C
340#define PEX_LINK_CTRL_STAT_REG 0x70
341
342#define PEX_ADV_ERR_RPRT_HDR_TRGT_REG 0x100
343#define PEX_UNCORRECT_ERR_STAT_REG 0x104
344#define PEX_UNCORRECT_ERR_MASK_REG 0x108
345#define PEX_UNCORRECT_ERR_SERVITY_REG 0x10C
346#define PEX_CORRECT_ERR_STAT_REG 0x110
347#define PEX_CORRECT_ERR_MASK_REG 0x114
348#define PEX_ADV_ERR_CAPABILITY_CTRL_REG 0x118
349#define PEX_HDR_LOG_FIRST_DWORD_REG 0x11C
350#define PEX_HDR_LOG_SECOND_DWORD_REG 0x120
351#define PEX_HDR_LOG_THIRD_DWORD_REG 0x124
352#define PEX_HDR_LOG_FOURTH_DWORD_REG 0x128
353
354
355
356/* PCI Express Device and Vendor ID Register*/
357/*PEX_DEVICE_AND_VENDOR_ID (PXDAVI)*/
358
359#define PXDAVI_VEN_ID_OFFS 0 /* Vendor ID */
360#define PXDAVI_VEN_ID_MASK (0xffff << PXDAVI_VEN_ID_OFFS)
361
362#define PXDAVI_DEV_ID_OFFS 16 /* Device ID */
363#define PXDAVI_DEV_ID_MASK (0xffff << PXDAVI_DEV_ID_OFFS)
364
365
366/* PCI Express Command and Status Register*/
367/*PEX_STATUS_AND_COMMAND (PXSAC)*/
368
369#define PXSAC_IO_EN BIT0 /* IO Enable */
370#define PXSAC_MEM_EN BIT1 /* Memory Enable */
371#define PXSAC_MASTER_EN BIT2 /* Master Enable */
372#define PXSAC_PERR_EN BIT6 /* Parity Errors Respond Enable */
373#define PXSAC_SERR_EN BIT8 /* Ability to assert SERR# line */
374#define PXSAC_INT_DIS BIT10 /* Interrupt Disable */
375#define PXSAC_INT_STAT BIT19 /* Interrupt Status */
376#define PXSAC_CAP_LIST BIT20 /* Capability List Support */
377#define PXSAC_MAS_DATA_PERR BIT24 /* Master Data Parity Error */
378#define PXSAC_SLAVE_TABORT BIT27 /* Signalled Target Abort */
379#define PXSAC_RT_ABORT BIT28 /* Recieved Target Abort */
380#define PXSAC_MABORT BIT29 /* Recieved Master Abort */
381#define PXSAC_SYSERR BIT30 /* Signalled system error */
382#define PXSAC_DET_PARERR BIT31 /* Detect Parity Error */
383
384
385/* PCI Express Class Code and Revision ID Register*/
386/*PEX_CLASS_CODE_AND_REVISION_ID (PXCCARI)*/
387
388#define PXCCARI_REVID_OFFS 0 /* Revision ID */
389#define PXCCARI_REVID_MASK (0xff << PXCCARI_REVID_OFFS)
390
391#define PXCCARI_FULL_CLASS_OFFS 8 /* Full Class Code */
392#define PXCCARI_FULL_CLASS_MASK (0xffffff << PXCCARI_FULL_CLASS_OFFS)
393
394#define PXCCARI_PROGIF_OFFS 8 /* Prog .I/F*/
395#define PXCCARI_PROGIF_MASK (0xff << PXCCARI_PROGIF_OFFS)
396
397#define PXCCARI_SUB_CLASS_OFFS 16 /* Sub Class*/
398#define PXCCARI_SUB_CLASS_MASK (0xff << PXCCARI_SUB_CLASS_OFFS)
399
400#define PXCCARI_BASE_CLASS_OFFS 24 /* Base Class*/
401#define PXCCARI_BASE_CLASS_MASK (0xff << PXCCARI_BASE_CLASS_OFFS)
402
403
404/* PCI Express BIST, Header Type and Cache Line Size Register*/
405/*PEX_BIST_HDR_TYPE_LAT_TMR_CACHE_LINE (PXBHTLTCL)*/
406
407#define PXBHTLTCL_CACHELINE_OFFS 0 /* Specifies the cache line size */
408#define PXBHTLTCL_CACHELINE_MASK (0xff << PXBHTLTCL_CACHELINE_OFFS)
409
410#define PXBHTLTCL_HEADTYPE_FULL_OFFS 16 /* Full Header Type */
411#define PXBHTLTCL_HEADTYPE_FULL_MASK (0xff << PXBHTLTCL_HEADTYPE_FULL_OFFS)
412
413#define PXBHTLTCL_MULTI_FUNC BIT23 /* Multi/Single function */
414
415#define PXBHTLTCL_HEADER_OFFS 16 /* Header type */
416#define PXBHTLTCL_HEADER_MASK (0x7f << PXBHTLTCL_HEADER_OFFS)
417#define PXBHTLTCL_HEADER_STANDARD (0x0 << PXBHTLTCL_HEADER_OFFS)
418#define PXBHTLTCL_HEADER_PCI2PCI_BRIDGE (0x1 << PXBHTLTCL_HEADER_OFFS)
419
420
421#define PXBHTLTCL_BISTCOMP_OFFS 24 /* BIST Completion Code */
422#define PXBHTLTCL_BISTCOMP_MASK (0xf << PXBHTLTCL_BISTCOMP_OFFS)
423
424#define PXBHTLTCL_BISTACT BIT30 /* BIST Activate bit */
425#define PXBHTLTCL_BISTCAP BIT31 /* BIST Capable Bit */
426#define PXBHTLTCL_BISTCAP_OFFS 31
427#define PXBHTLTCL_BISTCAP_MASK BIT31
428#define PXBHTLTCL_BISTCAP_VAL 0
429
430
431/* PCI Express Subsystem Device and Vendor ID */
432/*PEX_SUBSYS_ID_AND_SUBSYS_VENDOR_ID (PXSIASVI)*/
433
434#define PXSIASVI_VENID_OFFS 0 /* Subsystem Manufacturer Vendor ID Number */
435#define PXSIASVI_VENID_MASK (0xffff << PXSIASVI_VENID_OFFS)
436
437#define PXSIASVI_DEVID_OFFS 16 /* Subsystem Device ID Number */
438#define PXSIASVI_DEVID_MASK (0xffff << PXSIASVI_DEVID_OFFS)
439
440
441/* PCI Express Capability List Pointer Register*/
442/*PEX_CAPABILTY_LIST_POINTER (PXCLP)*/
443
444#define PXCLP_CAPPTR_OFFS 0 /* Capability List Pointer */
445#define PXCLP_CAPPTR_MASK (0xff << PXCLP_CAPPTR_OFFS)
446
447/* PCI Express Interrupt Pin and Line Register */
448/*PEX_INTERRUPT_PIN_AND_LINE (PXIPAL)*/
449
450#define PXIPAL_INTLINE_OFFS 0 /* Interrupt line (IRQ) */
451#define PXIPAL_INTLINE_MASK (0xff << PXIPAL_INTLINE_OFFS)
452
453#define PXIPAL_INTPIN_OFFS 8 /* interrupt pin (A,B,C,D) */
454#define PXIPAL_INTPIN_MASK (0xff << PXIPAL_INTPIN_OFFS)
455
456
457/* PCI Express Power Management Capability Header Register*/
458/*PEX_POWER_MNG_CAPABILITY (PXPMC)*/
459
460#define PXPMC_CAP_ID_OFFS 0 /* Capability ID */
461#define PXPMC_CAP_ID_MASK (0xff << PXPMC_CAP_ID_OFFS)
462
463#define PXPMC_NEXT_PTR_OFFS 8 /* Next Item Pointer */
464#define PXPMC_NEXT_PTR_MASK (0xff << PXPMC_NEXT_PTR_OFFS)
465
466#define PXPMC_PMC_VER_OFFS 16 /* PCI Power Management Capability Version*/
467#define PXPMC_PMC_VER_MASK (0x7 << PXPMC_PMC_VER_OFFS)
468
469#define PXPMC_DSI BIT21/* Device Specific Initialization */
470
471#define PXPMC_AUX_CUR_OFFS 22 /* Auxiliary Current Requirements */
472#define PXPMC_AUX_CUR_MASK (0x7 << PXPMC_AUX_CUR_OFFS)
473
474#define PXPMC_D1_SUP BIT25 /* D1 Power Management support*/
475
476#define PXPMC_D2_SUP BIT26 /* D2 Power Management support*/
477
478#define PXPMC_PME_SUP_OFFS 27 /* PM Event generation support*/
479#define PXPMC_PME_SUP_MASK (0x1f << PXPMC_PME_SUP_OFFS)
480
481/* PCI Express Power Management Control and Status Register*/
482/*PEX_POWER_MNG_STATUS_CONTROL (PXPMSC)*/
483
484#define PXPMSC_PM_STATE_OFFS 0 /* Power State */
485#define PXPMSC_PM_STATE_MASK (0x3 << PXPMSC_PM_STATE_OFFS)
486#define PXPMSC_PM_STATE_D0 (0x0 << PXPMSC_PM_STATE_OFFS)
487#define PXPMSC_PM_STATE_D1 (0x1 << PXPMSC_PM_STATE_OFFS)
488#define PXPMSC_PM_STATE_D2 (0x2 << PXPMSC_PM_STATE_OFFS)
489#define PXPMSC_PM_STATE_D3 (0x3 << PXPMSC_PM_STATE_OFFS)
490
491#define PXPMSC_PME_EN BIT8/* PM_PME Message Generation Enable */
492
493#define PXPMSC_PM_DATA_SEL_OFFS 9 /* Data Select*/
494#define PXPMSC_PM_DATA_SEL_MASK (0xf << PXPMSC_PM_DATA_SEL_OFFS)
495
496#define PXPMSC_PM_DATA_SCALE_OFFS 13 /* Data Scale */
497#define PXPMSC_PM_DATA_SCALE_MASK (0x3 << PXPMSC_PM_DATA_SCALE_OFFS)
498
499#define PXPMSC_PME_STAT BIT15/* PME Status */
500
501#define PXPMSC_PM_DATA_OFFS 24 /* State Data */
502#define PXPMSC_PM_DATA_MASK (0xff << PXPMSC_PM_DATA_OFFS)
503
504
505/* PCI Express MSI Message Control Register*/
506/*PEX_MSI_MESSAGE_CONTROL (PXMMC)*/
507
508#define PXMMC_CAP_ID_OFFS 0 /* Capability ID */
509#define PXMMC_CAP_ID_MASK (0xff << PXMMC_CAP_ID_OFFS)
510
511#define PXMMC_NEXT_PTR_OFFS 8 /* Next Item Pointer */
512#define PXMMC_NEXT_PTR_MASK (0xff << PXMMC_NEXT_PTR_OFFS)
513
514#define PXMMC_MSI_EN BIT18 /* MSI Enable */
515
516#define PXMMC_MULTI_CAP_OFFS 17 /* Multiple Message Capable */
517#define PXMMC_MULTI_CAP_MASK (0x7 << PXMMC_MULTI_CAP_OFFS)
518
519#define PXMMC_MULTI_EN_OFFS 20 /* Multiple Messages Enable */
520#define PXMMC_MULTI_EN_MASK (0x7 << PXMMC_MULTI_EN_OFFS)
521
522#define PXMMC_ADDR64 BIT23 /* 64-bit Addressing Capable */
523
524
525/* PCI Express MSI Message Address Register*/
526/*PEX_MSI_MESSAGE_ADDR (PXMMA)*/
527
528#define PXMMA_MSI_ADDR_OFFS 2 /* Message Address corresponds to
529                                        Address[31:2] of the MSI MWr TLP*/
530#define PXMMA_MSI_ADDR_MASK (0x3fffffff << PXMMA_MSI_ADDR_OFFS)
531
532
533/* PCI Express MSI Message Address (High) Register */
534/*PEX_MSI_MESSAGE_HIGH_ADDR (PXMMHA)*/
535
536#define PXMMA_MSI_ADDR_H_OFFS 0 /* Message Upper Address corresponds to
537                                            Address[63:32] of the MSI MWr TLP*/
538#define PXMMA_MSI_ADDR_H_MASK (0xffffffff << PXMMA_MSI_ADDR_H_OFFS )
539
540
541/* PCI Express MSI Message Data Register*/
542/*PEX_MSI_MESSAGE_DATA (PXMMD)*/
543
544#define PXMMD_MSI_DATA_OFFS 0 /* Message Data */
545#define PXMMD_MSI_DATA_MASK (0xffff << PXMMD_MSI_DATA_OFFS )
546
547
548/* PCI Express Capability Register*/
549/*PEX_CAPABILITY_REG (PXCR)*/
550
551#define PXCR_CAP_ID_OFFS 0 /* Capability ID*/
552#define PXCR_CAP_ID_MASK (0xff << PXCR_CAP_ID_OFFS)
553
554#define PXCR_NEXT_PTR_OFFS 8 /* Next Item Pointer*/
555#define PXCR_NEXT_PTR_MASK (0xff << PXCR_NEXT_PTR_OFFS)
556
557#define PXCR_CAP_VER_OFFS 16 /* Capability Version*/
558#define PXCR_CAP_VER_MASK (0xf << PXCR_CAP_VER_OFFS)
559
560#define PXCR_DEV_TYPE_OFFS 20 /* Device/Port Type*/
561#define PXCR_DEV_TYPE_MASK (0xf << PXCR_DEV_TYPE_OFFS)
562
563#define PXCR_SLOT_IMP BIT24 /* Slot Implemented*/
564
565#define PXCR_INT_MSG_NUM_OFFS 25 /* Interrupt Message Number*/
566#define PXCR_INT_MSG_NUM_MASK (0x1f << PXCR_INT_MSG_NUM_OFFS)
567
568
569/* PCI Express Device Capabilities Register */
570/*PEX_DEV_CAPABILITY_REG (PXDCR)*/
571
572#define PXDCR_MAX_PLD_SIZE_SUP_OFFS 0 /* Maximum Payload Size Supported*/
573#define PXDCR_MAX_PLD_SIZE_SUP_MASK (0x7 << PXDCR_MAX_PLD_SIZE_SUP_OFFS)
574
575#define PXDCR_EP_L0S_ACC_LAT_OFFS 6/* Endpoint L0s Acceptable Latency*/
576#define PXDCR_EP_L0S_ACC_LAT_MASK (0x7 << PXDCR_EP_L0S_ACC_LAT_OFFS)
577#define PXDCR_EP_L0S_ACC_LAT_64NS_LESS (0x0 << PXDCR_EP_L0S_ACC_LAT_OFFS)
578#define PXDCR_EP_L0S_ACC_LAT_64NS_128NS (0x1 << PXDCR_EP_L0S_ACC_LAT_OFFS)
579#define PXDCR_EP_L0S_ACC_LAT_128NS_256NS (0x2 << PXDCR_EP_L0S_ACC_LAT_OFFS)
580#define PXDCR_EP_L0S_ACC_LAT_256NS_512NS (0x3 << PXDCR_EP_L0S_ACC_LAT_OFFS)
581#define PXDCR_EP_L0S_ACC_LAT_512NS_1US (0x4 << PXDCR_EP_L0S_ACC_LAT_OFFS)
582#define PXDCR_EP_L0S_ACC_LAT_1US_2US (0x5 << PXDCR_EP_L0S_ACC_LAT_OFFS)
583#define PXDCR_EP_L0S_ACC_LAT_2US_4US (0x6 << PXDCR_EP_L0S_ACC_LAT_OFFS)
584#define PXDCR_EP_L0S_ACC_LAT_4US_MORE (0x7 << PXDCR_EP_L0S_ACC_LAT_OFFS)
585
586#define PXDCR_EP_L1_ACC_LAT_OFFS 9 /* Endpoint L1 Acceptable Latency*/
587#define PXDCR_EP_L1_ACC_LAT_MASK (0x7 << PXDCR_EP_L1_ACC_LAT_OFFS)
588#define PXDCR_EP_L1_ACC_LAT_64NS_LESS (0x0 << PXDCR_EP_L1_ACC_LAT_OFFS)
589#define PXDCR_EP_L1_ACC_LAT_64NS_128NS (0x1 << PXDCR_EP_L1_ACC_LAT_OFFS)
590#define PXDCR_EP_L1_ACC_LAT_128NS_256NS (0x2 << PXDCR_EP_L1_ACC_LAT_OFFS)
591#define PXDCR_EP_L1_ACC_LAT_256NS_512NS (0x3 << PXDCR_EP_L1_ACC_LAT_OFFS)
592#define PXDCR_EP_L1_ACC_LAT_512NS_1US (0x4 << PXDCR_EP_L1_ACC_LAT_OFFS)
593#define PXDCR_EP_L1_ACC_LAT_1US_2US (0x5 << PXDCR_EP_L1_ACC_LAT_OFFS)
594#define PXDCR_EP_L1_ACC_LAT_2US_4US (0x6 << PXDCR_EP_L1_ACC_LAT_OFFS)
595#define PXDCR_EP_L1_ACC_LAT_4US_MORE (0x7 << PXDCR_EP_L1_ACC_LAT_OFFS)
596
597
598#define PXDCR_ATT_BUT_PRS_OFFS 12 /* Attention Button Present*/
599#define PXDCR_ATT_BUT_PRS_MASK BIT12
600#define PXDCR_ATT_BUT_PRS_IMPLEMENTED BIT12
601
602#define PXDCR_ATT_IND_PRS_OFFS 13 /* Attention Indicator Present*/
603#define PXDCR_ATT_IND_PRS_MASK BIT13
604#define PXDCR_ATT_IND_PRS_IMPLEMENTED BIT13
605
606#define PXDCR_PWR_IND_PRS_OFFS 14/* Power Indicator Present*/
607#define PXDCR_PWR_IND_PRS_MASK BIT14
608#define PXDCR_PWR_IND_PRS_IMPLEMENTED BIT14
609
610#define PXDCR_CAP_SPL_VAL_OFFS 18 /*Captured Slot Power Limit
611                                                 Value*/
612#define PXDCR_CAP_SPL_VAL_MASK (0xff << PXDCR_CAP_SPL_VAL_OFFS)
613
614#define PXDCR_CAP_SP_LSCL_OFFS 26 /* Captured Slot Power Limit
615                                                  Scale */
616#define PXDCR_CAP_SP_LSCL_MASK (0x3 << PXDCR_CAP_SP_LSCL_OFFS)
617
618/* PCI Express Device Control Status Register */
619/*PEX_DEV_CTRL_STAT_REG (PXDCSR)*/
620
621#define PXDCSR_COR_ERR_REP_EN BIT0 /* Correctable Error Reporting Enable*/
622#define PXDCSR_NF_ERR_REP_EN BIT1 /* Non-Fatal Error Reporting Enable*/
623#define PXDCSR_F_ERR_REP_EN BIT2 /* Fatal Error Reporting Enable*/
624#define PXDCSR_UR_REP_EN BIT3 /* Unsupported Request (UR)
625                                                    Reporting Enable*/
626#define PXDCSR_EN_RO BIT4 /* Enable Relaxed Ordering*/
627
628#define PXDCSR_MAX_PLD_SZ_OFFS 5 /* Maximum Payload Size*/
629#define PXDCSR_MAX_PLD_SZ_MASK (0x7 << PXDCSR_MAX_PLD_SZ_OFFS)
630#define PXDCSR_MAX_PLD_SZ_128B (0x0 << PXDCSR_MAX_PLD_SZ_OFFS)
631#define PXDCSR_EN_NS BIT11 /* Enable No Snoop*/
632
633#define PXDCSR_MAX_RD_RQ_SZ_OFFS 12 /* Maximum Read Request Size*/
634#define PXDCSR_MAX_RD_RQ_SZ_MASK (0x7 << PXDCSR_MAX_RD_RQ_SZ_OFFS)
635#define PXDCSR_MAX_RD_RQ_SZ_128B (0x0 << PXDCSR_MAX_RD_RQ_SZ_OFFS)
636#define PXDCSR_MAX_RD_RQ_SZ_256B (0x1 << PXDCSR_MAX_RD_RQ_SZ_OFFS)
637#define PXDCSR_MAX_RD_RQ_SZ_512B (0x2 << PXDCSR_MAX_RD_RQ_SZ_OFFS)
638#define PXDCSR_MAX_RD_RQ_SZ_1KB (0x3 << PXDCSR_MAX_RD_RQ_SZ_OFFS)
639#define PXDCSR_MAX_RD_RQ_SZ_2KB (0x4 << PXDCSR_MAX_RD_RQ_SZ_OFFS)
640#define PXDCSR_MAX_RD_RQ_SZ_4KB (0x5 << PXDCSR_MAX_RD_RQ_SZ_OFFS)
641
642#define PXDCSR_COR_ERR_DET BIT16 /* Correctable Error Detected*/
643#define PXDCSR_NF_ERR_DET BIT17 /* Non-Fatal Error Detected.*/
644#define PXDCSR_F_ERR_DET BIT18 /* Fatal Error Detected.*/
645#define PXDCSR_UR_DET BIT19 /* Unsupported Request Detected */
646#define PXDCSR_AUX_PWR_DET BIT20 /* Reserved*/
647
648#define PXDCSR_TRANS_PEND_OFFS 21 /* Transactions Pending*/
649#define PXDCSR_TRANS_PEND_MASK BIT21
650#define PXDCSR_TRANS_PEND_NOT_COMPLETED (0x1 << PXDCSR_TRANS_PEND_OFFS)
651
652
653/* PCI Express Link Capabilities Register*/
654/*PEX_LINK_CAPABILITY_REG (PXLCR)*/
655
656#define PXLCR_MAX_LINK_SPD_OFFS 0 /* Maximum Link Speed*/
657#define PXLCR_MAX_LINK_SPD_MASK (0xf << PXLCR_MAX_LINK_SPD_OFFS)
658
659#define PXLCR_MAX_LNK_WDTH_OFFS 3 /* Maximum Link Width*/
660#define PXLCR_MAX_LNK_WDTH_MASK (0x3f << PXLCR_MAX_LNK_WDTH_OFFS)
661
662#define PXLCR_ASPM_SUP_OFFS 10 /* Active State Link PM Support*/
663#define PXLCR_ASPM_SUP_MASK (0x3 << PXLCR_ASPM_SUP_OFFS)
664
665#define PXLCR_L0S_EXT_LAT_OFFS 12 /* L0s Exit Latency*/
666#define PXLCR_L0S_EXT_LAT_MASK (0x7 << PXLCR_L0S_EXT_LAT_OFFS)
667#define PXLCR_L0S_EXT_LAT_64NS_LESS (0x0 << PXDCR_EP_L1_ACC_LAT_OFFS)
668#define PXLCR_L0S_EXT_LAT_64NS_128NS (0x1 << PXDCR_EP_L1_ACC_LAT_OFFS)
669#define PXLCR_L0S_EXT_LAT_128NS_256NS (0x2 << PXDCR_EP_L1_ACC_LAT_OFFS)
670#define PXLCR_L0S_EXT_LAT_256NS_512NS (0x3 << PXDCR_EP_L1_ACC_LAT_OFFS)
671#define PXLCR_L0S_EXT_LAT_512NS_1US (0x4 << PXDCR_EP_L1_ACC_LAT_OFFS)
672#define PXLCR_L0S_EXT_LAT_1US_2US (0x5 << PXDCR_EP_L1_ACC_LAT_OFFS)
673#define PXLCR_L0S_EXT_LAT_2US_4US (0x6 << PXDCR_EP_L1_ACC_LAT_OFFS)
674
675#define PXLCR_POR_TNUM_OFFS 24 /* Port Number */
676#define PXLCR_POR_TNUM_MASK (0xff << PXLCR_POR_TNUM_OFFS)
677
678/* PCI Express Link Control Status Register */
679/*PEX_LINK_CTRL_STAT_REG (PXLCSR)*/
680
681#define PXLCSR_ASPM_CNT_OFFS 0 /* Active State Link PM Control */
682#define PXLCSR_ASPM_CNT_MASK (0x3 << PXLCSR_ASPM_CNT_OFFS)
683#define PXLCSR_ASPM_CNT_DISABLED (0x0 << PXLCSR_ASPM_CNT_OFFS)
684#define PXLCSR_ASPM_CNT_L0S_ENT_SUPP (0x1 << PXLCSR_ASPM_CNT_OFFS)
685#define PXLCSR_ASPM_CNT_L1S_ENT_SUPP (0x2 << PXLCSR_ASPM_CNT_OFFS)
686#define PXLCSR_ASPM_CNT_L0S_L1S_ENT_SUPP (0x3 << PXLCSR_ASPM_CNT_OFFS)
687
688#define PXLCSR_RCB_OFFS 3 /* Read Completion Boundary */
689#define PXLCSR_RCB_MASK BIT3
690#define PXLCSR_RCB_64B (0 << PXLCSR_RCB_OFFS)
691#define PXLCSR_RCB_128B (1 << PXLCSR_RCB_OFFS)
692
693#define PXLCSR_LNK_DIS BIT4 /* Link Disable */
694#define PXLCSR_RETRN_LNK BIT5 /* Retrain Link */
695#define PXLCSR_CMN_CLK_CFG BIT6 /* Common Clock Configuration */
696#define PXLCSR_EXTD_SNC BIT7 /* Extended Sync */
697
698#define PXLCSR_LNK_SPD_OFFS 16 /* Link Speed */
699#define PXLCSR_LNK_SPD_MASK (0xf << PXLCSR_LNK_SPD_OFFS)
700
701#define PXLCSR_NEG_LNK_WDTH_OFFS 20 /* Negotiated Link Width */
702#define PXLCSR_NEG_LNK_WDTH_MASK (0x3f << PXLCSR_NEG_LNK_WDTH_OFFS)
703#define PXLCSR_NEG_LNK_WDTH_X1 (0x1 << PXLCSR_NEG_LNK_WDTH_OFFS)
704
705#define PXLCSR_LNK_TRN BIT27 /* Link Training */
706
707#define PXLCSR_SLT_CLK_CFG_OFFS 28 /* Slot Clock Configuration */
708#define PXLCSR_SLT_CLK_CFG_MASK BIT28
709#define PXLCSR_SLT_CLK_CFG_INDPNT (0x0 << PXLCSR_SLT_CLK_CFG_OFFS)
710#define PXLCSR_SLT_CLK_CFG_REF (0x1 << PXLCSR_SLT_CLK_CFG_OFFS)
711                                
712/* PCI Express Advanced Error Report Header Register */
713/*PEX_ADV_ERR_RPRT_HDR_TRGT_REG (PXAERHTR)*/
714
715/* PCI Express Uncorrectable Error Status Register*/
716/*PEX_UNCORRECT_ERR_STAT_REG (PXUESR)*/
717
718/* PCI Express Uncorrectable Error Mask Register */
719/*PEX_UNCORRECT_ERR_MASK_REG (PXUEMR)*/
720
721/* PCI Express Uncorrectable Error Severity Register */
722/*PEX_UNCORRECT_ERR_SERVITY_REG (PXUESR)*/
723
724/* PCI Express Correctable Error Status Register */
725/*PEX_CORRECT_ERR_STAT_REG (PXCESR)*/
726
727/* PCI Express Correctable Error Mask Register */
728/*PEX_CORRECT_ERR_MASK_REG (PXCEMR)*/
729
730/* PCI Express Advanced Error Capability and Control Register*/
731/*PEX_ADV_ERR_CAPABILITY_CTRL_REG (PXAECCR)*/
732
733/* PCI Express Header Log First DWORD Register*/
734/*PEX_HDR_LOG_FIRST_DWORD_REG (PXHLFDR)*/
735
736/* PCI Express Header Log Second DWORD Register*/
737/*PEX_HDR_LOG_SECOND_DWORD_REG (PXHLSDR)*/
738
739/* PCI Express Header Log Third DWORD Register*/
740/*PEX_HDR_LOG_THIRD_DWORD_REG (PXHLTDR)*/
741
742/* PCI Express Header Log Fourth DWORD Register*/
743/*PEX_HDR_LOG_FOURTH_DWORD_REG (PXHLFDR)*/
744
745#ifdef __cplusplus
746}
747#endif /* __cplusplus */
748
749#endif /* #ifndef __INCPEXREGSH */
750
751
752

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