Root/target/linux/generic/files/crypto/ocf/safe/safereg.h

1/*-
2 * Copyright (c) 2003 Sam Leffler, Errno Consulting
3 * Copyright (c) 2003 Global Technology Associates, Inc.
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 *
27 * $FreeBSD: src/sys/dev/safe/safereg.h,v 1.1 2003/07/21 21:46:07 sam Exp $
28 */
29#ifndef _SAFE_SAFEREG_H_
30#define _SAFE_SAFEREG_H_
31
32/*
33 * Register definitions for SafeNet SafeXcel-1141 crypto device.
34 * Definitions from revision 1.3 (Nov 6 2002) of the User's Manual.
35 */
36
37#define BS_BAR 0x10 /* DMA base address register */
38#define BS_TRDY_TIMEOUT 0x40 /* TRDY timeout */
39#define BS_RETRY_TIMEOUT 0x41 /* DMA retry timeout */
40
41#define PCI_VENDOR_SAFENET 0x16ae /* SafeNet, Inc. */
42
43/* SafeNet */
44#define PCI_PRODUCT_SAFEXCEL 0x1141 /* 1141 */
45
46#define SAFE_PE_CSR 0x0000 /* Packet Enginge Ctrl/Status */
47#define SAFE_PE_SRC 0x0004 /* Packet Engine Source */
48#define SAFE_PE_DST 0x0008 /* Packet Engine Destination */
49#define SAFE_PE_SA 0x000c /* Packet Engine SA */
50#define SAFE_PE_LEN 0x0010 /* Packet Engine Length */
51#define SAFE_PE_DMACFG 0x0040 /* Packet Engine DMA Configuration */
52#define SAFE_PE_DMASTAT 0x0044 /* Packet Engine DMA Status */
53#define SAFE_PE_PDRBASE 0x0048 /* Packet Engine Descriptor Ring Base */
54#define SAFE_PE_RDRBASE 0x004c /* Packet Engine Result Ring Base */
55#define SAFE_PE_RINGCFG 0x0050 /* Packet Engine Ring Configuration */
56#define SAFE_PE_RINGPOLL 0x0054 /* Packet Engine Ring Poll */
57#define SAFE_PE_IRNGSTAT 0x0058 /* Packet Engine Internal Ring Status */
58#define SAFE_PE_ERNGSTAT 0x005c /* Packet Engine External Ring Status */
59#define SAFE_PE_IOTHRESH 0x0060 /* Packet Engine I/O Threshold */
60#define SAFE_PE_GRNGBASE 0x0064 /* Packet Engine Gather Ring Base */
61#define SAFE_PE_SRNGBASE 0x0068 /* Packet Engine Scatter Ring Base */
62#define SAFE_PE_PARTSIZE 0x006c /* Packet Engine Particlar Ring Size */
63#define SAFE_PE_PARTCFG 0x0070 /* Packet Engine Particle Ring Config */
64#define SAFE_CRYPTO_CTRL 0x0080 /* Crypto Control */
65#define SAFE_DEVID 0x0084 /* Device ID */
66#define SAFE_DEVINFO 0x0088 /* Device Info */
67#define SAFE_HU_STAT 0x00a0 /* Host Unmasked Status */
68#define SAFE_HM_STAT 0x00a4 /* Host Masked Status (read-only) */
69#define SAFE_HI_CLR 0x00a4 /* Host Clear Interrupt (write-only) */
70#define SAFE_HI_MASK 0x00a8 /* Host Mask Control */
71#define SAFE_HI_CFG 0x00ac /* Interrupt Configuration */
72#define SAFE_HI_RD_DESCR 0x00b4 /* Force Descriptor Read */
73#define SAFE_HI_DESC_CNT 0x00b8 /* Host Descriptor Done Count */
74#define SAFE_DMA_ENDIAN 0x00c0 /* Master Endian Status */
75#define SAFE_DMA_SRCADDR 0x00c4 /* DMA Source Address Status */
76#define SAFE_DMA_DSTADDR 0x00c8 /* DMA Destination Address Status */
77#define SAFE_DMA_STAT 0x00cc /* DMA Current Status */
78#define SAFE_DMA_CFG 0x00d4 /* DMA Configuration/Status */
79#define SAFE_ENDIAN 0x00e0 /* Endian Configuration */
80#define SAFE_PK_A_ADDR 0x0800 /* Public Key A Address */
81#define SAFE_PK_B_ADDR 0x0804 /* Public Key B Address */
82#define SAFE_PK_C_ADDR 0x0808 /* Public Key C Address */
83#define SAFE_PK_D_ADDR 0x080c /* Public Key D Address */
84#define SAFE_PK_A_LEN 0x0810 /* Public Key A Length */
85#define SAFE_PK_B_LEN 0x0814 /* Public Key B Length */
86#define SAFE_PK_SHIFT 0x0818 /* Public Key Shift */
87#define SAFE_PK_FUNC 0x081c /* Public Key Function */
88#define SAFE_PK_RAM_START 0x1000 /* Public Key RAM start address */
89#define SAFE_PK_RAM_END 0x1fff /* Public Key RAM end address */
90
91#define SAFE_RNG_OUT 0x0100 /* RNG Output */
92#define SAFE_RNG_STAT 0x0104 /* RNG Status */
93#define SAFE_RNG_CTRL 0x0108 /* RNG Control */
94#define SAFE_RNG_A 0x010c /* RNG A */
95#define SAFE_RNG_B 0x0110 /* RNG B */
96#define SAFE_RNG_X_LO 0x0114 /* RNG X [31:0] */
97#define SAFE_RNG_X_MID 0x0118 /* RNG X [63:32] */
98#define SAFE_RNG_X_HI 0x011c /* RNG X [80:64] */
99#define SAFE_RNG_X_CNTR 0x0120 /* RNG Counter */
100#define SAFE_RNG_ALM_CNT 0x0124 /* RNG Alarm Count */
101#define SAFE_RNG_CNFG 0x0128 /* RNG Configuration */
102#define SAFE_RNG_LFSR1_LO 0x012c /* RNG LFSR1 [31:0] */
103#define SAFE_RNG_LFSR1_HI 0x0130 /* RNG LFSR1 [47:32] */
104#define SAFE_RNG_LFSR2_LO 0x0134 /* RNG LFSR1 [31:0] */
105#define SAFE_RNG_LFSR2_HI 0x0138 /* RNG LFSR1 [47:32] */
106
107#define SAFE_PE_CSR_READY 0x00000001 /* ready for processing */
108#define SAFE_PE_CSR_DONE 0x00000002 /* h/w completed processing */
109#define SAFE_PE_CSR_LOADSA 0x00000004 /* load SA digests */
110#define SAFE_PE_CSR_HASHFINAL 0x00000010 /* do hash pad & write result */
111#define SAFE_PE_CSR_SABUSID 0x000000c0 /* bus id for SA */
112#define SAFE_PE_CSR_SAPCI 0x00000040 /* PCI bus id for SA */
113#define SAFE_PE_CSR_NXTHDR 0x0000ff00 /* next hdr value for IPsec */
114#define SAFE_PE_CSR_FPAD 0x0000ff00 /* fixed pad for basic ops */
115#define SAFE_PE_CSR_STATUS 0x00ff0000 /* operation result status */
116#define SAFE_PE_CSR_AUTH_FAIL 0x00010000 /* ICV mismatch (inbound) */
117#define SAFE_PE_CSR_PAD_FAIL 0x00020000 /* pad verify fail (inbound) */
118#define SAFE_PE_CSR_SEQ_FAIL 0x00040000 /* sequence number (inbound) */
119#define SAFE_PE_CSR_XERROR 0x00080000 /* extended error follows */
120#define SAFE_PE_CSR_XECODE 0x00f00000 /* extended error code */
121#define SAFE_PE_CSR_XECODE_S 20
122#define SAFE_PE_CSR_XECODE_BADCMD 0 /* invalid command */
123#define SAFE_PE_CSR_XECODE_BADALG 1 /* invalid algorithm */
124#define SAFE_PE_CSR_XECODE_ALGDIS 2 /* algorithm disabled */
125#define SAFE_PE_CSR_XECODE_ZEROLEN 3 /* zero packet length */
126#define SAFE_PE_CSR_XECODE_DMAERR 4 /* bus DMA error */
127#define SAFE_PE_CSR_XECODE_PIPEABORT 5 /* secondary bus DMA error */
128#define SAFE_PE_CSR_XECODE_BADSPI 6 /* IPsec SPI mismatch */
129#define SAFE_PE_CSR_XECODE_TIMEOUT 10 /* failsafe timeout */
130#define SAFE_PE_CSR_PAD 0xff000000 /* ESP padding control/status */
131#define SAFE_PE_CSR_PAD_MIN 0x00000000 /* minimum IPsec padding */
132#define SAFE_PE_CSR_PAD_16 0x08000000 /* pad to 16-byte boundary */
133#define SAFE_PE_CSR_PAD_32 0x10000000 /* pad to 32-byte boundary */
134#define SAFE_PE_CSR_PAD_64 0x20000000 /* pad to 64-byte boundary */
135#define SAFE_PE_CSR_PAD_128 0x40000000 /* pad to 128-byte boundary */
136#define SAFE_PE_CSR_PAD_256 0x80000000 /* pad to 256-byte boundary */
137
138/*
139 * Check the CSR to see if the PE has returned ownership to
140 * the host. Note that before processing a descriptor this
141 * must be done followed by a check of the SAFE_PE_LEN register
142 * status bits to avoid premature processing of a descriptor
143 * on its way back to the host.
144 */
145#define SAFE_PE_CSR_IS_DONE(_csr) \
146    (((_csr) & (SAFE_PE_CSR_READY | SAFE_PE_CSR_DONE)) == SAFE_PE_CSR_DONE)
147
148#define SAFE_PE_LEN_LENGTH 0x000fffff /* total length (bytes) */
149#define SAFE_PE_LEN_READY 0x00400000 /* ready for processing */
150#define SAFE_PE_LEN_DONE 0x00800000 /* h/w completed processing */
151#define SAFE_PE_LEN_BYPASS 0xff000000 /* bypass offset (bytes) */
152#define SAFE_PE_LEN_BYPASS_S 24
153
154#define SAFE_PE_LEN_IS_DONE(_len) \
155    (((_len) & (SAFE_PE_LEN_READY | SAFE_PE_LEN_DONE)) == SAFE_PE_LEN_DONE)
156
157/* NB: these apply to HU_STAT, HM_STAT, HI_CLR, and HI_MASK */
158#define SAFE_INT_PE_CDONE 0x00000002 /* PE context done */
159#define SAFE_INT_PE_DDONE 0x00000008 /* PE descriptor done */
160#define SAFE_INT_PE_ERROR 0x00000010 /* PE error */
161#define SAFE_INT_PE_ODONE 0x00000020 /* PE operation done */
162
163#define SAFE_HI_CFG_PULSE 0x00000001 /* use pulse interrupt */
164#define SAFE_HI_CFG_LEVEL 0x00000000 /* use level interrupt */
165#define SAFE_HI_CFG_AUTOCLR 0x00000002 /* auto-clear pulse interrupt */
166
167#define SAFE_ENDIAN_PASS 0x000000e4 /* straight pass-thru */
168#define SAFE_ENDIAN_SWAB 0x0000001b /* swap bytes in 32-bit word */
169
170#define SAFE_PE_DMACFG_PERESET 0x00000001 /* reset packet engine */
171#define SAFE_PE_DMACFG_PDRRESET 0x00000002 /* reset PDR counters/ptrs */
172#define SAFE_PE_DMACFG_SGRESET 0x00000004 /* reset scatter/gather cache */
173#define SAFE_PE_DMACFG_FSENA 0x00000008 /* enable failsafe reset */
174#define SAFE_PE_DMACFG_PEMODE 0x00000100 /* packet engine mode */
175#define SAFE_PE_DMACFG_SAPREC 0x00000200 /* SA precedes packet */
176#define SAFE_PE_DMACFG_PKFOLL 0x00000400 /* packet follows descriptor */
177#define SAFE_PE_DMACFG_GPRBID 0x00003000 /* gather particle ring busid */
178#define SAFE_PE_DMACFG_GPRPCI 0x00001000 /* PCI gather particle ring */
179#define SAFE_PE_DMACFG_SPRBID 0x0000c000 /* scatter part. ring busid */
180#define SAFE_PE_DMACFG_SPRPCI 0x00004000 /* PCI scatter part. ring */
181#define SAFE_PE_DMACFG_ESDESC 0x00010000 /* endian swap descriptors */
182#define SAFE_PE_DMACFG_ESSA 0x00020000 /* endian swap SA data */
183#define SAFE_PE_DMACFG_ESPACKET 0x00040000 /* endian swap packet data */
184#define SAFE_PE_DMACFG_ESPDESC 0x00080000 /* endian swap particle desc. */
185#define SAFE_PE_DMACFG_NOPDRUP 0x00100000 /* supp. PDR ownership update */
186#define SAFE_PD_EDMACFG_PCIMODE 0x01000000 /* PCI target mode */
187
188#define SAFE_PE_DMASTAT_PEIDONE 0x00000001 /* PE core input done */
189#define SAFE_PE_DMASTAT_PEODONE 0x00000002 /* PE core output done */
190#define SAFE_PE_DMASTAT_ENCDONE 0x00000004 /* encryption done */
191#define SAFE_PE_DMASTAT_IHDONE 0x00000008 /* inner hash done */
192#define SAFE_PE_DMASTAT_OHDONE 0x00000010 /* outer hash (HMAC) done */
193#define SAFE_PE_DMASTAT_PADFLT 0x00000020 /* crypto pad fault */
194#define SAFE_PE_DMASTAT_ICVFLT 0x00000040 /* ICV fault */
195#define SAFE_PE_DMASTAT_SPIMIS 0x00000080 /* SPI mismatch */
196#define SAFE_PE_DMASTAT_CRYPTO 0x00000100 /* crypto engine timeout */
197#define SAFE_PE_DMASTAT_CQACT 0x00000200 /* command queue active */
198#define SAFE_PE_DMASTAT_IRACT 0x00000400 /* input request active */
199#define SAFE_PE_DMASTAT_ORACT 0x00000800 /* output request active */
200#define SAFE_PE_DMASTAT_PEISIZE 0x003ff000 /* PE input size:32-bit words */
201#define SAFE_PE_DMASTAT_PEOSIZE 0xffc00000 /* PE out. size:32-bit words */
202
203#define SAFE_PE_RINGCFG_SIZE 0x000003ff /* ring size (descriptors) */
204#define SAFE_PE_RINGCFG_OFFSET 0xffff0000 /* offset btw desc's (dwords) */
205#define SAFE_PE_RINGCFG_OFFSET_S 16
206
207#define SAFE_PE_RINGPOLL_POLL 0x00000fff /* polling frequency/divisor */
208#define SAFE_PE_RINGPOLL_RETRY 0x03ff0000 /* polling frequency/divisor */
209#define SAFE_PE_RINGPOLL_CONT 0x80000000 /* continuously poll */
210
211#define SAFE_PE_IRNGSTAT_CQAVAIL 0x00000001 /* command queue available */
212
213#define SAFE_PE_ERNGSTAT_NEXT 0x03ff0000 /* index of next packet desc. */
214#define SAFE_PE_ERNGSTAT_NEXT_S 16
215
216#define SAFE_PE_IOTHRESH_INPUT 0x000003ff /* input threshold (dwords) */
217#define SAFE_PE_IOTHRESH_OUTPUT 0x03ff0000 /* output threshold (dwords) */
218
219#define SAFE_PE_PARTCFG_SIZE 0x0000ffff /* scatter particle size */
220#define SAFE_PE_PARTCFG_GBURST 0x00030000 /* gather particle burst */
221#define SAFE_PE_PARTCFG_GBURST_2 0x00000000
222#define SAFE_PE_PARTCFG_GBURST_4 0x00010000
223#define SAFE_PE_PARTCFG_GBURST_8 0x00020000
224#define SAFE_PE_PARTCFG_GBURST_16 0x00030000
225#define SAFE_PE_PARTCFG_SBURST 0x000c0000 /* scatter particle burst */
226#define SAFE_PE_PARTCFG_SBURST_2 0x00000000
227#define SAFE_PE_PARTCFG_SBURST_4 0x00040000
228#define SAFE_PE_PARTCFG_SBURST_8 0x00080000
229#define SAFE_PE_PARTCFG_SBURST_16 0x000c0000
230
231#define SAFE_PE_PARTSIZE_SCAT 0xffff0000 /* scatter particle ring size */
232#define SAFE_PE_PARTSIZE_GATH 0x0000ffff /* gather particle ring size */
233
234#define SAFE_CRYPTO_CTRL_3DES 0x00000001 /* enable 3DES support */
235#define SAFE_CRYPTO_CTRL_PKEY 0x00010000 /* enable public key support */
236#define SAFE_CRYPTO_CTRL_RNG 0x00020000 /* enable RNG support */
237
238#define SAFE_DEVINFO_REV_MIN 0x0000000f /* minor rev for chip */
239#define SAFE_DEVINFO_REV_MAJ 0x000000f0 /* major rev for chip */
240#define SAFE_DEVINFO_REV_MAJ_S 4
241#define SAFE_DEVINFO_DES 0x00000100 /* DES/3DES support present */
242#define SAFE_DEVINFO_ARC4 0x00000200 /* ARC4 support present */
243#define SAFE_DEVINFO_AES 0x00000400 /* AES support present */
244#define SAFE_DEVINFO_MD5 0x00001000 /* MD5 support present */
245#define SAFE_DEVINFO_SHA1 0x00002000 /* SHA-1 support present */
246#define SAFE_DEVINFO_RIPEMD 0x00004000 /* RIPEMD support present */
247#define SAFE_DEVINFO_DEFLATE 0x00010000 /* Deflate support present */
248#define SAFE_DEVINFO_SARAM 0x00100000 /* on-chip SA RAM present */
249#define SAFE_DEVINFO_EMIBUS 0x00200000 /* EMI bus present */
250#define SAFE_DEVINFO_PKEY 0x00400000 /* public key support present */
251#define SAFE_DEVINFO_RNG 0x00800000 /* RNG present */
252
253#define SAFE_REV(_maj, _min) (((_maj) << SAFE_DEVINFO_REV_MAJ_S) | (_min))
254#define SAFE_REV_MAJ(_chiprev) \
255    (((_chiprev) & SAFE_DEVINFO_REV_MAJ) >> SAFE_DEVINFO_REV_MAJ_S)
256#define SAFE_REV_MIN(_chiprev) ((_chiprev) & SAFE_DEVINFO_REV_MIN)
257
258#define SAFE_PK_FUNC_MULT 0x00000001 /* Multiply function */
259#define SAFE_PK_FUNC_SQUARE 0x00000004 /* Square function */
260#define SAFE_PK_FUNC_ADD 0x00000010 /* Add function */
261#define SAFE_PK_FUNC_SUB 0x00000020 /* Subtract function */
262#define SAFE_PK_FUNC_LSHIFT 0x00000040 /* Left-shift function */
263#define SAFE_PK_FUNC_RSHIFT 0x00000080 /* Right-shift function */
264#define SAFE_PK_FUNC_DIV 0x00000100 /* Divide function */
265#define SAFE_PK_FUNC_CMP 0x00000400 /* Compare function */
266#define SAFE_PK_FUNC_COPY 0x00000800 /* Copy function */
267#define SAFE_PK_FUNC_EXP16 0x00002000 /* Exponentiate (4-bit ACT) */
268#define SAFE_PK_FUNC_EXP4 0x00004000 /* Exponentiate (2-bit ACT) */
269#define SAFE_PK_FUNC_RUN 0x00008000 /* start/status */
270
271#define SAFE_RNG_STAT_BUSY 0x00000001 /* busy, data not valid */
272
273#define SAFE_RNG_CTRL_PRE_LFSR 0x00000001 /* enable output pre-LFSR */
274#define SAFE_RNG_CTRL_TST_MODE 0x00000002 /* enable test mode */
275#define SAFE_RNG_CTRL_TST_RUN 0x00000004 /* start test state machine */
276#define SAFE_RNG_CTRL_ENA_RING1 0x00000008 /* test entropy oscillator #1 */
277#define SAFE_RNG_CTRL_ENA_RING2 0x00000010 /* test entropy oscillator #2 */
278#define SAFE_RNG_CTRL_DIS_ALARM 0x00000020 /* disable RNG alarm reports */
279#define SAFE_RNG_CTRL_TST_CLOCK 0x00000040 /* enable test clock */
280#define SAFE_RNG_CTRL_SHORTEN 0x00000080 /* shorten state timers */
281#define SAFE_RNG_CTRL_TST_ALARM 0x00000100 /* simulate alarm state */
282#define SAFE_RNG_CTRL_RST_LFSR 0x00000200 /* reset LFSR */
283
284/*
285 * Packet engine descriptor. Note that d_csr is a copy of the
286 * SAFE_PE_CSR register and all definitions apply, and d_len
287 * is a copy of the SAFE_PE_LEN register and all definitions apply.
288 * d_src and d_len may point directly to contiguous data or to a
289 * list of ``particle descriptors'' when using scatter/gather i/o.
290 */
291struct safe_desc {
292    u_int32_t d_csr; /* per-packet control/status */
293    u_int32_t d_src; /* source address */
294    u_int32_t d_dst; /* destination address */
295    u_int32_t d_sa; /* SA address */
296    u_int32_t d_len; /* length, bypass, status */
297};
298
299/*
300 * Scatter/Gather particle descriptor.
301 *
302 * NB: scatter descriptors do not specify a size; this is fixed
303 * by the setting of the SAFE_PE_PARTCFG register.
304 */
305struct safe_pdesc {
306    u_int32_t pd_addr; /* particle address */
307#ifdef __BIG_ENDIAN
308    u_int16_t pd_flags; /* control word */
309    u_int16_t pd_size; /* particle size (bytes) */
310#else
311    u_int16_t pd_flags; /* control word */
312    u_int16_t pd_size; /* particle size (bytes) */
313#endif
314};
315
316#define SAFE_PD_READY 0x0001 /* ready for processing */
317#define SAFE_PD_DONE 0x0002 /* h/w completed processing */
318
319/*
320 * Security Association (SA) Record (Rev 1). One of these is
321 * required for each operation processed by the packet engine.
322 */
323struct safe_sarec {
324    u_int32_t sa_cmd0;
325    u_int32_t sa_cmd1;
326    u_int32_t sa_resv0;
327    u_int32_t sa_resv1;
328    u_int32_t sa_key[8]; /* DES/3DES/AES key */
329    u_int32_t sa_indigest[5]; /* inner digest */
330    u_int32_t sa_outdigest[5]; /* outer digest */
331    u_int32_t sa_spi; /* SPI */
332    u_int32_t sa_seqnum; /* sequence number */
333    u_int32_t sa_seqmask[2]; /* sequence number mask */
334    u_int32_t sa_resv2;
335    u_int32_t sa_staterec; /* address of state record */
336    u_int32_t sa_resv3[2];
337    u_int32_t sa_samgmt0; /* SA management field 0 */
338    u_int32_t sa_samgmt1; /* SA management field 0 */
339};
340
341#define SAFE_SA_CMD0_OP 0x00000007 /* operation code */
342#define SAFE_SA_CMD0_OP_CRYPT 0x00000000 /* encrypt/decrypt (basic) */
343#define SAFE_SA_CMD0_OP_BOTH 0x00000001 /* encrypt-hash/hash-decrypto */
344#define SAFE_SA_CMD0_OP_HASH 0x00000003 /* hash (outbound-only) */
345#define SAFE_SA_CMD0_OP_ESP 0x00000000 /* ESP in/out (proto) */
346#define SAFE_SA_CMD0_OP_AH 0x00000001 /* AH in/out (proto) */
347#define SAFE_SA_CMD0_INBOUND 0x00000008 /* inbound operation */
348#define SAFE_SA_CMD0_OUTBOUND 0x00000000 /* outbound operation */
349#define SAFE_SA_CMD0_GROUP 0x00000030 /* operation group */
350#define SAFE_SA_CMD0_BASIC 0x00000000 /* basic operation */
351#define SAFE_SA_CMD0_PROTO 0x00000010 /* protocol/packet operation */
352#define SAFE_SA_CMD0_BUNDLE 0x00000020 /* bundled operation (resvd) */
353#define SAFE_SA_CMD0_PAD 0x000000c0 /* crypto pad method */
354#define SAFE_SA_CMD0_PAD_IPSEC 0x00000000 /* IPsec padding */
355#define SAFE_SA_CMD0_PAD_PKCS7 0x00000040 /* PKCS#7 padding */
356#define SAFE_SA_CMD0_PAD_CONS 0x00000080 /* constant padding */
357#define SAFE_SA_CMD0_PAD_ZERO 0x000000c0 /* zero padding */
358#define SAFE_SA_CMD0_CRYPT_ALG 0x00000f00 /* symmetric crypto algorithm */
359#define SAFE_SA_CMD0_DES 0x00000000 /* DES crypto algorithm */
360#define SAFE_SA_CMD0_3DES 0x00000100 /* 3DES crypto algorithm */
361#define SAFE_SA_CMD0_AES 0x00000300 /* AES crypto algorithm */
362#define SAFE_SA_CMD0_CRYPT_NULL 0x00000f00 /* null crypto algorithm */
363#define SAFE_SA_CMD0_HASH_ALG 0x0000f000 /* hash algorithm */
364#define SAFE_SA_CMD0_MD5 0x00000000 /* MD5 hash algorithm */
365#define SAFE_SA_CMD0_SHA1 0x00001000 /* SHA-1 hash algorithm */
366#define SAFE_SA_CMD0_HASH_NULL 0x0000f000 /* null hash algorithm */
367#define SAFE_SA_CMD0_HDR_PROC 0x00080000 /* header processing */
368#define SAFE_SA_CMD0_IBUSID 0x00300000 /* input bus id */
369#define SAFE_SA_CMD0_IPCI 0x00100000 /* PCI input bus id */
370#define SAFE_SA_CMD0_OBUSID 0x00c00000 /* output bus id */
371#define SAFE_SA_CMD0_OPCI 0x00400000 /* PCI output bus id */
372#define SAFE_SA_CMD0_IVLD 0x03000000 /* IV loading */
373#define SAFE_SA_CMD0_IVLD_NONE 0x00000000 /* IV no load (reuse) */
374#define SAFE_SA_CMD0_IVLD_IBUF 0x01000000 /* IV load from input buffer */
375#define SAFE_SA_CMD0_IVLD_STATE 0x02000000 /* IV load from state */
376#define SAFE_SA_CMD0_HSLD 0x0c000000 /* hash state loading */
377#define SAFE_SA_CMD0_HSLD_SA 0x00000000 /* hash state load from SA */
378#define SAFE_SA_CMD0_HSLD_STATE 0x08000000 /* hash state load from state */
379#define SAFE_SA_CMD0_HSLD_NONE 0x0c000000 /* hash state no load */
380#define SAFE_SA_CMD0_SAVEIV 0x10000000 /* save IV */
381#define SAFE_SA_CMD0_SAVEHASH 0x20000000 /* save hash state */
382#define SAFE_SA_CMD0_IGATHER 0x40000000 /* input gather */
383#define SAFE_SA_CMD0_OSCATTER 0x80000000 /* output scatter */
384
385#define SAFE_SA_CMD1_HDRCOPY 0x00000002 /* copy header to output */
386#define SAFE_SA_CMD1_PAYCOPY 0x00000004 /* copy payload to output */
387#define SAFE_SA_CMD1_PADCOPY 0x00000008 /* copy pad to output */
388#define SAFE_SA_CMD1_IPV4 0x00000000 /* IPv4 protocol */
389#define SAFE_SA_CMD1_IPV6 0x00000010 /* IPv6 protocol */
390#define SAFE_SA_CMD1_MUTABLE 0x00000020 /* mutable bit processing */
391#define SAFE_SA_CMD1_SRBUSID 0x000000c0 /* state record bus id */
392#define SAFE_SA_CMD1_SRPCI 0x00000040 /* state record from PCI */
393#define SAFE_SA_CMD1_CRMODE 0x00000300 /* crypto mode */
394#define SAFE_SA_CMD1_ECB 0x00000000 /* ECB crypto mode */
395#define SAFE_SA_CMD1_CBC 0x00000100 /* CBC crypto mode */
396#define SAFE_SA_CMD1_OFB 0x00000200 /* OFB crypto mode */
397#define SAFE_SA_CMD1_CFB 0x00000300 /* CFB crypto mode */
398#define SAFE_SA_CMD1_CRFEEDBACK 0x00000c00 /* crypto feedback mode */
399#define SAFE_SA_CMD1_64BIT 0x00000000 /* 64-bit crypto feedback */
400#define SAFE_SA_CMD1_8BIT 0x00000400 /* 8-bit crypto feedback */
401#define SAFE_SA_CMD1_1BIT 0x00000800 /* 1-bit crypto feedback */
402#define SAFE_SA_CMD1_128BIT 0x00000c00 /* 128-bit crypto feedback */
403#define SAFE_SA_CMD1_OPTIONS 0x00001000 /* HMAC/options mutable bit */
404#define SAFE_SA_CMD1_HMAC SAFE_SA_CMD1_OPTIONS
405#define SAFE_SA_CMD1_SAREV1 0x00008000 /* SA Revision 1 */
406#define SAFE_SA_CMD1_OFFSET 0x00ff0000 /* hash/crypto offset(dwords) */
407#define SAFE_SA_CMD1_OFFSET_S 16
408#define SAFE_SA_CMD1_AESKEYLEN 0x0f000000 /* AES key length */
409#define SAFE_SA_CMD1_AES128 0x02000000 /* 128-bit AES key */
410#define SAFE_SA_CMD1_AES192 0x03000000 /* 192-bit AES key */
411#define SAFE_SA_CMD1_AES256 0x04000000 /* 256-bit AES key */
412
413/*
414 * Security Associate State Record (Rev 1).
415 */
416struct safe_sastate {
417    u_int32_t sa_saved_iv[4]; /* saved IV (DES/3DES/AES) */
418    u_int32_t sa_saved_hashbc; /* saved hash byte count */
419    u_int32_t sa_saved_indigest[5]; /* saved inner digest */
420};
421#endif /* _SAFE_SAFEREG_H_ */
422

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