| 1 | /* |
| 2 | * Freescale SEC (talitos) device dependent data structures |
| 3 | * |
| 4 | * Copyright (c) 2006 Freescale Semiconductor, Inc. |
| 5 | * |
| 6 | * Redistribution and use in source and binary forms, with or without |
| 7 | * modification, are permitted provided that the following conditions |
| 8 | * are met: |
| 9 | * |
| 10 | * 1. Redistributions of source code must retain the above copyright |
| 11 | * notice, this list of conditions and the following disclaimer. |
| 12 | * 2. Redistributions in binary form must reproduce the above copyright |
| 13 | * notice, this list of conditions and the following disclaimer in the |
| 14 | * documentation and/or other materials provided with the distribution. |
| 15 | * 3. The name of the author may not be used to endorse or promote products |
| 16 | * derived from this software without specific prior written permission. |
| 17 | * |
| 18 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
| 19 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
| 20 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
| 21 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
| 22 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
| 23 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
| 24 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
| 25 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| 26 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
| 27 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| 28 | * |
| 29 | */ |
| 30 | |
| 31 | /* device ID register values */ |
| 32 | #define TALITOS_ID_SEC_2_0 0x40 |
| 33 | #define TALITOS_ID_SEC_2_1 0x40 /* cross ref with IP block revision reg */ |
| 34 | |
| 35 | /* |
| 36 | * following num_channels, channel-fifo-depth, exec-unit-mask, and |
| 37 | * descriptor-types-mask are for forward-compatibility with openfirmware |
| 38 | * flat device trees |
| 39 | */ |
| 40 | |
| 41 | /* |
| 42 | * num_channels : the number of channels available in each SEC version. |
| 43 | */ |
| 44 | |
| 45 | /* n.b. this driver requires these values be a power of 2 */ |
| 46 | #define TALITOS_NCHANNELS_SEC_1_0 4 |
| 47 | #define TALITOS_NCHANNELS_SEC_1_2 1 |
| 48 | #define TALITOS_NCHANNELS_SEC_2_0 4 |
| 49 | #define TALITOS_NCHANNELS_SEC_2_01 4 |
| 50 | #define TALITOS_NCHANNELS_SEC_2_1 4 |
| 51 | #define TALITOS_NCHANNELS_SEC_2_4 4 |
| 52 | |
| 53 | /* |
| 54 | * channel-fifo-depth : The number of descriptor |
| 55 | * pointers a channel fetch fifo can hold. |
| 56 | */ |
| 57 | #define TALITOS_CHFIFOLEN_SEC_1_0 1 |
| 58 | #define TALITOS_CHFIFOLEN_SEC_1_2 1 |
| 59 | #define TALITOS_CHFIFOLEN_SEC_2_0 24 |
| 60 | #define TALITOS_CHFIFOLEN_SEC_2_01 24 |
| 61 | #define TALITOS_CHFIFOLEN_SEC_2_1 24 |
| 62 | #define TALITOS_CHFIFOLEN_SEC_2_4 24 |
| 63 | |
| 64 | /* |
| 65 | * exec-unit-mask : The bitmask representing what Execution Units (EUs) |
| 66 | * are available. EU information should be encoded following the SEC's |
| 67 | * EU_SEL0 bitfield documentation, i.e. as follows: |
| 68 | * |
| 69 | * bit 31 = set if SEC permits no-EU selection (should be always set) |
| 70 | * bit 30 = set if SEC has the ARC4 EU (AFEU) |
| 71 | * bit 29 = set if SEC has the des/3des EU (DEU) |
| 72 | * bit 28 = set if SEC has the message digest EU (MDEU) |
| 73 | * bit 27 = set if SEC has the random number generator EU (RNG) |
| 74 | * bit 26 = set if SEC has the public key EU (PKEU) |
| 75 | * bit 25 = set if SEC has the aes EU (AESU) |
| 76 | * bit 24 = set if SEC has the Kasumi EU (KEU) |
| 77 | * |
| 78 | */ |
| 79 | #define TALITOS_HAS_EU_NONE (1<<0) |
| 80 | #define TALITOS_HAS_EU_AFEU (1<<1) |
| 81 | #define TALITOS_HAS_EU_DEU (1<<2) |
| 82 | #define TALITOS_HAS_EU_MDEU (1<<3) |
| 83 | #define TALITOS_HAS_EU_RNG (1<<4) |
| 84 | #define TALITOS_HAS_EU_PKEU (1<<5) |
| 85 | #define TALITOS_HAS_EU_AESU (1<<6) |
| 86 | #define TALITOS_HAS_EU_KEU (1<<7) |
| 87 | |
| 88 | /* the corresponding masks for each SEC version */ |
| 89 | #define TALITOS_HAS_EUS_SEC_1_0 0x7f |
| 90 | #define TALITOS_HAS_EUS_SEC_1_2 0x4d |
| 91 | #define TALITOS_HAS_EUS_SEC_2_0 0x7f |
| 92 | #define TALITOS_HAS_EUS_SEC_2_01 0x7f |
| 93 | #define TALITOS_HAS_EUS_SEC_2_1 0xff |
| 94 | #define TALITOS_HAS_EUS_SEC_2_4 0x7f |
| 95 | |
| 96 | /* |
| 97 | * descriptor-types-mask : The bitmask representing what descriptors |
| 98 | * are available. Descriptor type information should be encoded |
| 99 | * following the SEC's Descriptor Header Dword DESC_TYPE field |
| 100 | * documentation, i.e. as follows: |
| 101 | * |
| 102 | * bit 0 = set if SEC supports the aesu_ctr_nonsnoop desc. type |
| 103 | * bit 1 = set if SEC supports the ipsec_esp descriptor type |
| 104 | * bit 2 = set if SEC supports the common_nonsnoop desc. type |
| 105 | * bit 3 = set if SEC supports the 802.11i AES ccmp desc. type |
| 106 | * bit 4 = set if SEC supports the hmac_snoop_no_afeu desc. type |
| 107 | * bit 5 = set if SEC supports the srtp descriptor type |
| 108 | * bit 6 = set if SEC supports the non_hmac_snoop_no_afeu desc.type |
| 109 | * bit 7 = set if SEC supports the pkeu_assemble descriptor type |
| 110 | * bit 8 = set if SEC supports the aesu_key_expand_output desc.type |
| 111 | * bit 9 = set if SEC supports the pkeu_ptmul descriptor type |
| 112 | * bit 10 = set if SEC supports the common_nonsnoop_afeu desc. type |
| 113 | * bit 11 = set if SEC supports the pkeu_ptadd_dbl descriptor type |
| 114 | * |
| 115 | * ..and so on and so forth. |
| 116 | */ |
| 117 | #define TALITOS_HAS_DT_AESU_CTR_NONSNOOP (1<<0) |
| 118 | #define TALITOS_HAS_DT_IPSEC_ESP (1<<1) |
| 119 | #define TALITOS_HAS_DT_COMMON_NONSNOOP (1<<2) |
| 120 | |
| 121 | /* the corresponding masks for each SEC version */ |
| 122 | #define TALITOS_HAS_DESCTYPES_SEC_2_0 0x01010ebf |
| 123 | #define TALITOS_HAS_DESCTYPES_SEC_2_1 0x012b0ebf |
| 124 | |
| 125 | /* |
| 126 | * a TALITOS_xxx_HI address points to the low data bits (32-63) of the register |
| 127 | */ |
| 128 | |
| 129 | /* global register offset addresses */ |
| 130 | #define TALITOS_ID 0x1020 |
| 131 | #define TALITOS_ID_HI 0x1024 |
| 132 | #define TALITOS_MCR 0x1030 /* master control register */ |
| 133 | #define TALITOS_MCR_HI 0x1038 /* master control register */ |
| 134 | #define TALITOS_MCR_SWR 0x1 |
| 135 | #define TALITOS_IMR 0x1008 /* interrupt mask register */ |
| 136 | #define TALITOS_IMR_ALL 0x00010fff /* enable all interrupts mask */ |
| 137 | #define TALITOS_IMR_ERRONLY 0x00010aaa /* enable error interrupts */ |
| 138 | #define TALITOS_IMR_HI 0x100C /* interrupt mask register */ |
| 139 | #define TALITOS_IMR_HI_ALL 0x00323333 /* enable all interrupts mask */ |
| 140 | #define TALITOS_IMR_HI_ERRONLY 0x00222222 /* enable error interrupts */ |
| 141 | #define TALITOS_ISR 0x1010 /* interrupt status register */ |
| 142 | #define TALITOS_ISR_ERROR 0x00010faa /* errors mask */ |
| 143 | #define TALITOS_ISR_DONE 0x00000055 /* channel(s) done mask */ |
| 144 | #define TALITOS_ISR_HI 0x1014 /* interrupt status register */ |
| 145 | #define TALITOS_ICR 0x1018 /* interrupt clear register */ |
| 146 | #define TALITOS_ICR_HI 0x101C /* interrupt clear register */ |
| 147 | |
| 148 | /* channel register address stride */ |
| 149 | #define TALITOS_CH_OFFSET 0x100 |
| 150 | |
| 151 | /* channel register offset addresses and bits */ |
| 152 | #define TALITOS_CH_CCCR 0x1108 /* Crypto-Channel Config Register */ |
| 153 | #define TALITOS_CH_CCCR_RESET 0x1 /* Channel Reset bit */ |
| 154 | #define TALITOS_CH_CCCR_HI 0x110c /* Crypto-Channel Config Register */ |
| 155 | #define TALITOS_CH_CCCR_HI_CDWE 0x10 /* Channel done writeback enable bit */ |
| 156 | #define TALITOS_CH_CCCR_HI_NT 0x4 /* Notification type bit */ |
| 157 | #define TALITOS_CH_CCCR_HI_CDIE 0x2 /* Channel Done Interrupt Enable bit */ |
| 158 | #define TALITOS_CH_CCPSR 0x1110 /* Crypto-Channel Pointer Status Reg */ |
| 159 | #define TALITOS_CH_CCPSR_HI 0x1114 /* Crypto-Channel Pointer Status Reg */ |
| 160 | #define TALITOS_CH_FF 0x1148 /* Fetch FIFO */ |
| 161 | #define TALITOS_CH_FF_HI 0x114c /* Fetch FIFO's FETCH_ADRS */ |
| 162 | #define TALITOS_CH_CDPR 0x1140 /* Crypto-Channel Pointer Status Reg */ |
| 163 | #define TALITOS_CH_CDPR_HI 0x1144 /* Crypto-Channel Pointer Status Reg */ |
| 164 | #define TALITOS_CH_DESCBUF 0x1180 /* (thru 11bf) Crypto-Channel |
| 165 | * Descriptor Buffer (debug) */ |
| 166 | |
| 167 | /* execution unit register offset addresses and bits */ |
| 168 | #define TALITOS_DEUSR 0x2028 /* DEU status register */ |
| 169 | #define TALITOS_DEUSR_HI 0x202c /* DEU status register */ |
| 170 | #define TALITOS_DEUISR 0x2030 /* DEU interrupt status register */ |
| 171 | #define TALITOS_DEUISR_HI 0x2034 /* DEU interrupt status register */ |
| 172 | #define TALITOS_DEUICR 0x2038 /* DEU interrupt control register */ |
| 173 | #define TALITOS_DEUICR_HI 0x203c /* DEU interrupt control register */ |
| 174 | #define TALITOS_AESUISR 0x4030 /* AESU interrupt status register */ |
| 175 | #define TALITOS_AESUISR_HI 0x4034 /* AESU interrupt status register */ |
| 176 | #define TALITOS_AESUICR 0x4038 /* AESU interrupt control register */ |
| 177 | #define TALITOS_AESUICR_HI 0x403c /* AESU interrupt control register */ |
| 178 | #define TALITOS_MDEUISR 0x6030 /* MDEU interrupt status register */ |
| 179 | #define TALITOS_MDEUISR_HI 0x6034 /* MDEU interrupt status register */ |
| 180 | #define TALITOS_RNGSR 0xa028 /* RNG status register */ |
| 181 | #define TALITOS_RNGSR_HI 0xa02c /* RNG status register */ |
| 182 | #define TALITOS_RNGSR_HI_RD 0x1 /* RNG Reset done */ |
| 183 | #define TALITOS_RNGSR_HI_OFL 0xff0000/* number of dwords in RNG output FIFO*/ |
| 184 | #define TALITOS_RNGDSR 0xa010 /* RNG data size register */ |
| 185 | #define TALITOS_RNGDSR_HI 0xa014 /* RNG data size register */ |
| 186 | #define TALITOS_RNG_FIFO 0xa800 /* RNG FIFO - pool of random numbers */ |
| 187 | #define TALITOS_RNGISR 0xa030 /* RNG Interrupt status register */ |
| 188 | #define TALITOS_RNGISR_HI 0xa034 /* RNG Interrupt status register */ |
| 189 | #define TALITOS_RNGRCR 0xa018 /* RNG Reset control register */ |
| 190 | #define TALITOS_RNGRCR_HI 0xa01c /* RNG Reset control register */ |
| 191 | #define TALITOS_RNGRCR_HI_SR 0x1 /* RNG RNGRCR:Software Reset */ |
| 192 | |
| 193 | /* descriptor pointer entry */ |
| 194 | struct talitos_desc_ptr { |
| 195 | u16 len; /* length */ |
| 196 | u8 extent; /* jump (to s/g link table) and extent */ |
| 197 | u8 res; /* reserved */ |
| 198 | u32 ptr; /* pointer */ |
| 199 | }; |
| 200 | |
| 201 | /* descriptor */ |
| 202 | struct talitos_desc { |
| 203 | u32 hdr; /* header */ |
| 204 | u32 res; /* reserved */ |
| 205 | struct talitos_desc_ptr ptr[7]; /* ptr/len pair array */ |
| 206 | }; |
| 207 | |
| 208 | /* talitos descriptor header (hdr) bits */ |
| 209 | |
| 210 | /* primary execution unit select */ |
| 211 | #define TALITOS_SEL0_AFEU 0x10000000 |
| 212 | #define TALITOS_SEL0_DEU 0x20000000 |
| 213 | #define TALITOS_SEL0_MDEU 0x30000000 |
| 214 | #define TALITOS_SEL0_RNG 0x40000000 |
| 215 | #define TALITOS_SEL0_PKEU 0x50000000 |
| 216 | #define TALITOS_SEL0_AESU 0x60000000 |
| 217 | |
| 218 | /* primary execution unit mode (MODE0) and derivatives */ |
| 219 | #define TALITOS_MODE0_AESU_CBC 0x00200000 |
| 220 | #define TALITOS_MODE0_AESU_ENC 0x00100000 |
| 221 | #define TALITOS_MODE0_DEU_CBC 0x00400000 |
| 222 | #define TALITOS_MODE0_DEU_3DES 0x00200000 |
| 223 | #define TALITOS_MODE0_DEU_ENC 0x00100000 |
| 224 | #define TALITOS_MODE0_MDEU_INIT 0x01000000 /* init starting regs */ |
| 225 | #define TALITOS_MODE0_MDEU_HMAC 0x00800000 |
| 226 | #define TALITOS_MODE0_MDEU_PAD 0x00400000 /* PD */ |
| 227 | #define TALITOS_MODE0_MDEU_MD5 0x00200000 |
| 228 | #define TALITOS_MODE0_MDEU_SHA256 0x00100000 |
| 229 | #define TALITOS_MODE0_MDEU_SHA1 0x00000000 /* SHA-160 */ |
| 230 | #define TALITOS_MODE0_MDEU_MD5_HMAC \ |
| 231 | (TALITOS_MODE0_MDEU_MD5 | TALITOS_MODE0_MDEU_HMAC) |
| 232 | #define TALITOS_MODE0_MDEU_SHA256_HMAC \ |
| 233 | (TALITOS_MODE0_MDEU_SHA256 | TALITOS_MODE0_MDEU_HMAC) |
| 234 | #define TALITOS_MODE0_MDEU_SHA1_HMAC \ |
| 235 | (TALITOS_MODE0_MDEU_SHA1 | TALITOS_MODE0_MDEU_HMAC) |
| 236 | |
| 237 | /* secondary execution unit select (SEL1) */ |
| 238 | /* it's MDEU or nothing */ |
| 239 | #define TALITOS_SEL1_MDEU 0x00030000 |
| 240 | |
| 241 | /* secondary execution unit mode (MODE1) and derivatives */ |
| 242 | #define TALITOS_MODE1_MDEU_INIT 0x00001000 /* init starting regs */ |
| 243 | #define TALITOS_MODE1_MDEU_HMAC 0x00000800 |
| 244 | #define TALITOS_MODE1_MDEU_PAD 0x00000400 /* PD */ |
| 245 | #define TALITOS_MODE1_MDEU_MD5 0x00000200 |
| 246 | #define TALITOS_MODE1_MDEU_SHA256 0x00000100 |
| 247 | #define TALITOS_MODE1_MDEU_SHA1 0x00000000 /* SHA-160 */ |
| 248 | #define TALITOS_MODE1_MDEU_MD5_HMAC \ |
| 249 | (TALITOS_MODE1_MDEU_MD5 | TALITOS_MODE1_MDEU_HMAC) |
| 250 | #define TALITOS_MODE1_MDEU_SHA256_HMAC \ |
| 251 | (TALITOS_MODE1_MDEU_SHA256 | TALITOS_MODE1_MDEU_HMAC) |
| 252 | #define TALITOS_MODE1_MDEU_SHA1_HMAC \ |
| 253 | (TALITOS_MODE1_MDEU_SHA1 | TALITOS_MODE1_MDEU_HMAC) |
| 254 | |
| 255 | /* direction of overall data flow (DIR) */ |
| 256 | #define TALITOS_DIR_OUTBOUND 0x00000000 |
| 257 | #define TALITOS_DIR_INBOUND 0x00000002 |
| 258 | |
| 259 | /* done notification (DN) */ |
| 260 | #define TALITOS_DONE_NOTIFY 0x00000001 |
| 261 | |
| 262 | /* descriptor types */ |
| 263 | /* odd numbers here are valid on SEC2 and greater only (e.g. ipsec_esp) */ |
| 264 | #define TD_TYPE_AESU_CTR_NONSNOOP (0 << 3) |
| 265 | #define TD_TYPE_IPSEC_ESP (1 << 3) |
| 266 | #define TD_TYPE_COMMON_NONSNOOP_NO_AFEU (2 << 3) |
| 267 | #define TD_TYPE_HMAC_SNOOP_NO_AFEU (4 << 3) |
| 268 | |
| 269 | #define TALITOS_HDR_DONE_BITS 0xff000000 |
| 270 | |
| 271 | #define DPRINTF(a...) do { \ |
| 272 | if (debug) { \ |
| 273 | printk("%s: ", sc ? \ |
| 274 | device_get_nameunit(sc->sc_cdev) : "talitos"); \ |
| 275 | printk(a); \ |
| 276 | } \ |
| 277 | } while (0) |
| 278 | |
