| 1 | /* |
| 2 | * ADM6996 switch driver |
| 3 | * |
| 4 | * Copyright (c) 2008 Felix Fietkau <nbd@openwrt.org> |
| 5 | * Copyright (c) 2010,2011 Peter Lebbing <peter@digitalbrains.com> |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify it |
| 8 | * under the terms of the GNU General Public License v2 as published by the |
| 9 | * Free Software Foundation |
| 10 | */ |
| 11 | #ifndef __ADM6996_H |
| 12 | #define __ADM6996_H |
| 13 | |
| 14 | /* |
| 15 | * ADM_PHY_PORTS: Number of ports with a PHY. |
| 16 | * We only control ports 0 to 3, because if 4 is connected, it is most likely |
| 17 | * not connected to the switch but to a separate MII and MAC for the WAN port. |
| 18 | */ |
| 19 | #define ADM_PHY_PORTS 4 |
| 20 | #define ADM_NUM_PORTS 6 |
| 21 | #define ADM_CPU_PORT 5 |
| 22 | |
| 23 | #define ADM_NUM_VLANS 16 |
| 24 | #define ADM_VLAN_MAX_ID 4094 |
| 25 | |
| 26 | enum admreg { |
| 27 | ADM_EEPROM_BASE = 0x0, |
| 28 | ADM_P0_CFG = ADM_EEPROM_BASE + 1, |
| 29 | ADM_P1_CFG = ADM_EEPROM_BASE + 3, |
| 30 | ADM_P2_CFG = ADM_EEPROM_BASE + 5, |
| 31 | ADM_P3_CFG = ADM_EEPROM_BASE + 7, |
| 32 | ADM_P4_CFG = ADM_EEPROM_BASE + 8, |
| 33 | ADM_P5_CFG = ADM_EEPROM_BASE + 9, |
| 34 | ADM_SYSC0 = ADM_EEPROM_BASE + 0xa, |
| 35 | ADM_VLAN_PRIOMAP = ADM_EEPROM_BASE + 0xe, |
| 36 | ADM_SYSC3 = ADM_EEPROM_BASE + 0x11, |
| 37 | /* Input Force No Tag Enable */ |
| 38 | ADM_IFNTE = ADM_EEPROM_BASE + 0x20, |
| 39 | ADM_VID_CHECK = ADM_EEPROM_BASE + 0x26, |
| 40 | ADM_P0_PVID = ADM_EEPROM_BASE + 0x28, |
| 41 | ADM_P1_PVID = ADM_EEPROM_BASE + 0x29, |
| 42 | /* Output Tag Bypass Enable and P2 PVID */ |
| 43 | ADM_OTBE_P2_PVID = ADM_EEPROM_BASE + 0x2a, |
| 44 | ADM_P3_P4_PVID = ADM_EEPROM_BASE + 0x2b, |
| 45 | ADM_P5_PVID = ADM_EEPROM_BASE + 0x2c, |
| 46 | ADM_EEPROM_EXT_BASE = 0x40, |
| 47 | #define ADM_VLAN_FILT_L(n) (ADM_EEPROM_EXT_BASE + 2 * (n)) |
| 48 | #define ADM_VLAN_FILT_H(n) (ADM_EEPROM_EXT_BASE + 1 + 2 * (n)) |
| 49 | ADM_COUNTER_BASE = 0xa0, |
| 50 | ADM_SIG0 = ADM_COUNTER_BASE + 0, |
| 51 | ADM_SIG1 = ADM_COUNTER_BASE + 1, |
| 52 | ADM_PHY_BASE = 0x200, |
| 53 | #define ADM_PHY_PORT(n) (ADM_PHY_BASE + (0x20 * n)) |
| 54 | }; |
| 55 | |
| 56 | /* Chip identification patterns */ |
| 57 | #define ADM_SIG0_MASK 0xffff |
| 58 | #define ADM_SIG0_VAL 0x1023 |
| 59 | #define ADM_SIG1_MASK 0xffff |
| 60 | #define ADM_SIG1_VAL 0x0007 |
| 61 | |
| 62 | enum { |
| 63 | ADM_PHYCFG_COLTST = (1 << 7), /* Enable collision test */ |
| 64 | ADM_PHYCFG_DPLX = (1 << 8), /* Enable full duplex */ |
| 65 | ADM_PHYCFG_ANEN_RST = (1 << 9), /* Restart auto negotiation (self clear) */ |
| 66 | ADM_PHYCFG_ISO = (1 << 10), /* Isolate PHY */ |
| 67 | ADM_PHYCFG_PDN = (1 << 11), /* Power down PHY */ |
| 68 | ADM_PHYCFG_ANEN = (1 << 12), /* Enable auto negotiation */ |
| 69 | ADM_PHYCFG_SPEED_100 = (1 << 13), /* Enable 100 Mbit/s */ |
| 70 | ADM_PHYCFG_LPBK = (1 << 14), /* Enable loopback operation */ |
| 71 | ADM_PHYCFG_RST = (1 << 15), /* Reset the port (self clear) */ |
| 72 | ADM_PHYCFG_INIT = ( |
| 73 | ADM_PHYCFG_RST | |
| 74 | ADM_PHYCFG_SPEED_100 | |
| 75 | ADM_PHYCFG_ANEN | |
| 76 | ADM_PHYCFG_ANEN_RST |
| 77 | ) |
| 78 | }; |
| 79 | |
| 80 | enum { |
| 81 | ADM_PORTCFG_FC = (1 << 0), /* Enable 802.x flow control */ |
| 82 | ADM_PORTCFG_AN = (1 << 1), /* Enable auto-negotiation */ |
| 83 | ADM_PORTCFG_SPEED_100 = (1 << 2), /* Enable 100 Mbit/s */ |
| 84 | ADM_PORTCFG_DPLX = (1 << 3), /* Enable full duplex */ |
| 85 | ADM_PORTCFG_OT = (1 << 4), /* Output tagged packets */ |
| 86 | ADM_PORTCFG_PD = (1 << 5), /* Port disable */ |
| 87 | ADM_PORTCFG_TV_PRIO = (1 << 6), /* 0 = VLAN based priority |
| 88 | * 1 = TOS based priority */ |
| 89 | ADM_PORTCFG_PPE = (1 << 7), /* Port based priority enable */ |
| 90 | ADM_PORTCFG_PP_S = (1 << 8), /* Port based priority, 2 bits */ |
| 91 | ADM_PORTCFG_PVID_BASE = (1 << 10), /* Primary VLAN id, 4 bits */ |
| 92 | ADM_PORTCFG_FSE = (1 << 14), /* Fx select enable */ |
| 93 | ADM_PORTCFG_CAM = (1 << 15), /* Crossover Auto MDIX */ |
| 94 | |
| 95 | ADM_PORTCFG_INIT = ( |
| 96 | ADM_PORTCFG_FC | |
| 97 | ADM_PORTCFG_AN | |
| 98 | ADM_PORTCFG_SPEED_100 | |
| 99 | ADM_PORTCFG_DPLX | |
| 100 | ADM_PORTCFG_CAM |
| 101 | ), |
| 102 | ADM_PORTCFG_CPU = ( |
| 103 | ADM_PORTCFG_FC | |
| 104 | ADM_PORTCFG_SPEED_100 | |
| 105 | ADM_PORTCFG_OT | |
| 106 | ADM_PORTCFG_DPLX |
| 107 | ), |
| 108 | }; |
| 109 | |
| 110 | #define ADM_PORTCFG_PPID(n) ((n & 0x3) << 8) |
| 111 | #define ADM_PORTCFG_PVID(n) ((n & 0xf) << 10) |
| 112 | #define ADM_PORTCFG_PVID_MASK (0xf << 10) |
| 113 | |
| 114 | #define ADM_IFNTE_MASK (0x3f << 9) |
| 115 | #define ADM_VID_CHECK_MASK (0x3f << 6) |
| 116 | |
| 117 | #define ADM_P0_PVID_VAL(n) ((((n) & 0xff0) >> 4) << 0) |
| 118 | #define ADM_P1_PVID_VAL(n) ((((n) & 0xff0) >> 4) << 0) |
| 119 | #define ADM_P2_PVID_VAL(n) ((((n) & 0xff0) >> 4) << 0) |
| 120 | #define ADM_P3_PVID_VAL(n) ((((n) & 0xff0) >> 4) << 0) |
| 121 | #define ADM_P4_PVID_VAL(n) ((((n) & 0xff0) >> 4) << 8) |
| 122 | #define ADM_P5_PVID_VAL(n) ((((n) & 0xff0) >> 4) << 0) |
| 123 | #define ADM_P2_PVID_MASK 0xff |
| 124 | |
| 125 | #define ADM_OTBE(n) (((n) & 0x3f) << 8) |
| 126 | #define ADM_OTBE_MASK (0x3f << 8) |
| 127 | |
| 128 | /* ADM_SYSC0 */ |
| 129 | enum { |
| 130 | ADM_NTTE = (1 << 2), /* New Tag Transmit Enable */ |
| 131 | ADM_RVID1 = (1 << 8) /* Replace VLAN ID 1 */ |
| 132 | }; |
| 133 | |
| 134 | /* Tag Based VLAN in ADM_SYSC3 */ |
| 135 | #define ADM_TBV (1 << 5) |
| 136 | |
| 137 | static const u8 adm_portcfg[] = { |
| 138 | [0] = ADM_P0_CFG, |
| 139 | [1] = ADM_P1_CFG, |
| 140 | [2] = ADM_P2_CFG, |
| 141 | [3] = ADM_P3_CFG, |
| 142 | [4] = ADM_P4_CFG, |
| 143 | [5] = ADM_P5_CFG, |
| 144 | }; |
| 145 | |
| 146 | /* Fields in ADM_VLAN_FILT_L(x) */ |
| 147 | #define ADM_VLAN_FILT_FID(n) (((n) & 0xf) << 12) |
| 148 | #define ADM_VLAN_FILT_TAGGED(n) (((n) & 0x3f) << 6) |
| 149 | #define ADM_VLAN_FILT_MEMBER(n) (((n) & 0x3f) << 0) |
| 150 | #define ADM_VLAN_FILT_MEMBER_MASK 0x3f |
| 151 | /* Fields in ADM_VLAN_FILT_H(x) */ |
| 152 | #define ADM_VLAN_FILT_VALID (1 << 15) |
| 153 | #define ADM_VLAN_FILT_VID(n) (((n) & 0xfff) << 0) |
| 154 | |
| 155 | |
| 156 | /* |
| 157 | * Split the register address in phy id and register |
| 158 | * it will get combined again by the mdio bus op |
| 159 | */ |
| 160 | #define PHYADDR(_reg) ((_reg >> 5) & 0xff), (_reg & 0x1f) |
| 161 | |
| 162 | #endif |
| 163 | |
