Root/target/linux/generic/files/drivers/net/phy/ar8216.c

1/*
2 * ar8216.c: AR8216 switch driver
3 *
4 * Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
5 * Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; either version 2
10 * of the License, or (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 */
17
18#include <linux/if.h>
19#include <linux/module.h>
20#include <linux/init.h>
21#include <linux/list.h>
22#include <linux/if_ether.h>
23#include <linux/skbuff.h>
24#include <linux/netdevice.h>
25#include <linux/netlink.h>
26#include <linux/bitops.h>
27#include <net/genetlink.h>
28#include <linux/switch.h>
29#include <linux/delay.h>
30#include <linux/phy.h>
31#include <linux/netdevice.h>
32#include <linux/etherdevice.h>
33#include <linux/lockdep.h>
34#include <linux/ar8216_platform.h>
35#include <linux/workqueue.h>
36#include "ar8216.h"
37
38/* size of the vlan table */
39#define AR8X16_MAX_VLANS 128
40#define AR8X16_PROBE_RETRIES 10
41#define AR8X16_MAX_PORTS 8
42
43#define AR8XXX_MIB_WORK_DELAY 2000 /* msecs */
44
45struct ar8216_priv;
46
47#define AR8XXX_CAP_GIGE BIT(0)
48#define AR8XXX_CAP_MIB_COUNTERS BIT(1)
49
50enum {
51    AR8XXX_VER_AR8216 = 0x01,
52    AR8XXX_VER_AR8236 = 0x03,
53    AR8XXX_VER_AR8316 = 0x10,
54    AR8XXX_VER_AR8327 = 0x12,
55};
56
57struct ar8xxx_mib_desc {
58    unsigned int size;
59    unsigned int offset;
60    const char *name;
61};
62
63struct ar8xxx_chip {
64    unsigned long caps;
65
66    int (*hw_init)(struct ar8216_priv *priv);
67    void (*init_globals)(struct ar8216_priv *priv);
68    void (*init_port)(struct ar8216_priv *priv, int port);
69    void (*setup_port)(struct ar8216_priv *priv, int port, u32 egress,
70               u32 ingress, u32 members, u32 pvid);
71    u32 (*read_port_status)(struct ar8216_priv *priv, int port);
72    int (*atu_flush)(struct ar8216_priv *priv);
73    void (*vtu_flush)(struct ar8216_priv *priv);
74    void (*vtu_load_vlan)(struct ar8216_priv *priv, u32 vid, u32 port_mask);
75
76    const struct ar8xxx_mib_desc *mib_decs;
77    unsigned num_mibs;
78};
79
80struct ar8216_priv {
81    struct switch_dev dev;
82    struct phy_device *phy;
83    u32 (*read)(struct ar8216_priv *priv, int reg);
84    void (*write)(struct ar8216_priv *priv, int reg, u32 val);
85    const struct net_device_ops *ndo_old;
86    struct net_device_ops ndo;
87    struct mutex reg_mutex;
88    u8 chip_ver;
89    u8 chip_rev;
90    const struct ar8xxx_chip *chip;
91    bool initialized;
92    bool port4_phy;
93    char buf[2048];
94
95    bool init;
96    bool mii_lo_first;
97
98    struct mutex mib_lock;
99    struct delayed_work mib_work;
100    int mib_next_port;
101    u64 *mib_stats;
102
103    /* all fields below are cleared on reset */
104    bool vlan;
105    u16 vlan_id[AR8X16_MAX_VLANS];
106    u8 vlan_table[AR8X16_MAX_VLANS];
107    u8 vlan_tagged;
108    u16 pvid[AR8X16_MAX_PORTS];
109};
110
111#define MIB_DESC(_s , _o, _n) \
112    { \
113        .size = (_s), \
114        .offset = (_o), \
115        .name = (_n), \
116    }
117
118static const struct ar8xxx_mib_desc ar8216_mibs[] = {
119    MIB_DESC(1, AR8216_STATS_RXBROAD, "RxBroad"),
120    MIB_DESC(1, AR8216_STATS_RXPAUSE, "RxPause"),
121    MIB_DESC(1, AR8216_STATS_RXMULTI, "RxMulti"),
122    MIB_DESC(1, AR8216_STATS_RXFCSERR, "RxFcsErr"),
123    MIB_DESC(1, AR8216_STATS_RXALIGNERR, "RxAlignErr"),
124    MIB_DESC(1, AR8216_STATS_RXRUNT, "RxRunt"),
125    MIB_DESC(1, AR8216_STATS_RXFRAGMENT, "RxFragment"),
126    MIB_DESC(1, AR8216_STATS_RX64BYTE, "Rx64Byte"),
127    MIB_DESC(1, AR8216_STATS_RX128BYTE, "Rx128Byte"),
128    MIB_DESC(1, AR8216_STATS_RX256BYTE, "Rx256Byte"),
129    MIB_DESC(1, AR8216_STATS_RX512BYTE, "Rx512Byte"),
130    MIB_DESC(1, AR8216_STATS_RX1024BYTE, "Rx1024Byte"),
131    MIB_DESC(1, AR8216_STATS_RXMAXBYTE, "RxMaxByte"),
132    MIB_DESC(1, AR8216_STATS_RXTOOLONG, "RxTooLong"),
133    MIB_DESC(2, AR8216_STATS_RXGOODBYTE, "RxGoodByte"),
134    MIB_DESC(2, AR8216_STATS_RXBADBYTE, "RxBadByte"),
135    MIB_DESC(1, AR8216_STATS_RXOVERFLOW, "RxOverFlow"),
136    MIB_DESC(1, AR8216_STATS_FILTERED, "Filtered"),
137    MIB_DESC(1, AR8216_STATS_TXBROAD, "TxBroad"),
138    MIB_DESC(1, AR8216_STATS_TXPAUSE, "TxPause"),
139    MIB_DESC(1, AR8216_STATS_TXMULTI, "TxMulti"),
140    MIB_DESC(1, AR8216_STATS_TXUNDERRUN, "TxUnderRun"),
141    MIB_DESC(1, AR8216_STATS_TX64BYTE, "Tx64Byte"),
142    MIB_DESC(1, AR8216_STATS_TX128BYTE, "Tx128Byte"),
143    MIB_DESC(1, AR8216_STATS_TX256BYTE, "Tx256Byte"),
144    MIB_DESC(1, AR8216_STATS_TX512BYTE, "Tx512Byte"),
145    MIB_DESC(1, AR8216_STATS_TX1024BYTE, "Tx1024Byte"),
146    MIB_DESC(1, AR8216_STATS_TXMAXBYTE, "TxMaxByte"),
147    MIB_DESC(1, AR8216_STATS_TXOVERSIZE, "TxOverSize"),
148    MIB_DESC(2, AR8216_STATS_TXBYTE, "TxByte"),
149    MIB_DESC(1, AR8216_STATS_TXCOLLISION, "TxCollision"),
150    MIB_DESC(1, AR8216_STATS_TXABORTCOL, "TxAbortCol"),
151    MIB_DESC(1, AR8216_STATS_TXMULTICOL, "TxMultiCol"),
152    MIB_DESC(1, AR8216_STATS_TXSINGLECOL, "TxSingleCol"),
153    MIB_DESC(1, AR8216_STATS_TXEXCDEFER, "TxExcDefer"),
154    MIB_DESC(1, AR8216_STATS_TXDEFER, "TxDefer"),
155    MIB_DESC(1, AR8216_STATS_TXLATECOL, "TxLateCol"),
156};
157
158static const struct ar8xxx_mib_desc ar8236_mibs[] = {
159    MIB_DESC(1, AR8236_STATS_RXBROAD, "RxBroad"),
160    MIB_DESC(1, AR8236_STATS_RXPAUSE, "RxPause"),
161    MIB_DESC(1, AR8236_STATS_RXMULTI, "RxMulti"),
162    MIB_DESC(1, AR8236_STATS_RXFCSERR, "RxFcsErr"),
163    MIB_DESC(1, AR8236_STATS_RXALIGNERR, "RxAlignErr"),
164    MIB_DESC(1, AR8236_STATS_RXRUNT, "RxRunt"),
165    MIB_DESC(1, AR8236_STATS_RXFRAGMENT, "RxFragment"),
166    MIB_DESC(1, AR8236_STATS_RX64BYTE, "Rx64Byte"),
167    MIB_DESC(1, AR8236_STATS_RX128BYTE, "Rx128Byte"),
168    MIB_DESC(1, AR8236_STATS_RX256BYTE, "Rx256Byte"),
169    MIB_DESC(1, AR8236_STATS_RX512BYTE, "Rx512Byte"),
170    MIB_DESC(1, AR8236_STATS_RX1024BYTE, "Rx1024Byte"),
171    MIB_DESC(1, AR8236_STATS_RX1518BYTE, "Rx1518Byte"),
172    MIB_DESC(1, AR8236_STATS_RXMAXBYTE, "RxMaxByte"),
173    MIB_DESC(1, AR8236_STATS_RXTOOLONG, "RxTooLong"),
174    MIB_DESC(2, AR8236_STATS_RXGOODBYTE, "RxGoodByte"),
175    MIB_DESC(2, AR8236_STATS_RXBADBYTE, "RxBadByte"),
176    MIB_DESC(1, AR8236_STATS_RXOVERFLOW, "RxOverFlow"),
177    MIB_DESC(1, AR8236_STATS_FILTERED, "Filtered"),
178    MIB_DESC(1, AR8236_STATS_TXBROAD, "TxBroad"),
179    MIB_DESC(1, AR8236_STATS_TXPAUSE, "TxPause"),
180    MIB_DESC(1, AR8236_STATS_TXMULTI, "TxMulti"),
181    MIB_DESC(1, AR8236_STATS_TXUNDERRUN, "TxUnderRun"),
182    MIB_DESC(1, AR8236_STATS_TX64BYTE, "Tx64Byte"),
183    MIB_DESC(1, AR8236_STATS_TX128BYTE, "Tx128Byte"),
184    MIB_DESC(1, AR8236_STATS_TX256BYTE, "Tx256Byte"),
185    MIB_DESC(1, AR8236_STATS_TX512BYTE, "Tx512Byte"),
186    MIB_DESC(1, AR8236_STATS_TX1024BYTE, "Tx1024Byte"),
187    MIB_DESC(1, AR8236_STATS_TX1518BYTE, "Tx1518Byte"),
188    MIB_DESC(1, AR8236_STATS_TXMAXBYTE, "TxMaxByte"),
189    MIB_DESC(1, AR8236_STATS_TXOVERSIZE, "TxOverSize"),
190    MIB_DESC(2, AR8236_STATS_TXBYTE, "TxByte"),
191    MIB_DESC(1, AR8236_STATS_TXCOLLISION, "TxCollision"),
192    MIB_DESC(1, AR8236_STATS_TXABORTCOL, "TxAbortCol"),
193    MIB_DESC(1, AR8236_STATS_TXMULTICOL, "TxMultiCol"),
194    MIB_DESC(1, AR8236_STATS_TXSINGLECOL, "TxSingleCol"),
195    MIB_DESC(1, AR8236_STATS_TXEXCDEFER, "TxExcDefer"),
196    MIB_DESC(1, AR8236_STATS_TXDEFER, "TxDefer"),
197    MIB_DESC(1, AR8236_STATS_TXLATECOL, "TxLateCol"),
198};
199
200#define to_ar8216(_dev) container_of(_dev, struct ar8216_priv, dev)
201
202static inline bool ar8xxx_has_gige(struct ar8216_priv *priv)
203{
204    return priv->chip->caps & AR8XXX_CAP_GIGE;
205}
206
207static inline bool ar8xxx_has_mib_counters(struct ar8216_priv *priv)
208{
209    return priv->chip->caps & AR8XXX_CAP_MIB_COUNTERS;
210}
211
212static inline bool chip_is_ar8216(struct ar8216_priv *priv)
213{
214    return priv->chip_ver == AR8XXX_VER_AR8216;
215}
216
217static inline bool chip_is_ar8236(struct ar8216_priv *priv)
218{
219    return priv->chip_ver == AR8XXX_VER_AR8236;
220}
221
222static inline bool chip_is_ar8316(struct ar8216_priv *priv)
223{
224    return priv->chip_ver == AR8XXX_VER_AR8316;
225}
226
227static inline bool chip_is_ar8327(struct ar8216_priv *priv)
228{
229    return priv->chip_ver == AR8XXX_VER_AR8327;
230}
231
232static inline void
233split_addr(u32 regaddr, u16 *r1, u16 *r2, u16 *page)
234{
235    regaddr >>= 1;
236    *r1 = regaddr & 0x1e;
237
238    regaddr >>= 5;
239    *r2 = regaddr & 0x7;
240
241    regaddr >>= 3;
242    *page = regaddr & 0x1ff;
243}
244
245static u32
246ar8216_mii_read(struct ar8216_priv *priv, int reg)
247{
248    struct phy_device *phy = priv->phy;
249    struct mii_bus *bus = phy->bus;
250    u16 r1, r2, page;
251    u16 lo, hi;
252
253    split_addr((u32) reg, &r1, &r2, &page);
254
255    mutex_lock(&bus->mdio_lock);
256
257    bus->write(bus, 0x18, 0, page);
258    usleep_range(1000, 2000); /* wait for the page switch to propagate */
259    lo = bus->read(bus, 0x10 | r2, r1);
260    hi = bus->read(bus, 0x10 | r2, r1 + 1);
261
262    mutex_unlock(&bus->mdio_lock);
263
264    return (hi << 16) | lo;
265}
266
267static void
268ar8216_mii_write(struct ar8216_priv *priv, int reg, u32 val)
269{
270    struct phy_device *phy = priv->phy;
271    struct mii_bus *bus = phy->bus;
272    u16 r1, r2, r3;
273    u16 lo, hi;
274
275    split_addr((u32) reg, &r1, &r2, &r3);
276    lo = val & 0xffff;
277    hi = (u16) (val >> 16);
278
279    mutex_lock(&bus->mdio_lock);
280
281    bus->write(bus, 0x18, 0, r3);
282    usleep_range(1000, 2000); /* wait for the page switch to propagate */
283    if (priv->mii_lo_first) {
284        bus->write(bus, 0x10 | r2, r1, lo);
285        bus->write(bus, 0x10 | r2, r1 + 1, hi);
286    } else {
287        bus->write(bus, 0x10 | r2, r1 + 1, hi);
288        bus->write(bus, 0x10 | r2, r1, lo);
289    }
290
291    mutex_unlock(&bus->mdio_lock);
292}
293
294static void
295ar8216_phy_dbg_write(struct ar8216_priv *priv, int phy_addr,
296             u16 dbg_addr, u16 dbg_data)
297{
298    struct mii_bus *bus = priv->phy->bus;
299
300    mutex_lock(&bus->mdio_lock);
301    bus->write(bus, phy_addr, MII_ATH_DBG_ADDR, dbg_addr);
302    bus->write(bus, phy_addr, MII_ATH_DBG_DATA, dbg_data);
303    mutex_unlock(&bus->mdio_lock);
304}
305
306static void
307ar8216_phy_mmd_write(struct ar8216_priv *priv, int phy_addr, u16 addr, u16 data)
308{
309    struct mii_bus *bus = priv->phy->bus;
310
311    mutex_lock(&bus->mdio_lock);
312    bus->write(bus, phy_addr, MII_ATH_MMD_ADDR, addr);
313    bus->write(bus, phy_addr, MII_ATH_MMD_DATA, data);
314    mutex_unlock(&bus->mdio_lock);
315}
316
317static u32
318ar8216_rmw(struct ar8216_priv *priv, int reg, u32 mask, u32 val)
319{
320    u32 v;
321
322    lockdep_assert_held(&priv->reg_mutex);
323
324    v = priv->read(priv, reg);
325    v &= ~mask;
326    v |= val;
327    priv->write(priv, reg, v);
328
329    return v;
330}
331
332static inline void
333ar8216_reg_set(struct ar8216_priv *priv, int reg, u32 val)
334{
335    u32 v;
336
337    lockdep_assert_held(&priv->reg_mutex);
338
339    v = priv->read(priv, reg);
340    v |= val;
341    priv->write(priv, reg, v);
342}
343
344static int
345ar8216_reg_wait(struct ar8216_priv *priv, u32 reg, u32 mask, u32 val,
346        unsigned timeout)
347{
348    int i;
349
350    for (i = 0; i < timeout; i++) {
351        u32 t;
352
353        t = priv->read(priv, reg);
354        if ((t & mask) == val)
355            return 0;
356
357        usleep_range(1000, 2000);
358    }
359
360    return -ETIMEDOUT;
361}
362
363static int
364ar8216_mib_op(struct ar8216_priv *priv, u32 op)
365{
366    unsigned mib_func;
367    int ret;
368
369    lockdep_assert_held(&priv->mib_lock);
370
371    if (chip_is_ar8327(priv))
372        mib_func = AR8327_REG_MIB_FUNC;
373    else
374        mib_func = AR8216_REG_MIB_FUNC;
375
376    mutex_lock(&priv->reg_mutex);
377    /* Capture the hardware statistics for all ports */
378    ar8216_rmw(priv, mib_func, AR8216_MIB_FUNC, (op << AR8216_MIB_FUNC_S));
379    mutex_unlock(&priv->reg_mutex);
380
381    /* Wait for the capturing to complete. */
382    ret = ar8216_reg_wait(priv, mib_func, AR8216_MIB_BUSY, 0, 10);
383    if (ret)
384        goto out;
385
386    ret = 0;
387
388out:
389    return ret;
390}
391
392static int
393ar8216_mib_capture(struct ar8216_priv *priv)
394{
395    return ar8216_mib_op(priv, AR8216_MIB_FUNC_CAPTURE);
396}
397
398static int
399ar8216_mib_flush(struct ar8216_priv *priv)
400{
401    return ar8216_mib_op(priv, AR8216_MIB_FUNC_FLUSH);
402}
403
404static void
405ar8216_mib_fetch_port_stat(struct ar8216_priv *priv, int port, bool flush)
406{
407    unsigned int base;
408    u64 *mib_stats;
409    int i;
410
411    WARN_ON(port >= priv->dev.ports);
412
413    lockdep_assert_held(&priv->mib_lock);
414
415    if (chip_is_ar8327(priv))
416        base = AR8327_REG_PORT_STATS_BASE(port);
417    else if (chip_is_ar8236(priv) ||
418         chip_is_ar8316(priv))
419        base = AR8236_REG_PORT_STATS_BASE(port);
420    else
421        base = AR8216_REG_PORT_STATS_BASE(port);
422
423    mib_stats = &priv->mib_stats[port * priv->chip->num_mibs];
424    for (i = 0; i < priv->chip->num_mibs; i++) {
425        const struct ar8xxx_mib_desc *mib;
426        u64 t;
427
428        mib = &priv->chip->mib_decs[i];
429        t = priv->read(priv, base + mib->offset);
430        if (mib->size == 2) {
431            u64 hi;
432
433            hi = priv->read(priv, base + mib->offset + 4);
434            t |= hi << 32;
435        }
436
437        if (flush)
438            mib_stats[i] = 0;
439        else
440            mib_stats[i] += t;
441    }
442}
443
444static void
445ar8216_read_port_link(struct ar8216_priv *priv, int port,
446              struct switch_port_link *link)
447{
448    u32 status;
449    u32 speed;
450
451    memset(link, '\0', sizeof(*link));
452
453    status = priv->chip->read_port_status(priv, port);
454
455    link->aneg = !!(status & AR8216_PORT_STATUS_LINK_AUTO);
456    if (link->aneg) {
457        link->link = !!(status & AR8216_PORT_STATUS_LINK_UP);
458        if (!link->link)
459            return;
460    } else {
461        link->link = true;
462    }
463
464    link->duplex = !!(status & AR8216_PORT_STATUS_DUPLEX);
465    link->tx_flow = !!(status & AR8216_PORT_STATUS_TXFLOW);
466    link->rx_flow = !!(status & AR8216_PORT_STATUS_RXFLOW);
467
468    speed = (status & AR8216_PORT_STATUS_SPEED) >>
469         AR8216_PORT_STATUS_SPEED_S;
470
471    switch (speed) {
472    case AR8216_PORT_SPEED_10M:
473        link->speed = SWITCH_PORT_SPEED_10;
474        break;
475    case AR8216_PORT_SPEED_100M:
476        link->speed = SWITCH_PORT_SPEED_100;
477        break;
478    case AR8216_PORT_SPEED_1000M:
479        link->speed = SWITCH_PORT_SPEED_1000;
480        break;
481    default:
482        link->speed = SWITCH_PORT_SPEED_UNKNOWN;
483        break;
484    }
485}
486
487static struct sk_buff *
488ar8216_mangle_tx(struct net_device *dev, struct sk_buff *skb)
489{
490    struct ar8216_priv *priv = dev->phy_ptr;
491    unsigned char *buf;
492
493    if (unlikely(!priv))
494        goto error;
495
496    if (!priv->vlan)
497        goto send;
498
499    if (unlikely(skb_headroom(skb) < 2)) {
500        if (pskb_expand_head(skb, 2, 0, GFP_ATOMIC) < 0)
501            goto error;
502    }
503
504    buf = skb_push(skb, 2);
505    buf[0] = 0x10;
506    buf[1] = 0x80;
507
508send:
509    return skb;
510
511error:
512    dev_kfree_skb_any(skb);
513    return NULL;
514}
515
516static void
517ar8216_mangle_rx(struct net_device *dev, struct sk_buff *skb)
518{
519    struct ar8216_priv *priv;
520    unsigned char *buf;
521    int port, vlan;
522
523    priv = dev->phy_ptr;
524    if (!priv)
525        return;
526
527    /* don't strip the header if vlan mode is disabled */
528    if (!priv->vlan)
529        return;
530
531    /* strip header, get vlan id */
532    buf = skb->data;
533    skb_pull(skb, 2);
534
535    /* check for vlan header presence */
536    if ((buf[12 + 2] != 0x81) || (buf[13 + 2] != 0x00))
537        return;
538
539    port = buf[0] & 0xf;
540
541    /* no need to fix up packets coming from a tagged source */
542    if (priv->vlan_tagged & (1 << port))
543        return;
544
545    /* lookup port vid from local table, the switch passes an invalid vlan id */
546    vlan = priv->vlan_id[priv->pvid[port]];
547
548    buf[14 + 2] &= 0xf0;
549    buf[14 + 2] |= vlan >> 8;
550    buf[15 + 2] = vlan & 0xff;
551}
552
553static int
554ar8216_wait_bit(struct ar8216_priv *priv, int reg, u32 mask, u32 val)
555{
556    int timeout = 20;
557    u32 t = 0;
558
559    while (1) {
560        t = priv->read(priv, reg);
561        if ((t & mask) == val)
562            return 0;
563
564        if (timeout-- <= 0)
565            break;
566
567        udelay(10);
568    }
569
570    pr_err("ar8216: timeout on reg %08x: %08x & %08x != %08x\n",
571           (unsigned int) reg, t, mask, val);
572    return -ETIMEDOUT;
573}
574
575static void
576ar8216_vtu_op(struct ar8216_priv *priv, u32 op, u32 val)
577{
578    if (ar8216_wait_bit(priv, AR8216_REG_VTU, AR8216_VTU_ACTIVE, 0))
579        return;
580    if ((op & AR8216_VTU_OP) == AR8216_VTU_OP_LOAD) {
581        val &= AR8216_VTUDATA_MEMBER;
582        val |= AR8216_VTUDATA_VALID;
583        priv->write(priv, AR8216_REG_VTU_DATA, val);
584    }
585    op |= AR8216_VTU_ACTIVE;
586    priv->write(priv, AR8216_REG_VTU, op);
587}
588
589static void
590ar8216_vtu_flush(struct ar8216_priv *priv)
591{
592    ar8216_vtu_op(priv, AR8216_VTU_OP_FLUSH, 0);
593}
594
595static void
596ar8216_vtu_load_vlan(struct ar8216_priv *priv, u32 vid, u32 port_mask)
597{
598    u32 op;
599
600    op = AR8216_VTU_OP_LOAD | (vid << AR8216_VTU_VID_S);
601    ar8216_vtu_op(priv, op, port_mask);
602}
603
604static int
605ar8216_atu_flush(struct ar8216_priv *priv)
606{
607    int ret;
608
609    ret = ar8216_wait_bit(priv, AR8216_REG_ATU, AR8216_ATU_ACTIVE, 0);
610    if (!ret)
611        priv->write(priv, AR8216_REG_ATU, AR8216_ATU_OP_FLUSH);
612
613    return ret;
614}
615
616static u32
617ar8216_read_port_status(struct ar8216_priv *priv, int port)
618{
619    return priv->read(priv, AR8216_REG_PORT_STATUS(port));
620}
621
622static void
623ar8216_setup_port(struct ar8216_priv *priv, int port, u32 egress, u32 ingress,
624          u32 members, u32 pvid)
625{
626    u32 header;
627
628    if (chip_is_ar8216(priv) && priv->vlan && port == AR8216_PORT_CPU)
629        header = AR8216_PORT_CTRL_HEADER;
630    else
631        header = 0;
632
633    ar8216_rmw(priv, AR8216_REG_PORT_CTRL(port),
634           AR8216_PORT_CTRL_LEARN | AR8216_PORT_CTRL_VLAN_MODE |
635           AR8216_PORT_CTRL_SINGLE_VLAN | AR8216_PORT_CTRL_STATE |
636           AR8216_PORT_CTRL_HEADER | AR8216_PORT_CTRL_LEARN_LOCK,
637           AR8216_PORT_CTRL_LEARN | header |
638           (egress << AR8216_PORT_CTRL_VLAN_MODE_S) |
639           (AR8216_PORT_STATE_FORWARD << AR8216_PORT_CTRL_STATE_S));
640
641    ar8216_rmw(priv, AR8216_REG_PORT_VLAN(port),
642           AR8216_PORT_VLAN_DEST_PORTS | AR8216_PORT_VLAN_MODE |
643           AR8216_PORT_VLAN_DEFAULT_ID,
644           (members << AR8216_PORT_VLAN_DEST_PORTS_S) |
645           (ingress << AR8216_PORT_VLAN_MODE_S) |
646           (pvid << AR8216_PORT_VLAN_DEFAULT_ID_S));
647}
648
649static int
650ar8216_hw_init(struct ar8216_priv *priv)
651{
652    return 0;
653}
654
655static void
656ar8216_init_globals(struct ar8216_priv *priv)
657{
658    /* standard atheros magic */
659    priv->write(priv, 0x38, 0xc000050e);
660
661    ar8216_rmw(priv, AR8216_REG_GLOBAL_CTRL,
662           AR8216_GCTRL_MTU, 1518 + 8 + 2);
663}
664
665static void
666ar8216_init_port(struct ar8216_priv *priv, int port)
667{
668    /* Enable port learning and tx */
669    priv->write(priv, AR8216_REG_PORT_CTRL(port),
670        AR8216_PORT_CTRL_LEARN |
671        (4 << AR8216_PORT_CTRL_STATE_S));
672
673    priv->write(priv, AR8216_REG_PORT_VLAN(port), 0);
674
675    if (port == AR8216_PORT_CPU) {
676        priv->write(priv, AR8216_REG_PORT_STATUS(port),
677            AR8216_PORT_STATUS_LINK_UP |
678            (ar8xxx_has_gige(priv) ?
679                                AR8216_PORT_SPEED_1000M : AR8216_PORT_SPEED_100M) |
680            AR8216_PORT_STATUS_TXMAC |
681            AR8216_PORT_STATUS_RXMAC |
682            (chip_is_ar8316(priv) ? AR8216_PORT_STATUS_RXFLOW : 0) |
683            (chip_is_ar8316(priv) ? AR8216_PORT_STATUS_TXFLOW : 0) |
684            AR8216_PORT_STATUS_DUPLEX);
685    } else {
686        priv->write(priv, AR8216_REG_PORT_STATUS(port),
687            AR8216_PORT_STATUS_LINK_AUTO);
688    }
689}
690
691static const struct ar8xxx_chip ar8216_chip = {
692    .caps = AR8XXX_CAP_MIB_COUNTERS,
693
694    .hw_init = ar8216_hw_init,
695    .init_globals = ar8216_init_globals,
696    .init_port = ar8216_init_port,
697    .setup_port = ar8216_setup_port,
698    .read_port_status = ar8216_read_port_status,
699    .atu_flush = ar8216_atu_flush,
700    .vtu_flush = ar8216_vtu_flush,
701    .vtu_load_vlan = ar8216_vtu_load_vlan,
702
703    .num_mibs = ARRAY_SIZE(ar8216_mibs),
704    .mib_decs = ar8216_mibs,
705};
706
707static void
708ar8236_setup_port(struct ar8216_priv *priv, int port, u32 egress, u32 ingress,
709          u32 members, u32 pvid)
710{
711    ar8216_rmw(priv, AR8216_REG_PORT_CTRL(port),
712           AR8216_PORT_CTRL_LEARN | AR8216_PORT_CTRL_VLAN_MODE |
713           AR8216_PORT_CTRL_SINGLE_VLAN | AR8216_PORT_CTRL_STATE |
714           AR8216_PORT_CTRL_HEADER | AR8216_PORT_CTRL_LEARN_LOCK,
715           AR8216_PORT_CTRL_LEARN |
716           (egress << AR8216_PORT_CTRL_VLAN_MODE_S) |
717           (AR8216_PORT_STATE_FORWARD << AR8216_PORT_CTRL_STATE_S));
718
719    ar8216_rmw(priv, AR8236_REG_PORT_VLAN(port),
720           AR8236_PORT_VLAN_DEFAULT_ID,
721           (pvid << AR8236_PORT_VLAN_DEFAULT_ID_S));
722
723    ar8216_rmw(priv, AR8236_REG_PORT_VLAN2(port),
724           AR8236_PORT_VLAN2_VLAN_MODE |
725           AR8236_PORT_VLAN2_MEMBER,
726           (ingress << AR8236_PORT_VLAN2_VLAN_MODE_S) |
727           (members << AR8236_PORT_VLAN2_MEMBER_S));
728}
729
730static int
731ar8236_hw_init(struct ar8216_priv *priv)
732{
733    int i;
734    struct mii_bus *bus;
735
736    if (priv->initialized)
737        return 0;
738
739    /* Initialize the PHYs */
740    bus = priv->phy->bus;
741    for (i = 0; i < 5; i++) {
742        mdiobus_write(bus, i, MII_ADVERTISE,
743                  ADVERTISE_ALL | ADVERTISE_PAUSE_CAP |
744                  ADVERTISE_PAUSE_ASYM);
745        mdiobus_write(bus, i, MII_BMCR, BMCR_RESET | BMCR_ANENABLE);
746    }
747    msleep(1000);
748
749    priv->initialized = true;
750    return 0;
751}
752
753static void
754ar8236_init_globals(struct ar8216_priv *priv)
755{
756    /* enable jumbo frames */
757    ar8216_rmw(priv, AR8216_REG_GLOBAL_CTRL,
758           AR8316_GCTRL_MTU, 9018 + 8 + 2);
759
760    /* Enable MIB counters */
761    ar8216_rmw(priv, AR8216_REG_MIB_FUNC, AR8216_MIB_FUNC | AR8236_MIB_EN,
762           (AR8216_MIB_FUNC_NO_OP << AR8216_MIB_FUNC_S) |
763           AR8236_MIB_EN);
764}
765
766static const struct ar8xxx_chip ar8236_chip = {
767    .caps = AR8XXX_CAP_MIB_COUNTERS,
768    .hw_init = ar8236_hw_init,
769    .init_globals = ar8236_init_globals,
770    .init_port = ar8216_init_port,
771    .setup_port = ar8236_setup_port,
772    .read_port_status = ar8216_read_port_status,
773    .atu_flush = ar8216_atu_flush,
774    .vtu_flush = ar8216_vtu_flush,
775    .vtu_load_vlan = ar8216_vtu_load_vlan,
776
777    .num_mibs = ARRAY_SIZE(ar8236_mibs),
778    .mib_decs = ar8236_mibs,
779};
780
781static int
782ar8316_hw_init(struct ar8216_priv *priv)
783{
784    int i;
785    u32 val, newval;
786    struct mii_bus *bus;
787
788    val = priv->read(priv, 0x8);
789
790    if (priv->phy->interface == PHY_INTERFACE_MODE_RGMII) {
791        if (priv->port4_phy) {
792            /* value taken from Ubiquiti RouterStation Pro */
793            newval = 0x81461bea;
794            printk(KERN_INFO "ar8316: Using port 4 as PHY\n");
795        } else {
796            newval = 0x01261be2;
797            printk(KERN_INFO "ar8316: Using port 4 as switch port\n");
798        }
799    } else if (priv->phy->interface == PHY_INTERFACE_MODE_GMII) {
800        /* value taken from AVM Fritz!Box 7390 sources */
801        newval = 0x010e5b71;
802    } else {
803        /* no known value for phy interface */
804        printk(KERN_ERR "ar8316: unsupported mii mode: %d.\n",
805            priv->phy->interface);
806        return -EINVAL;
807    }
808
809    if (val == newval)
810        goto out;
811
812    priv->write(priv, 0x8, newval);
813
814    /* Initialize the ports */
815    bus = priv->phy->bus;
816    for (i = 0; i < 5; i++) {
817        if ((i == 4) && priv->port4_phy &&
818            priv->phy->interface == PHY_INTERFACE_MODE_RGMII) {
819            /* work around for phy4 rgmii mode */
820            ar8216_phy_dbg_write(priv, i, 0x12, 0x480c);
821            /* rx delay */
822            ar8216_phy_dbg_write(priv, i, 0x0, 0x824e);
823            /* tx delay */
824            ar8216_phy_dbg_write(priv, i, 0x5, 0x3d47);
825            msleep(1000);
826        }
827
828        /* initialize the port itself */
829        mdiobus_write(bus, i, MII_ADVERTISE,
830            ADVERTISE_ALL | ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
831        mdiobus_write(bus, i, MII_CTRL1000, ADVERTISE_1000FULL);
832        mdiobus_write(bus, i, MII_BMCR, BMCR_RESET | BMCR_ANENABLE);
833        msleep(1000);
834    }
835
836out:
837    priv->initialized = true;
838    return 0;
839}
840
841static void
842ar8316_init_globals(struct ar8216_priv *priv)
843{
844    /* standard atheros magic */
845    priv->write(priv, 0x38, 0xc000050e);
846
847    /* enable cpu port to receive multicast and broadcast frames */
848    priv->write(priv, AR8216_REG_FLOOD_MASK, 0x003f003f);
849
850    /* enable jumbo frames */
851    ar8216_rmw(priv, AR8216_REG_GLOBAL_CTRL,
852           AR8316_GCTRL_MTU, 9018 + 8 + 2);
853
854    /* Enable MIB counters */
855    ar8216_rmw(priv, AR8216_REG_MIB_FUNC, AR8216_MIB_FUNC | AR8236_MIB_EN,
856           (AR8216_MIB_FUNC_NO_OP << AR8216_MIB_FUNC_S) |
857           AR8236_MIB_EN);
858}
859
860static const struct ar8xxx_chip ar8316_chip = {
861    .caps = AR8XXX_CAP_GIGE | AR8XXX_CAP_MIB_COUNTERS,
862    .hw_init = ar8316_hw_init,
863    .init_globals = ar8316_init_globals,
864    .init_port = ar8216_init_port,
865    .setup_port = ar8216_setup_port,
866    .read_port_status = ar8216_read_port_status,
867    .atu_flush = ar8216_atu_flush,
868    .vtu_flush = ar8216_vtu_flush,
869    .vtu_load_vlan = ar8216_vtu_load_vlan,
870
871    .num_mibs = ARRAY_SIZE(ar8236_mibs),
872    .mib_decs = ar8236_mibs,
873};
874
875static u32
876ar8327_get_pad_cfg(struct ar8327_pad_cfg *cfg)
877{
878    u32 t;
879
880    if (!cfg)
881        return 0;
882
883    t = 0;
884    switch (cfg->mode) {
885    case AR8327_PAD_NC:
886        break;
887
888    case AR8327_PAD_MAC2MAC_MII:
889        t = AR8327_PAD_MAC_MII_EN;
890        if (cfg->rxclk_sel)
891            t |= AR8327_PAD_MAC_MII_RXCLK_SEL;
892        if (cfg->txclk_sel)
893            t |= AR8327_PAD_MAC_MII_TXCLK_SEL;
894        break;
895
896    case AR8327_PAD_MAC2MAC_GMII:
897        t = AR8327_PAD_MAC_GMII_EN;
898        if (cfg->rxclk_sel)
899            t |= AR8327_PAD_MAC_GMII_RXCLK_SEL;
900        if (cfg->txclk_sel)
901            t |= AR8327_PAD_MAC_GMII_TXCLK_SEL;
902        break;
903
904    case AR8327_PAD_MAC_SGMII:
905        t = AR8327_PAD_SGMII_EN;
906
907        /*
908         * WAR for the QUalcomm Atheros AP136 board.
909         * It seems that RGMII TX/RX delay settings needs to be
910         * applied for SGMII mode as well, The ethernet is not
911         * reliable without this.
912         */
913        t |= cfg->txclk_delay_sel << AR8327_PAD_RGMII_TXCLK_DELAY_SEL_S;
914        t |= cfg->rxclk_delay_sel << AR8327_PAD_RGMII_RXCLK_DELAY_SEL_S;
915        if (cfg->rxclk_delay_en)
916            t |= AR8327_PAD_RGMII_RXCLK_DELAY_EN;
917        if (cfg->txclk_delay_en)
918            t |= AR8327_PAD_RGMII_TXCLK_DELAY_EN;
919
920        if (cfg->sgmii_delay_en)
921            t |= AR8327_PAD_SGMII_DELAY_EN;
922
923        break;
924
925    case AR8327_PAD_MAC2PHY_MII:
926        t = AR8327_PAD_PHY_MII_EN;
927        if (cfg->rxclk_sel)
928            t |= AR8327_PAD_PHY_MII_RXCLK_SEL;
929        if (cfg->txclk_sel)
930            t |= AR8327_PAD_PHY_MII_TXCLK_SEL;
931        break;
932
933    case AR8327_PAD_MAC2PHY_GMII:
934        t = AR8327_PAD_PHY_GMII_EN;
935        if (cfg->pipe_rxclk_sel)
936            t |= AR8327_PAD_PHY_GMII_PIPE_RXCLK_SEL;
937        if (cfg->rxclk_sel)
938            t |= AR8327_PAD_PHY_GMII_RXCLK_SEL;
939        if (cfg->txclk_sel)
940            t |= AR8327_PAD_PHY_GMII_TXCLK_SEL;
941        break;
942
943    case AR8327_PAD_MAC_RGMII:
944        t = AR8327_PAD_RGMII_EN;
945        t |= cfg->txclk_delay_sel << AR8327_PAD_RGMII_TXCLK_DELAY_SEL_S;
946        t |= cfg->rxclk_delay_sel << AR8327_PAD_RGMII_RXCLK_DELAY_SEL_S;
947        if (cfg->rxclk_delay_en)
948            t |= AR8327_PAD_RGMII_RXCLK_DELAY_EN;
949        if (cfg->txclk_delay_en)
950            t |= AR8327_PAD_RGMII_TXCLK_DELAY_EN;
951        break;
952
953    case AR8327_PAD_PHY_GMII:
954        t = AR8327_PAD_PHYX_GMII_EN;
955        break;
956
957    case AR8327_PAD_PHY_RGMII:
958        t = AR8327_PAD_PHYX_RGMII_EN;
959        break;
960
961    case AR8327_PAD_PHY_MII:
962        t = AR8327_PAD_PHYX_MII_EN;
963        break;
964    }
965
966    return t;
967}
968
969static void
970ar8327_phy_fixup(struct ar8216_priv *priv, int phy)
971{
972    switch (priv->chip_rev) {
973    case 1:
974        /* For 100M waveform */
975        ar8216_phy_dbg_write(priv, phy, 0, 0x02ea);
976        /* Turn on Gigabit clock */
977        ar8216_phy_dbg_write(priv, phy, 0x3d, 0x68a0);
978        break;
979
980    case 2:
981        ar8216_phy_mmd_write(priv, phy, 0x7, 0x3c);
982        ar8216_phy_mmd_write(priv, phy, 0x4007, 0x0);
983        /* fallthrough */
984    case 4:
985        ar8216_phy_mmd_write(priv, phy, 0x3, 0x800d);
986        ar8216_phy_mmd_write(priv, phy, 0x4003, 0x803f);
987
988        ar8216_phy_dbg_write(priv, phy, 0x3d, 0x6860);
989        ar8216_phy_dbg_write(priv, phy, 0x5, 0x2c46);
990        ar8216_phy_dbg_write(priv, phy, 0x3c, 0x6000);
991        break;
992    }
993}
994
995static int
996ar8327_hw_init(struct ar8216_priv *priv)
997{
998    struct ar8327_platform_data *pdata;
999    struct ar8327_led_cfg *led_cfg;
1000    struct mii_bus *bus;
1001    u32 pos, new_pos;
1002    u32 t;
1003    int i;
1004
1005    pdata = priv->phy->dev.platform_data;
1006    if (!pdata)
1007        return -EINVAL;
1008
1009    t = ar8327_get_pad_cfg(pdata->pad0_cfg);
1010    priv->write(priv, AR8327_REG_PAD0_MODE, t);
1011    t = ar8327_get_pad_cfg(pdata->pad5_cfg);
1012    priv->write(priv, AR8327_REG_PAD5_MODE, t);
1013    t = ar8327_get_pad_cfg(pdata->pad6_cfg);
1014    priv->write(priv, AR8327_REG_PAD6_MODE, t);
1015
1016    pos = priv->read(priv, AR8327_REG_POWER_ON_STRIP);
1017    new_pos = pos;
1018
1019    led_cfg = pdata->led_cfg;
1020    if (led_cfg) {
1021        if (led_cfg->open_drain)
1022            new_pos |= AR8327_POWER_ON_STRIP_LED_OPEN_EN;
1023        else
1024            new_pos &= ~AR8327_POWER_ON_STRIP_LED_OPEN_EN;
1025
1026        priv->write(priv, AR8327_REG_LED_CTRL0, led_cfg->led_ctrl0);
1027        priv->write(priv, AR8327_REG_LED_CTRL1, led_cfg->led_ctrl1);
1028        priv->write(priv, AR8327_REG_LED_CTRL2, led_cfg->led_ctrl2);
1029        priv->write(priv, AR8327_REG_LED_CTRL3, led_cfg->led_ctrl3);
1030    }
1031
1032    if (new_pos != pos) {
1033        new_pos |= AR8327_POWER_ON_STRIP_POWER_ON_SEL;
1034        priv->write(priv, AR8327_REG_POWER_ON_STRIP, new_pos);
1035    }
1036
1037    bus = priv->phy->bus;
1038    for (i = 0; i < AR8327_NUM_PHYS; i++) {
1039        ar8327_phy_fixup(priv, i);
1040
1041        /* start aneg on the PHY */
1042        mdiobus_write(bus, i, MII_ADVERTISE, ADVERTISE_ALL |
1043                             ADVERTISE_PAUSE_CAP |
1044                             ADVERTISE_PAUSE_ASYM);
1045        mdiobus_write(bus, i, MII_CTRL1000, ADVERTISE_1000FULL);
1046        mdiobus_write(bus, i, MII_BMCR, BMCR_RESET | BMCR_ANENABLE);
1047    }
1048
1049    msleep(1000);
1050
1051    return 0;
1052}
1053
1054static void
1055ar8327_init_globals(struct ar8216_priv *priv)
1056{
1057    u32 t;
1058
1059    /* enable CPU port and disable mirror port */
1060    t = AR8327_FWD_CTRL0_CPU_PORT_EN |
1061        AR8327_FWD_CTRL0_MIRROR_PORT;
1062    priv->write(priv, AR8327_REG_FWD_CTRL0, t);
1063
1064    /* forward multicast and broadcast frames to CPU */
1065    t = (AR8327_PORTS_ALL << AR8327_FWD_CTRL1_UC_FLOOD_S) |
1066        (AR8327_PORTS_ALL << AR8327_FWD_CTRL1_MC_FLOOD_S) |
1067        (AR8327_PORTS_ALL << AR8327_FWD_CTRL1_BC_FLOOD_S);
1068    priv->write(priv, AR8327_REG_FWD_CTRL1, t);
1069
1070    /* setup MTU */
1071    ar8216_rmw(priv, AR8327_REG_MAX_FRAME_SIZE,
1072           AR8327_MAX_FRAME_SIZE_MTU, 1518 + 8 + 2);
1073
1074    /* Enable MIB counters */
1075    ar8216_reg_set(priv, AR8327_REG_MODULE_EN,
1076               AR8327_MODULE_EN_MIB);
1077}
1078
1079static void
1080ar8327_config_port(struct ar8216_priv *priv, unsigned int port,
1081            struct ar8327_port_cfg *cfg)
1082{
1083    u32 t;
1084
1085    if (!cfg || !cfg->force_link) {
1086        priv->write(priv, AR8327_REG_PORT_STATUS(port),
1087                AR8216_PORT_STATUS_LINK_AUTO);
1088        return;
1089    }
1090
1091    t = AR8216_PORT_STATUS_TXMAC | AR8216_PORT_STATUS_RXMAC;
1092    t |= cfg->duplex ? AR8216_PORT_STATUS_DUPLEX : 0;
1093    t |= cfg->rxpause ? AR8216_PORT_STATUS_RXFLOW : 0;
1094    t |= cfg->txpause ? AR8216_PORT_STATUS_TXFLOW : 0;
1095
1096    switch (cfg->speed) {
1097    case AR8327_PORT_SPEED_10:
1098        t |= AR8216_PORT_SPEED_10M;
1099        break;
1100    case AR8327_PORT_SPEED_100:
1101        t |= AR8216_PORT_SPEED_100M;
1102        break;
1103    case AR8327_PORT_SPEED_1000:
1104        t |= AR8216_PORT_SPEED_1000M;
1105        break;
1106    }
1107
1108    priv->write(priv, AR8327_REG_PORT_STATUS(port), t);
1109}
1110
1111static void
1112ar8327_init_port(struct ar8216_priv *priv, int port)
1113{
1114    struct ar8327_platform_data *pdata;
1115    struct ar8327_port_cfg *cfg;
1116    u32 t;
1117
1118    pdata = priv->phy->dev.platform_data;
1119
1120    if (pdata && port == AR8216_PORT_CPU)
1121        cfg = &pdata->port0_cfg;
1122    else if (pdata && port == 6)
1123        cfg = &pdata->port6_cfg;
1124    else
1125        cfg = NULL;
1126
1127    ar8327_config_port(priv, port, cfg);
1128    
1129    priv->write(priv, AR8327_REG_PORT_HEADER(port), 0);
1130
1131    t = 1 << AR8327_PORT_VLAN0_DEF_SVID_S;
1132    t |= 1 << AR8327_PORT_VLAN0_DEF_CVID_S;
1133    priv->write(priv, AR8327_REG_PORT_VLAN0(port), t);
1134
1135    t = AR8327_PORT_VLAN1_OUT_MODE_UNTOUCH << AR8327_PORT_VLAN1_OUT_MODE_S;
1136    priv->write(priv, AR8327_REG_PORT_VLAN1(port), t);
1137
1138    t = AR8327_PORT_LOOKUP_LEARN;
1139    t |= AR8216_PORT_STATE_FORWARD << AR8327_PORT_LOOKUP_STATE_S;
1140    priv->write(priv, AR8327_REG_PORT_LOOKUP(port), t);
1141}
1142
1143static u32
1144ar8327_read_port_status(struct ar8216_priv *priv, int port)
1145{
1146    return priv->read(priv, AR8327_REG_PORT_STATUS(port));
1147}
1148
1149static int
1150ar8327_atu_flush(struct ar8216_priv *priv)
1151{
1152    int ret;
1153
1154    ret = ar8216_wait_bit(priv, AR8327_REG_ATU_FUNC,
1155                  AR8327_ATU_FUNC_BUSY, 0);
1156    if (!ret)
1157        priv->write(priv, AR8327_REG_ATU_FUNC,
1158                AR8327_ATU_FUNC_OP_FLUSH);
1159
1160    return ret;
1161}
1162
1163static void
1164ar8327_vtu_op(struct ar8216_priv *priv, u32 op, u32 val)
1165{
1166    if (ar8216_wait_bit(priv, AR8327_REG_VTU_FUNC1,
1167                AR8327_VTU_FUNC1_BUSY, 0))
1168        return;
1169
1170    if ((op & AR8327_VTU_FUNC1_OP) == AR8327_VTU_FUNC1_OP_LOAD)
1171        priv->write(priv, AR8327_REG_VTU_FUNC0, val);
1172
1173    op |= AR8327_VTU_FUNC1_BUSY;
1174    priv->write(priv, AR8327_REG_VTU_FUNC1, op);
1175}
1176
1177static void
1178ar8327_vtu_flush(struct ar8216_priv *priv)
1179{
1180    ar8327_vtu_op(priv, AR8327_VTU_FUNC1_OP_FLUSH, 0);
1181}
1182
1183static void
1184ar8327_vtu_load_vlan(struct ar8216_priv *priv, u32 vid, u32 port_mask)
1185{
1186    u32 op;
1187    u32 val;
1188    int i;
1189
1190    op = AR8327_VTU_FUNC1_OP_LOAD | (vid << AR8327_VTU_FUNC1_VID_S);
1191    val = AR8327_VTU_FUNC0_VALID | AR8327_VTU_FUNC0_IVL;
1192    for (i = 0; i < AR8327_NUM_PORTS; i++) {
1193        u32 mode;
1194
1195        if ((port_mask & BIT(i)) == 0)
1196            mode = AR8327_VTU_FUNC0_EG_MODE_NOT;
1197        else if (priv->vlan == 0)
1198            mode = AR8327_VTU_FUNC0_EG_MODE_KEEP;
1199        else if (priv->vlan_tagged & BIT(i))
1200            mode = AR8327_VTU_FUNC0_EG_MODE_TAG;
1201        else
1202            mode = AR8327_VTU_FUNC0_EG_MODE_UNTAG;
1203
1204        val |= mode << AR8327_VTU_FUNC0_EG_MODE_S(i);
1205    }
1206    ar8327_vtu_op(priv, op, val);
1207}
1208
1209static void
1210ar8327_setup_port(struct ar8216_priv *priv, int port, u32 egress, u32 ingress,
1211          u32 members, u32 pvid)
1212{
1213    u32 t;
1214    u32 mode;
1215
1216    t = pvid << AR8327_PORT_VLAN0_DEF_SVID_S;
1217    t |= pvid << AR8327_PORT_VLAN0_DEF_CVID_S;
1218    priv->write(priv, AR8327_REG_PORT_VLAN0(port), t);
1219
1220    mode = AR8327_PORT_VLAN1_OUT_MODE_UNMOD;
1221    switch (egress) {
1222    case AR8216_OUT_KEEP:
1223        mode = AR8327_PORT_VLAN1_OUT_MODE_UNTOUCH;
1224        break;
1225    case AR8216_OUT_STRIP_VLAN:
1226        mode = AR8327_PORT_VLAN1_OUT_MODE_UNTAG;
1227        break;
1228    case AR8216_OUT_ADD_VLAN:
1229        mode = AR8327_PORT_VLAN1_OUT_MODE_TAG;
1230        break;
1231    }
1232
1233    t = AR8327_PORT_VLAN1_PORT_VLAN_PROP;
1234    t |= mode << AR8327_PORT_VLAN1_OUT_MODE_S;
1235    priv->write(priv, AR8327_REG_PORT_VLAN1(port), t);
1236
1237    t = members;
1238    t |= AR8327_PORT_LOOKUP_LEARN;
1239    t |= ingress << AR8327_PORT_LOOKUP_IN_MODE_S;
1240    t |= AR8216_PORT_STATE_FORWARD << AR8327_PORT_LOOKUP_STATE_S;
1241    priv->write(priv, AR8327_REG_PORT_LOOKUP(port), t);
1242}
1243
1244static const struct ar8xxx_chip ar8327_chip = {
1245    .caps = AR8XXX_CAP_GIGE | AR8XXX_CAP_MIB_COUNTERS,
1246    .hw_init = ar8327_hw_init,
1247    .init_globals = ar8327_init_globals,
1248    .init_port = ar8327_init_port,
1249    .setup_port = ar8327_setup_port,
1250    .read_port_status = ar8327_read_port_status,
1251    .atu_flush = ar8327_atu_flush,
1252    .vtu_flush = ar8327_vtu_flush,
1253    .vtu_load_vlan = ar8327_vtu_load_vlan,
1254
1255    .num_mibs = ARRAY_SIZE(ar8236_mibs),
1256    .mib_decs = ar8236_mibs,
1257};
1258
1259static int
1260ar8216_sw_set_vlan(struct switch_dev *dev, const struct switch_attr *attr,
1261           struct switch_val *val)
1262{
1263    struct ar8216_priv *priv = to_ar8216(dev);
1264    priv->vlan = !!val->value.i;
1265    return 0;
1266}
1267
1268static int
1269ar8216_sw_get_vlan(struct switch_dev *dev, const struct switch_attr *attr,
1270           struct switch_val *val)
1271{
1272    struct ar8216_priv *priv = to_ar8216(dev);
1273    val->value.i = priv->vlan;
1274    return 0;
1275}
1276
1277
1278static int
1279ar8216_sw_set_pvid(struct switch_dev *dev, int port, int vlan)
1280{
1281    struct ar8216_priv *priv = to_ar8216(dev);
1282
1283    /* make sure no invalid PVIDs get set */
1284
1285    if (vlan >= dev->vlans)
1286        return -EINVAL;
1287
1288    priv->pvid[port] = vlan;
1289    return 0;
1290}
1291
1292static int
1293ar8216_sw_get_pvid(struct switch_dev *dev, int port, int *vlan)
1294{
1295    struct ar8216_priv *priv = to_ar8216(dev);
1296    *vlan = priv->pvid[port];
1297    return 0;
1298}
1299
1300static int
1301ar8216_sw_set_vid(struct switch_dev *dev, const struct switch_attr *attr,
1302          struct switch_val *val)
1303{
1304    struct ar8216_priv *priv = to_ar8216(dev);
1305    priv->vlan_id[val->port_vlan] = val->value.i;
1306    return 0;
1307}
1308
1309static int
1310ar8216_sw_get_vid(struct switch_dev *dev, const struct switch_attr *attr,
1311          struct switch_val *val)
1312{
1313    struct ar8216_priv *priv = to_ar8216(dev);
1314    val->value.i = priv->vlan_id[val->port_vlan];
1315    return 0;
1316}
1317
1318static int
1319ar8216_sw_get_port_link(struct switch_dev *dev, int port,
1320            struct switch_port_link *link)
1321{
1322    struct ar8216_priv *priv = to_ar8216(dev);
1323
1324    ar8216_read_port_link(priv, port, link);
1325    return 0;
1326}
1327
1328static int
1329ar8216_sw_get_ports(struct switch_dev *dev, struct switch_val *val)
1330{
1331    struct ar8216_priv *priv = to_ar8216(dev);
1332    u8 ports = priv->vlan_table[val->port_vlan];
1333    int i;
1334
1335    val->len = 0;
1336    for (i = 0; i < dev->ports; i++) {
1337        struct switch_port *p;
1338
1339        if (!(ports & (1 << i)))
1340            continue;
1341
1342        p = &val->value.ports[val->len++];
1343        p->id = i;
1344        if (priv->vlan_tagged & (1 << i))
1345            p->flags = (1 << SWITCH_PORT_FLAG_TAGGED);
1346        else
1347            p->flags = 0;
1348    }
1349    return 0;
1350}
1351
1352static int
1353ar8216_sw_set_ports(struct switch_dev *dev, struct switch_val *val)
1354{
1355    struct ar8216_priv *priv = to_ar8216(dev);
1356    u8 *vt = &priv->vlan_table[val->port_vlan];
1357    int i, j;
1358
1359    *vt = 0;
1360    for (i = 0; i < val->len; i++) {
1361        struct switch_port *p = &val->value.ports[i];
1362
1363        if (p->flags & (1 << SWITCH_PORT_FLAG_TAGGED)) {
1364            priv->vlan_tagged |= (1 << p->id);
1365        } else {
1366            priv->vlan_tagged &= ~(1 << p->id);
1367            priv->pvid[p->id] = val->port_vlan;
1368
1369            /* make sure that an untagged port does not
1370             * appear in other vlans */
1371            for (j = 0; j < AR8X16_MAX_VLANS; j++) {
1372                if (j == val->port_vlan)
1373                    continue;
1374                priv->vlan_table[j] &= ~(1 << p->id);
1375            }
1376        }
1377
1378        *vt |= 1 << p->id;
1379    }
1380    return 0;
1381}
1382
1383static int
1384ar8216_sw_hw_apply(struct switch_dev *dev)
1385{
1386    struct ar8216_priv *priv = to_ar8216(dev);
1387    u8 portmask[AR8X16_MAX_PORTS];
1388    int i, j;
1389
1390    mutex_lock(&priv->reg_mutex);
1391    /* flush all vlan translation unit entries */
1392    priv->chip->vtu_flush(priv);
1393
1394    memset(portmask, 0, sizeof(portmask));
1395    if (!priv->init) {
1396        /* calculate the port destination masks and load vlans
1397         * into the vlan translation unit */
1398        for (j = 0; j < AR8X16_MAX_VLANS; j++) {
1399            u8 vp = priv->vlan_table[j];
1400
1401            if (!vp)
1402                continue;
1403
1404            for (i = 0; i < dev->ports; i++) {
1405                u8 mask = (1 << i);
1406                if (vp & mask)
1407                    portmask[i] |= vp & ~mask;
1408            }
1409
1410            priv->chip->vtu_load_vlan(priv, priv->vlan_id[j],
1411                         priv->vlan_table[j]);
1412        }
1413    } else {
1414        /* vlan disabled:
1415         * isolate all ports, but connect them to the cpu port */
1416        for (i = 0; i < dev->ports; i++) {
1417            if (i == AR8216_PORT_CPU)
1418                continue;
1419
1420            portmask[i] = 1 << AR8216_PORT_CPU;
1421            portmask[AR8216_PORT_CPU] |= (1 << i);
1422        }
1423    }
1424
1425    /* update the port destination mask registers and tag settings */
1426    for (i = 0; i < dev->ports; i++) {
1427        int egress, ingress;
1428        int pvid;
1429
1430        if (priv->vlan) {
1431            pvid = priv->vlan_id[priv->pvid[i]];
1432            if (priv->vlan_tagged & (1 << i))
1433                egress = AR8216_OUT_ADD_VLAN;
1434            else
1435                egress = AR8216_OUT_STRIP_VLAN;
1436            ingress = AR8216_IN_SECURE;
1437        } else {
1438            pvid = i;
1439            egress = AR8216_OUT_KEEP;
1440            ingress = AR8216_IN_PORT_ONLY;
1441        }
1442
1443        priv->chip->setup_port(priv, i, egress, ingress, portmask[i],
1444                       pvid);
1445    }
1446    mutex_unlock(&priv->reg_mutex);
1447    return 0;
1448}
1449
1450static int
1451ar8216_sw_reset_switch(struct switch_dev *dev)
1452{
1453    struct ar8216_priv *priv = to_ar8216(dev);
1454    int i;
1455
1456    mutex_lock(&priv->reg_mutex);
1457    memset(&priv->vlan, 0, sizeof(struct ar8216_priv) -
1458        offsetof(struct ar8216_priv, vlan));
1459
1460    for (i = 0; i < AR8X16_MAX_VLANS; i++)
1461        priv->vlan_id[i] = i;
1462
1463    /* Configure all ports */
1464    for (i = 0; i < dev->ports; i++)
1465        priv->chip->init_port(priv, i);
1466
1467    priv->chip->init_globals(priv);
1468    mutex_unlock(&priv->reg_mutex);
1469
1470    return ar8216_sw_hw_apply(dev);
1471}
1472
1473static int
1474ar8216_sw_set_reset_mibs(struct switch_dev *dev,
1475             const struct switch_attr *attr,
1476             struct switch_val *val)
1477{
1478    struct ar8216_priv *priv = to_ar8216(dev);
1479    unsigned int len;
1480    int ret;
1481
1482    if (!ar8xxx_has_mib_counters(priv))
1483        return -EOPNOTSUPP;
1484
1485    mutex_lock(&priv->mib_lock);
1486
1487    len = priv->dev.ports * priv->chip->num_mibs *
1488          sizeof(*priv->mib_stats);
1489    memset(priv->mib_stats, '\0', len);
1490    ret = ar8216_mib_flush(priv);
1491    if (ret)
1492        goto unlock;
1493
1494    ret = 0;
1495
1496unlock:
1497    mutex_unlock(&priv->mib_lock);
1498    return ret;
1499}
1500
1501static int
1502ar8216_sw_set_port_reset_mib(struct switch_dev *dev,
1503                 const struct switch_attr *attr,
1504                 struct switch_val *val)
1505{
1506    struct ar8216_priv *priv = to_ar8216(dev);
1507    int port;
1508    int ret;
1509
1510    if (!ar8xxx_has_mib_counters(priv))
1511        return -EOPNOTSUPP;
1512
1513    port = val->port_vlan;
1514    if (port >= dev->ports)
1515        return -EINVAL;
1516
1517    mutex_lock(&priv->mib_lock);
1518    ret = ar8216_mib_capture(priv);
1519    if (ret)
1520        goto unlock;
1521
1522    ar8216_mib_fetch_port_stat(priv, port, true);
1523
1524    ret = 0;
1525
1526unlock:
1527    mutex_unlock(&priv->mib_lock);
1528    return ret;
1529}
1530
1531static int
1532ar8216_sw_get_port_mib(struct switch_dev *dev,
1533               const struct switch_attr *attr,
1534               struct switch_val *val)
1535{
1536    struct ar8216_priv *priv = to_ar8216(dev);
1537    const struct ar8xxx_chip *chip = priv->chip;
1538    u64 *mib_stats;
1539    int port;
1540    int ret;
1541    char *buf = priv->buf;
1542    int i, len = 0;
1543
1544    if (!ar8xxx_has_mib_counters(priv))
1545        return -EOPNOTSUPP;
1546
1547    port = val->port_vlan;
1548    if (port >= dev->ports)
1549        return -EINVAL;
1550
1551    mutex_lock(&priv->mib_lock);
1552    ret = ar8216_mib_capture(priv);
1553    if (ret)
1554        goto unlock;
1555
1556    ar8216_mib_fetch_port_stat(priv, port, false);
1557
1558    len += snprintf(buf + len, sizeof(priv->buf) - len,
1559            "Port %d MIB counters\n",
1560            port);
1561
1562    mib_stats = &priv->mib_stats[port * chip->num_mibs];
1563    for (i = 0; i < chip->num_mibs; i++)
1564        len += snprintf(buf + len, sizeof(priv->buf) - len,
1565                "%-12s: %llu\n",
1566                chip->mib_decs[i].name,
1567                mib_stats[i]);
1568
1569    val->value.s = buf;
1570    val->len = len;
1571
1572    ret = 0;
1573
1574unlock:
1575    mutex_unlock(&priv->mib_lock);
1576    return ret;
1577}
1578
1579static struct switch_attr ar8216_globals[] = {
1580    {
1581        .type = SWITCH_TYPE_INT,
1582        .name = "enable_vlan",
1583        .description = "Enable VLAN mode",
1584        .set = ar8216_sw_set_vlan,
1585        .get = ar8216_sw_get_vlan,
1586        .max = 1
1587    },
1588    {
1589        .type = SWITCH_TYPE_NOVAL,
1590        .name = "reset_mibs",
1591        .description = "Reset all MIB counters",
1592        .set = ar8216_sw_set_reset_mibs,
1593    },
1594
1595};
1596
1597static struct switch_attr ar8216_port[] = {
1598    {
1599        .type = SWITCH_TYPE_NOVAL,
1600        .name = "reset_mib",
1601        .description = "Reset single port MIB counters",
1602        .set = ar8216_sw_set_port_reset_mib,
1603    },
1604    {
1605        .type = SWITCH_TYPE_STRING,
1606        .name = "mib",
1607        .description = "Get port's MIB counters",
1608        .set = NULL,
1609        .get = ar8216_sw_get_port_mib,
1610    },
1611};
1612
1613static struct switch_attr ar8216_vlan[] = {
1614    {
1615        .type = SWITCH_TYPE_INT,
1616        .name = "vid",
1617        .description = "VLAN ID (0-4094)",
1618        .set = ar8216_sw_set_vid,
1619        .get = ar8216_sw_get_vid,
1620        .max = 4094,
1621    },
1622};
1623
1624static const struct switch_dev_ops ar8216_sw_ops = {
1625    .attr_global = {
1626        .attr = ar8216_globals,
1627        .n_attr = ARRAY_SIZE(ar8216_globals),
1628    },
1629    .attr_port = {
1630        .attr = ar8216_port,
1631        .n_attr = ARRAY_SIZE(ar8216_port),
1632    },
1633    .attr_vlan = {
1634        .attr = ar8216_vlan,
1635        .n_attr = ARRAY_SIZE(ar8216_vlan),
1636    },
1637    .get_port_pvid = ar8216_sw_get_pvid,
1638    .set_port_pvid = ar8216_sw_set_pvid,
1639    .get_vlan_ports = ar8216_sw_get_ports,
1640    .set_vlan_ports = ar8216_sw_set_ports,
1641    .apply_config = ar8216_sw_hw_apply,
1642    .reset_switch = ar8216_sw_reset_switch,
1643    .get_port_link = ar8216_sw_get_port_link,
1644};
1645
1646static int
1647ar8216_id_chip(struct ar8216_priv *priv)
1648{
1649    u32 val;
1650    u16 id;
1651    int i;
1652
1653    val = ar8216_mii_read(priv, AR8216_REG_CTRL);
1654    if (val == ~0)
1655        return -ENODEV;
1656
1657    id = val & (AR8216_CTRL_REVISION | AR8216_CTRL_VERSION);
1658    for (i = 0; i < AR8X16_PROBE_RETRIES; i++) {
1659        u16 t;
1660
1661        val = ar8216_mii_read(priv, AR8216_REG_CTRL);
1662        if (val == ~0)
1663            return -ENODEV;
1664
1665        t = val & (AR8216_CTRL_REVISION | AR8216_CTRL_VERSION);
1666        if (t != id)
1667            return -ENODEV;
1668    }
1669
1670    priv->chip_ver = (id & AR8216_CTRL_VERSION) >> AR8216_CTRL_VERSION_S;
1671    priv->chip_rev = (id & AR8216_CTRL_REVISION);
1672
1673    switch (priv->chip_ver) {
1674    case AR8XXX_VER_AR8216:
1675        priv->chip = &ar8216_chip;
1676        break;
1677    case AR8XXX_VER_AR8236:
1678        priv->chip = &ar8236_chip;
1679        break;
1680    case AR8XXX_VER_AR8316:
1681        priv->chip = &ar8316_chip;
1682        break;
1683    case AR8XXX_VER_AR8327:
1684        priv->mii_lo_first = true;
1685        priv->chip = &ar8327_chip;
1686        break;
1687    default:
1688        printk(KERN_DEBUG
1689            "ar8216: Unknown Atheros device [ver=%d, rev=%d, phy_id=%04x%04x]\n",
1690            priv->chip_ver, priv->chip_rev,
1691            mdiobus_read(priv->phy->bus, priv->phy->addr, 2),
1692            mdiobus_read(priv->phy->bus, priv->phy->addr, 3));
1693
1694        return -ENODEV;
1695    }
1696
1697    return 0;
1698}
1699
1700static void
1701ar8xxx_mib_work_func(struct work_struct *work)
1702{
1703    struct ar8216_priv *priv;
1704    int err;
1705
1706    priv = container_of(work, struct ar8216_priv, mib_work.work);
1707
1708    mutex_lock(&priv->mib_lock);
1709
1710    err = ar8216_mib_capture(priv);
1711    if (err)
1712        goto next_port;
1713
1714    ar8216_mib_fetch_port_stat(priv, priv->mib_next_port, false);
1715
1716next_port:
1717    priv->mib_next_port++;
1718    if (priv->mib_next_port >= priv->dev.ports)
1719        priv->mib_next_port = 0;
1720
1721    mutex_unlock(&priv->mib_lock);
1722    schedule_delayed_work(&priv->mib_work,
1723                  msecs_to_jiffies(AR8XXX_MIB_WORK_DELAY));
1724}
1725
1726static int
1727ar8xxx_mib_init(struct ar8216_priv *priv)
1728{
1729    unsigned int len;
1730
1731    if (!ar8xxx_has_mib_counters(priv))
1732        return 0;
1733
1734    BUG_ON(!priv->chip->mib_decs || !priv->chip->num_mibs);
1735
1736    len = priv->dev.ports * priv->chip->num_mibs *
1737          sizeof(*priv->mib_stats);
1738    priv->mib_stats = kzalloc(len, GFP_KERNEL);
1739
1740    if (!priv->mib_stats)
1741        return -ENOMEM;
1742
1743    mutex_init(&priv->mib_lock);
1744    INIT_DELAYED_WORK(&priv->mib_work, ar8xxx_mib_work_func);
1745
1746    return 0;
1747}
1748
1749static void
1750ar8xxx_mib_start(struct ar8216_priv *priv)
1751{
1752    if (!ar8xxx_has_mib_counters(priv))
1753        return;
1754
1755    schedule_delayed_work(&priv->mib_work,
1756                  msecs_to_jiffies(AR8XXX_MIB_WORK_DELAY));
1757}
1758
1759static void
1760ar8xxx_mib_cleanup(struct ar8216_priv *priv)
1761{
1762    if (!ar8xxx_has_mib_counters(priv))
1763        return;
1764
1765    cancel_delayed_work(&priv->mib_work);
1766    kfree(priv->mib_stats);
1767}
1768
1769static int
1770ar8216_config_init(struct phy_device *pdev)
1771{
1772    struct ar8216_priv *priv = pdev->priv;
1773    struct net_device *dev = pdev->attached_dev;
1774    struct switch_dev *swdev;
1775    int ret;
1776
1777    if (!priv) {
1778        priv = kzalloc(sizeof(struct ar8216_priv), GFP_KERNEL);
1779        if (priv == NULL)
1780            return -ENOMEM;
1781    }
1782
1783    priv->phy = pdev;
1784
1785    ret = ar8216_id_chip(priv);
1786    if (ret)
1787        goto err_free_priv;
1788
1789    if (pdev->addr != 0) {
1790        if (ar8xxx_has_gige(priv)) {
1791            pdev->supported |= SUPPORTED_1000baseT_Full;
1792            pdev->advertising |= ADVERTISED_1000baseT_Full;
1793        }
1794
1795        if (chip_is_ar8316(priv)) {
1796            /* check if we're attaching to the switch twice */
1797            pdev = pdev->bus->phy_map[0];
1798            if (!pdev) {
1799                kfree(priv);
1800                return 0;
1801            }
1802
1803            /* switch device has not been initialized, reuse priv */
1804            if (!pdev->priv) {
1805                priv->port4_phy = true;
1806                pdev->priv = priv;
1807                return 0;
1808            }
1809
1810            kfree(priv);
1811
1812            /* switch device has been initialized, reinit */
1813            priv = pdev->priv;
1814            priv->dev.ports = (AR8216_NUM_PORTS - 1);
1815            priv->initialized = false;
1816            priv->port4_phy = true;
1817            ar8316_hw_init(priv);
1818            return 0;
1819        }
1820
1821        kfree(priv);
1822        return 0;
1823    }
1824
1825    if (ar8xxx_has_gige(priv))
1826        pdev->supported = SUPPORTED_1000baseT_Full;
1827    else
1828        pdev->supported = SUPPORTED_100baseT_Full;
1829    pdev->advertising = pdev->supported;
1830
1831    mutex_init(&priv->reg_mutex);
1832    priv->read = ar8216_mii_read;
1833    priv->write = ar8216_mii_write;
1834
1835    pdev->priv = priv;
1836
1837    swdev = &priv->dev;
1838    swdev->cpu_port = AR8216_PORT_CPU;
1839    swdev->ops = &ar8216_sw_ops;
1840    swdev->ports = AR8216_NUM_PORTS;
1841
1842    if (chip_is_ar8316(priv)) {
1843        swdev->name = "Atheros AR8316";
1844        swdev->vlans = AR8X16_MAX_VLANS;
1845
1846        if (priv->port4_phy) {
1847            /* port 5 connected to the other mac, therefore unusable */
1848            swdev->ports = (AR8216_NUM_PORTS - 1);
1849        }
1850    } else if (chip_is_ar8236(priv)) {
1851        swdev->name = "Atheros AR8236";
1852        swdev->vlans = AR8216_NUM_VLANS;
1853        swdev->ports = AR8216_NUM_PORTS;
1854    } else if (chip_is_ar8327(priv)) {
1855        swdev->name = "Atheros AR8327";
1856        swdev->vlans = AR8X16_MAX_VLANS;
1857        swdev->ports = AR8327_NUM_PORTS;
1858    } else {
1859        swdev->name = "Atheros AR8216";
1860        swdev->vlans = AR8216_NUM_VLANS;
1861    }
1862
1863    ret = ar8xxx_mib_init(priv);
1864    if (ret)
1865        goto err_free_priv;
1866
1867    ret = register_switch(&priv->dev, pdev->attached_dev);
1868    if (ret)
1869        goto err_cleanup_mib;
1870
1871    printk(KERN_INFO "%s: %s switch driver attached.\n",
1872        pdev->attached_dev->name, swdev->name);
1873
1874    priv->init = true;
1875
1876    ret = priv->chip->hw_init(priv);
1877    if (ret)
1878        goto err_cleanup_mib;
1879
1880    ret = ar8216_sw_reset_switch(&priv->dev);
1881    if (ret)
1882        goto err_cleanup_mib;
1883
1884    dev->phy_ptr = priv;
1885
1886    /* VID fixup only needed on ar8216 */
1887    if (chip_is_ar8216(priv) && pdev->addr == 0) {
1888        dev->priv_flags |= IFF_NO_IP_ALIGN;
1889        dev->eth_mangle_rx = ar8216_mangle_rx;
1890        dev->eth_mangle_tx = ar8216_mangle_tx;
1891    }
1892
1893    priv->init = false;
1894
1895    ar8xxx_mib_start(priv);
1896
1897    return 0;
1898
1899err_cleanup_mib:
1900    ar8xxx_mib_cleanup(priv);
1901err_free_priv:
1902    kfree(priv);
1903    return ret;
1904}
1905
1906static int
1907ar8216_read_status(struct phy_device *phydev)
1908{
1909    struct ar8216_priv *priv = phydev->priv;
1910    struct switch_port_link link;
1911    int ret;
1912
1913    if (phydev->addr != 0)
1914        return genphy_read_status(phydev);
1915
1916    ar8216_read_port_link(priv, phydev->addr, &link);
1917    phydev->link = !!link.link;
1918    if (!phydev->link)
1919        return 0;
1920
1921    switch (link.speed) {
1922    case SWITCH_PORT_SPEED_10:
1923        phydev->speed = SPEED_10;
1924        break;
1925    case SWITCH_PORT_SPEED_100:
1926        phydev->speed = SPEED_100;
1927        break;
1928    case SWITCH_PORT_SPEED_1000:
1929        phydev->speed = SPEED_1000;
1930        break;
1931    default:
1932        phydev->speed = 0;
1933    }
1934    phydev->duplex = link.duplex ? DUPLEX_FULL : DUPLEX_HALF;
1935
1936    /* flush the address translation unit */
1937    mutex_lock(&priv->reg_mutex);
1938    ret = priv->chip->atu_flush(priv);
1939    mutex_unlock(&priv->reg_mutex);
1940
1941    phydev->state = PHY_RUNNING;
1942    netif_carrier_on(phydev->attached_dev);
1943    phydev->adjust_link(phydev->attached_dev);
1944
1945    return ret;
1946}
1947
1948static int
1949ar8216_config_aneg(struct phy_device *phydev)
1950{
1951    if (phydev->addr == 0)
1952        return 0;
1953
1954    return genphy_config_aneg(phydev);
1955}
1956
1957static int
1958ar8216_probe(struct phy_device *pdev)
1959{
1960    struct ar8216_priv *priv;
1961    int ret;
1962
1963    priv = kzalloc(sizeof(struct ar8216_priv), GFP_KERNEL);
1964    if (priv == NULL)
1965        return -ENOMEM;
1966
1967    priv->phy = pdev;
1968
1969    ret = ar8216_id_chip(priv);
1970    kfree(priv);
1971
1972    return ret;
1973}
1974
1975static void
1976ar8216_remove(struct phy_device *pdev)
1977{
1978    struct ar8216_priv *priv = pdev->priv;
1979    struct net_device *dev = pdev->attached_dev;
1980
1981    if (!priv)
1982        return;
1983
1984    dev->priv_flags &= ~IFF_NO_IP_ALIGN;
1985    dev->eth_mangle_rx = NULL;
1986    dev->eth_mangle_tx = NULL;
1987
1988    if (pdev->addr == 0)
1989        unregister_switch(&priv->dev);
1990
1991    ar8xxx_mib_cleanup(priv);
1992    kfree(priv);
1993}
1994
1995static struct phy_driver ar8216_driver = {
1996    .phy_id = 0x004d0000,
1997    .name = "Atheros AR8216/AR8236/AR8316",
1998    .phy_id_mask = 0xffff0000,
1999    .features = PHY_BASIC_FEATURES,
2000    .probe = ar8216_probe,
2001    .remove = ar8216_remove,
2002    .config_init = &ar8216_config_init,
2003    .config_aneg = &ar8216_config_aneg,
2004    .read_status = &ar8216_read_status,
2005    .driver = { .owner = THIS_MODULE },
2006};
2007
2008int __init
2009ar8216_init(void)
2010{
2011    return phy_driver_register(&ar8216_driver);
2012}
2013
2014void __exit
2015ar8216_exit(void)
2016{
2017    phy_driver_unregister(&ar8216_driver);
2018}
2019
2020module_init(ar8216_init);
2021module_exit(ar8216_exit);
2022MODULE_LICENSE("GPL");
2023
2024

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