| 1 | --- a/arch/mips/bcm47xx/nvram.c |
| 2 | +++ b/arch/mips/bcm47xx/nvram.c |
| 3 | @@ -43,8 +43,8 @@ static void early_nvram_init(void) |
| 4 | #ifdef CONFIG_BCM47XX_SSB |
| 5 | case BCM47XX_BUS_TYPE_SSB: |
| 6 | mcore_ssb = &bcm47xx_bus.ssb.mipscore; |
| 7 | - base = mcore_ssb->flash_window; |
| 8 | - lim = mcore_ssb->flash_window_size; |
| 9 | + base = mcore_ssb->pflash.window; |
| 10 | + lim = mcore_ssb->pflash.window_size; |
| 11 | break; |
| 12 | #endif |
| 13 | #ifdef CONFIG_BCM47XX_BCMA |
| 14 | --- a/arch/mips/bcm47xx/wgt634u.c |
| 15 | +++ b/arch/mips/bcm47xx/wgt634u.c |
| 16 | @@ -156,10 +156,10 @@ static int __init wgt634u_init(void) |
| 17 | SSB_CHIPCO_IRQ_GPIO); |
| 18 | } |
| 19 | |
| 20 | - wgt634u_flash_data.width = mcore->flash_buswidth; |
| 21 | - wgt634u_flash_resource.start = mcore->flash_window; |
| 22 | - wgt634u_flash_resource.end = mcore->flash_window |
| 23 | - + mcore->flash_window_size |
| 24 | + wgt634u_flash_data.width = mcore->pflash.buswidth; |
| 25 | + wgt634u_flash_resource.start = mcore->pflash.window; |
| 26 | + wgt634u_flash_resource.end = mcore->pflash.window |
| 27 | + + mcore->pflash.window_size |
| 28 | - 1; |
| 29 | return platform_add_devices(wgt634u_devices, |
| 30 | ARRAY_SIZE(wgt634u_devices)); |
| 31 | --- a/drivers/bcma/Kconfig |
| 32 | +++ b/drivers/bcma/Kconfig |
| 33 | @@ -48,12 +48,12 @@ config BCMA_DRIVER_MIPS |
| 34 | |
| 35 | config BCMA_SFLASH |
| 36 | bool |
| 37 | - depends on BCMA_DRIVER_MIPS && BROKEN |
| 38 | + depends on BCMA_DRIVER_MIPS |
| 39 | default y |
| 40 | |
| 41 | config BCMA_NFLASH |
| 42 | bool |
| 43 | - depends on BCMA_DRIVER_MIPS && BROKEN |
| 44 | + depends on BCMA_DRIVER_MIPS |
| 45 | default y |
| 46 | |
| 47 | config BCMA_DRIVER_GMAC_CMN |
| 48 | --- a/drivers/bcma/bcma_private.h |
| 49 | +++ b/drivers/bcma/bcma_private.h |
| 50 | @@ -48,12 +48,13 @@ void bcma_chipco_serial_init(struct bcma |
| 51 | #endif /* CONFIG_BCMA_DRIVER_MIPS */ |
| 52 | |
| 53 | /* driver_chipcommon_pmu.c */ |
| 54 | -u32 bcma_pmu_alp_clock(struct bcma_drv_cc *cc); |
| 55 | -u32 bcma_pmu_get_clockcpu(struct bcma_drv_cc *cc); |
| 56 | +u32 bcma_pmu_get_alp_clock(struct bcma_drv_cc *cc); |
| 57 | +u32 bcma_pmu_get_cpu_clock(struct bcma_drv_cc *cc); |
| 58 | |
| 59 | #ifdef CONFIG_BCMA_SFLASH |
| 60 | /* driver_chipcommon_sflash.c */ |
| 61 | int bcma_sflash_init(struct bcma_drv_cc *cc); |
| 62 | +extern struct platform_device bcma_sflash_dev; |
| 63 | #else |
| 64 | static inline int bcma_sflash_init(struct bcma_drv_cc *cc) |
| 65 | { |
| 66 | @@ -65,6 +66,7 @@ static inline int bcma_sflash_init(struc |
| 67 | #ifdef CONFIG_BCMA_NFLASH |
| 68 | /* driver_chipcommon_nflash.c */ |
| 69 | int bcma_nflash_init(struct bcma_drv_cc *cc); |
| 70 | +extern struct platform_device bcma_nflash_dev; |
| 71 | #else |
| 72 | static inline int bcma_nflash_init(struct bcma_drv_cc *cc) |
| 73 | { |
| 74 | @@ -82,6 +84,8 @@ extern void __exit bcma_host_pci_exit(vo |
| 75 | /* driver_pci.c */ |
| 76 | u32 bcma_pcie_read(struct bcma_drv_pci *pc, u32 address); |
| 77 | |
| 78 | +extern int bcma_chipco_watchdog_register(struct bcma_drv_cc *cc); |
| 79 | + |
| 80 | #ifdef CONFIG_BCMA_DRIVER_PCI_HOSTMODE |
| 81 | bool __devinit bcma_core_pci_is_in_hostmode(struct bcma_drv_pci *pc); |
| 82 | void __devinit bcma_core_pci_hostmode_init(struct bcma_drv_pci *pc); |
| 83 | --- a/drivers/bcma/core.c |
| 84 | +++ b/drivers/bcma/core.c |
| 85 | @@ -65,7 +65,7 @@ void bcma_core_set_clockmode(struct bcma |
| 86 | switch (clkmode) { |
| 87 | case BCMA_CLKMODE_FAST: |
| 88 | bcma_set32(core, BCMA_CLKCTLST, BCMA_CLKCTLST_FORCEHT); |
| 89 | - udelay(64); |
| 90 | + usleep_range(64, 300); |
| 91 | for (i = 0; i < 1500; i++) { |
| 92 | if (bcma_read32(core, BCMA_CLKCTLST) & |
| 93 | BCMA_CLKCTLST_HAVEHT) { |
| 94 | --- a/drivers/bcma/driver_chipcommon.c |
| 95 | +++ b/drivers/bcma/driver_chipcommon.c |
| 96 | @@ -4,12 +4,15 @@ |
| 97 | * |
| 98 | * Copyright 2005, Broadcom Corporation |
| 99 | * Copyright 2006, 2007, Michael Buesch <m@bues.ch> |
| 100 | + * Copyright 2012, Hauke Mehrtens <hauke@hauke-m.de> |
| 101 | * |
| 102 | * Licensed under the GNU/GPL. See COPYING for details. |
| 103 | */ |
| 104 | |
| 105 | #include "bcma_private.h" |
| 106 | +#include <linux/bcm47xx_wdt.h> |
| 107 | #include <linux/export.h> |
| 108 | +#include <linux/platform_device.h> |
| 109 | #include <linux/bcma/bcma.h> |
| 110 | |
| 111 | static inline u32 bcma_cc_write32_masked(struct bcma_drv_cc *cc, u16 offset, |
| 112 | @@ -22,12 +25,93 @@ static inline u32 bcma_cc_write32_masked |
| 113 | return value; |
| 114 | } |
| 115 | |
| 116 | -void bcma_core_chipcommon_init(struct bcma_drv_cc *cc) |
| 117 | +static u32 bcma_chipco_get_alp_clock(struct bcma_drv_cc *cc) |
| 118 | { |
| 119 | - u32 leddc_on = 10; |
| 120 | - u32 leddc_off = 90; |
| 121 | + if (cc->capabilities & BCMA_CC_CAP_PMU) |
| 122 | + return bcma_pmu_get_alp_clock(cc); |
| 123 | |
| 124 | - if (cc->setup_done) |
| 125 | + return 20000000; |
| 126 | +} |
| 127 | + |
| 128 | +static u32 bcma_chipco_watchdog_get_max_timer(struct bcma_drv_cc *cc) |
| 129 | +{ |
| 130 | + struct bcma_bus *bus = cc->core->bus; |
| 131 | + u32 nb; |
| 132 | + |
| 133 | + if (cc->capabilities & BCMA_CC_CAP_PMU) { |
| 134 | + if (bus->chipinfo.id == BCMA_CHIP_ID_BCM4706) |
| 135 | + nb = 32; |
| 136 | + else if (cc->core->id.rev < 26) |
| 137 | + nb = 16; |
| 138 | + else |
| 139 | + nb = (cc->core->id.rev >= 37) ? 32 : 24; |
| 140 | + } else { |
| 141 | + nb = 28; |
| 142 | + } |
| 143 | + if (nb == 32) |
| 144 | + return 0xffffffff; |
| 145 | + else |
| 146 | + return (1 << nb) - 1; |
| 147 | +} |
| 148 | + |
| 149 | +static u32 bcma_chipco_watchdog_timer_set_wdt(struct bcm47xx_wdt *wdt, |
| 150 | + u32 ticks) |
| 151 | +{ |
| 152 | + struct bcma_drv_cc *cc = bcm47xx_wdt_get_drvdata(wdt); |
| 153 | + |
| 154 | + return bcma_chipco_watchdog_timer_set(cc, ticks); |
| 155 | +} |
| 156 | + |
| 157 | +static u32 bcma_chipco_watchdog_timer_set_ms_wdt(struct bcm47xx_wdt *wdt, |
| 158 | + u32 ms) |
| 159 | +{ |
| 160 | + struct bcma_drv_cc *cc = bcm47xx_wdt_get_drvdata(wdt); |
| 161 | + u32 ticks; |
| 162 | + |
| 163 | + ticks = bcma_chipco_watchdog_timer_set(cc, cc->ticks_per_ms * ms); |
| 164 | + return ticks / cc->ticks_per_ms; |
| 165 | +} |
| 166 | + |
| 167 | +static int bcma_chipco_watchdog_ticks_per_ms(struct bcma_drv_cc *cc) |
| 168 | +{ |
| 169 | + struct bcma_bus *bus = cc->core->bus; |
| 170 | + |
| 171 | + if (cc->capabilities & BCMA_CC_CAP_PMU) { |
| 172 | + if (bus->chipinfo.id == BCMA_CHIP_ID_BCM4706) |
| 173 | + /* 4706 CC and PMU watchdogs are clocked at 1/4 of ALP clock */ |
| 174 | + return bcma_chipco_get_alp_clock(cc) / 4000; |
| 175 | + else |
| 176 | + /* based on 32KHz ILP clock */ |
| 177 | + return 32; |
| 178 | + } else { |
| 179 | + return bcma_chipco_get_alp_clock(cc) / 1000; |
| 180 | + } |
| 181 | +} |
| 182 | + |
| 183 | +int bcma_chipco_watchdog_register(struct bcma_drv_cc *cc) |
| 184 | +{ |
| 185 | + struct bcm47xx_wdt wdt = {}; |
| 186 | + struct platform_device *pdev; |
| 187 | + |
| 188 | + wdt.driver_data = cc; |
| 189 | + wdt.timer_set = bcma_chipco_watchdog_timer_set_wdt; |
| 190 | + wdt.timer_set_ms = bcma_chipco_watchdog_timer_set_ms_wdt; |
| 191 | + wdt.max_timer_ms = bcma_chipco_watchdog_get_max_timer(cc) / cc->ticks_per_ms; |
| 192 | + |
| 193 | + pdev = platform_device_register_data(NULL, "bcm47xx-wdt", |
| 194 | + cc->core->bus->num, &wdt, |
| 195 | + sizeof(wdt)); |
| 196 | + if (IS_ERR(pdev)) |
| 197 | + return PTR_ERR(pdev); |
| 198 | + |
| 199 | + cc->watchdog = pdev; |
| 200 | + |
| 201 | + return 0; |
| 202 | +} |
| 203 | + |
| 204 | +void bcma_core_chipcommon_early_init(struct bcma_drv_cc *cc) |
| 205 | +{ |
| 206 | + if (cc->early_setup_done) |
| 207 | return; |
| 208 | |
| 209 | if (cc->core->id.rev >= 11) |
| 210 | @@ -36,6 +120,22 @@ void bcma_core_chipcommon_init(struct bc |
| 211 | if (cc->core->id.rev >= 35) |
| 212 | cc->capabilities_ext = bcma_cc_read32(cc, BCMA_CC_CAP_EXT); |
| 213 | |
| 214 | + if (cc->capabilities & BCMA_CC_CAP_PMU) |
| 215 | + bcma_pmu_early_init(cc); |
| 216 | + |
| 217 | + cc->early_setup_done = true; |
| 218 | +} |
| 219 | + |
| 220 | +void bcma_core_chipcommon_init(struct bcma_drv_cc *cc) |
| 221 | +{ |
| 222 | + u32 leddc_on = 10; |
| 223 | + u32 leddc_off = 90; |
| 224 | + |
| 225 | + if (cc->setup_done) |
| 226 | + return; |
| 227 | + |
| 228 | + bcma_core_chipcommon_early_init(cc); |
| 229 | + |
| 230 | if (cc->core->id.rev >= 20) { |
| 231 | bcma_cc_write32(cc, BCMA_CC_GPIOPULLUP, 0); |
| 232 | bcma_cc_write32(cc, BCMA_CC_GPIOPULLDOWN, 0); |
| 233 | @@ -56,15 +156,33 @@ void bcma_core_chipcommon_init(struct bc |
| 234 | ((leddc_on << BCMA_CC_GPIOTIMER_ONTIME_SHIFT) | |
| 235 | (leddc_off << BCMA_CC_GPIOTIMER_OFFTIME_SHIFT))); |
| 236 | } |
| 237 | + cc->ticks_per_ms = bcma_chipco_watchdog_ticks_per_ms(cc); |
| 238 | |
| 239 | cc->setup_done = true; |
| 240 | } |
| 241 | |
| 242 | /* Set chip watchdog reset timer to fire in 'ticks' backplane cycles */ |
| 243 | -void bcma_chipco_watchdog_timer_set(struct bcma_drv_cc *cc, u32 ticks) |
| 244 | +u32 bcma_chipco_watchdog_timer_set(struct bcma_drv_cc *cc, u32 ticks) |
| 245 | { |
| 246 | - /* instant NMI */ |
| 247 | - bcma_cc_write32(cc, BCMA_CC_WATCHDOG, ticks); |
| 248 | + u32 maxt; |
| 249 | + enum bcma_clkmode clkmode; |
| 250 | + |
| 251 | + maxt = bcma_chipco_watchdog_get_max_timer(cc); |
| 252 | + if (cc->capabilities & BCMA_CC_CAP_PMU) { |
| 253 | + if (ticks == 1) |
| 254 | + ticks = 2; |
| 255 | + else if (ticks > maxt) |
| 256 | + ticks = maxt; |
| 257 | + bcma_cc_write32(cc, BCMA_CC_PMU_WATCHDOG, ticks); |
| 258 | + } else { |
| 259 | + clkmode = ticks ? BCMA_CLKMODE_FAST : BCMA_CLKMODE_DYNAMIC; |
| 260 | + bcma_core_set_clockmode(cc->core, clkmode); |
| 261 | + if (ticks > maxt) |
| 262 | + ticks = maxt; |
| 263 | + /* instant NMI */ |
| 264 | + bcma_cc_write32(cc, BCMA_CC_WATCHDOG, ticks); |
| 265 | + } |
| 266 | + return ticks; |
| 267 | } |
| 268 | |
| 269 | void bcma_chipco_irq_mask(struct bcma_drv_cc *cc, u32 mask, u32 value) |
| 270 | @@ -118,8 +236,7 @@ void bcma_chipco_serial_init(struct bcma |
| 271 | struct bcma_serial_port *ports = cc->serial_ports; |
| 272 | |
| 273 | if (ccrev >= 11 && ccrev != 15) { |
| 274 | - /* Fixed ALP clock */ |
| 275 | - baud_base = bcma_pmu_alp_clock(cc); |
| 276 | + baud_base = bcma_chipco_get_alp_clock(cc); |
| 277 | if (ccrev >= 21) { |
| 278 | /* Turn off UART clock before switching clocksource. */ |
| 279 | bcma_cc_write32(cc, BCMA_CC_CORECTL, |
| 280 | --- a/drivers/bcma/driver_chipcommon_nflash.c |
| 281 | +++ b/drivers/bcma/driver_chipcommon_nflash.c |
| 282 | @@ -5,15 +5,40 @@ |
| 283 | * Licensed under the GNU/GPL. See COPYING for details. |
| 284 | */ |
| 285 | |
| 286 | +#include <linux/platform_device.h> |
| 287 | #include <linux/bcma/bcma.h> |
| 288 | -#include <linux/bcma/bcma_driver_chipcommon.h> |
| 289 | -#include <linux/delay.h> |
| 290 | |
| 291 | #include "bcma_private.h" |
| 292 | |
| 293 | +struct platform_device bcma_nflash_dev = { |
| 294 | + .name = "bcma_nflash", |
| 295 | + .num_resources = 0, |
| 296 | +}; |
| 297 | + |
| 298 | /* Initialize NAND flash access */ |
| 299 | int bcma_nflash_init(struct bcma_drv_cc *cc) |
| 300 | { |
| 301 | - bcma_err(cc->core->bus, "NAND flash support is broken\n"); |
| 302 | + struct bcma_bus *bus = cc->core->bus; |
| 303 | + |
| 304 | + if (bus->chipinfo.id != BCMA_CHIP_ID_BCM4706 && |
| 305 | + cc->core->id.rev != 0x38) { |
| 306 | + bcma_err(bus, "NAND flash on unsupported board!\n"); |
| 307 | + return -ENOTSUPP; |
| 308 | + } |
| 309 | + |
| 310 | + if (!(cc->capabilities & BCMA_CC_CAP_NFLASH)) { |
| 311 | + bcma_err(bus, "NAND flash not present according to ChipCommon\n"); |
| 312 | + return -ENODEV; |
| 313 | + } |
| 314 | + |
| 315 | + cc->nflash.present = true; |
| 316 | + if (cc->core->id.rev == 38 && |
| 317 | + (cc->status & BCMA_CC_CHIPST_5357_NAND_BOOT)) |
| 318 | + cc->nflash.boot = true; |
| 319 | + |
| 320 | + /* Prepare platform device, but don't register it yet. It's too early, |
| 321 | + * malloc (required by device_private_init) is not available yet. */ |
| 322 | + bcma_nflash_dev.dev.platform_data = &cc->nflash; |
| 323 | + |
| 324 | return 0; |
| 325 | } |
| 326 | --- a/drivers/bcma/driver_chipcommon_pmu.c |
| 327 | +++ b/drivers/bcma/driver_chipcommon_pmu.c |
| 328 | @@ -76,7 +76,10 @@ static void bcma_pmu_resources_init(stru |
| 329 | if (max_msk) |
| 330 | bcma_cc_write32(cc, BCMA_CC_PMU_MAXRES_MSK, max_msk); |
| 331 | |
| 332 | - /* Add some delay; allow resources to come up and settle. */ |
| 333 | + /* |
| 334 | + * Add some delay; allow resources to come up and settle. |
| 335 | + * Delay is required for SoC (early init). |
| 336 | + */ |
| 337 | mdelay(2); |
| 338 | } |
| 339 | |
| 340 | @@ -101,7 +104,7 @@ void bcma_chipco_bcm4331_ext_pa_lines_ct |
| 341 | bcma_cc_write32(cc, BCMA_CC_CHIPCTL, val); |
| 342 | } |
| 343 | |
| 344 | -void bcma_pmu_workarounds(struct bcma_drv_cc *cc) |
| 345 | +static void bcma_pmu_workarounds(struct bcma_drv_cc *cc) |
| 346 | { |
| 347 | struct bcma_bus *bus = cc->core->bus; |
| 348 | |
| 349 | @@ -141,7 +144,7 @@ void bcma_pmu_workarounds(struct bcma_dr |
| 350 | } |
| 351 | } |
| 352 | |
| 353 | -void bcma_pmu_init(struct bcma_drv_cc *cc) |
| 354 | +void bcma_pmu_early_init(struct bcma_drv_cc *cc) |
| 355 | { |
| 356 | u32 pmucap; |
| 357 | |
| 358 | @@ -150,7 +153,10 @@ void bcma_pmu_init(struct bcma_drv_cc *c |
| 359 | |
| 360 | bcma_debug(cc->core->bus, "Found rev %u PMU (capabilities 0x%08X)\n", |
| 361 | cc->pmu.rev, pmucap); |
| 362 | +} |
| 363 | |
| 364 | +void bcma_pmu_init(struct bcma_drv_cc *cc) |
| 365 | +{ |
| 366 | if (cc->pmu.rev == 1) |
| 367 | bcma_cc_mask32(cc, BCMA_CC_PMU_CTL, |
| 368 | ~BCMA_CC_PMU_CTL_NOILPONW); |
| 369 | @@ -162,7 +168,7 @@ void bcma_pmu_init(struct bcma_drv_cc *c |
| 370 | bcma_pmu_workarounds(cc); |
| 371 | } |
| 372 | |
| 373 | -u32 bcma_pmu_alp_clock(struct bcma_drv_cc *cc) |
| 374 | +u32 bcma_pmu_get_alp_clock(struct bcma_drv_cc *cc) |
| 375 | { |
| 376 | struct bcma_bus *bus = cc->core->bus; |
| 377 | |
| 378 | @@ -190,7 +196,7 @@ u32 bcma_pmu_alp_clock(struct bcma_drv_c |
| 379 | /* Find the output of the "m" pll divider given pll controls that start with |
| 380 | * pllreg "pll0" i.e. 12 for main 6 for phy, 0 for misc. |
| 381 | */ |
| 382 | -static u32 bcma_pmu_clock(struct bcma_drv_cc *cc, u32 pll0, u32 m) |
| 383 | +static u32 bcma_pmu_pll_clock(struct bcma_drv_cc *cc, u32 pll0, u32 m) |
| 384 | { |
| 385 | u32 tmp, div, ndiv, p1, p2, fc; |
| 386 | struct bcma_bus *bus = cc->core->bus; |
| 387 | @@ -219,14 +225,14 @@ static u32 bcma_pmu_clock(struct bcma_dr |
| 388 | ndiv = (tmp & BCMA_CC_PPL_NDIV_MASK) >> BCMA_CC_PPL_NDIV_SHIFT; |
| 389 | |
| 390 | /* Do calculation in Mhz */ |
| 391 | - fc = bcma_pmu_alp_clock(cc) / 1000000; |
| 392 | + fc = bcma_pmu_get_alp_clock(cc) / 1000000; |
| 393 | fc = (p1 * ndiv * fc) / p2; |
| 394 | |
| 395 | /* Return clock in Hertz */ |
| 396 | return (fc / div) * 1000000; |
| 397 | } |
| 398 | |
| 399 | -static u32 bcma_pmu_clock_bcm4706(struct bcma_drv_cc *cc, u32 pll0, u32 m) |
| 400 | +static u32 bcma_pmu_pll_clock_bcm4706(struct bcma_drv_cc *cc, u32 pll0, u32 m) |
| 401 | { |
| 402 | u32 tmp, ndiv, p1div, p2div; |
| 403 | u32 clock; |
| 404 | @@ -257,7 +263,7 @@ static u32 bcma_pmu_clock_bcm4706(struct |
| 405 | } |
| 406 | |
| 407 | /* query bus clock frequency for PMU-enabled chipcommon */ |
| 408 | -u32 bcma_pmu_get_clockcontrol(struct bcma_drv_cc *cc) |
| 409 | +static u32 bcma_pmu_get_bus_clock(struct bcma_drv_cc *cc) |
| 410 | { |
| 411 | struct bcma_bus *bus = cc->core->bus; |
| 412 | |
| 413 | @@ -265,40 +271,42 @@ u32 bcma_pmu_get_clockcontrol(struct bcm |
| 414 | case BCMA_CHIP_ID_BCM4716: |
| 415 | case BCMA_CHIP_ID_BCM4748: |
| 416 | case BCMA_CHIP_ID_BCM47162: |
| 417 | - return bcma_pmu_clock(cc, BCMA_CC_PMU4716_MAINPLL_PLL0, |
| 418 | - BCMA_CC_PMU5_MAINPLL_SSB); |
| 419 | + return bcma_pmu_pll_clock(cc, BCMA_CC_PMU4716_MAINPLL_PLL0, |
| 420 | + BCMA_CC_PMU5_MAINPLL_SSB); |
| 421 | case BCMA_CHIP_ID_BCM5356: |
| 422 | - return bcma_pmu_clock(cc, BCMA_CC_PMU5356_MAINPLL_PLL0, |
| 423 | - BCMA_CC_PMU5_MAINPLL_SSB); |
| 424 | + return bcma_pmu_pll_clock(cc, BCMA_CC_PMU5356_MAINPLL_PLL0, |
| 425 | + BCMA_CC_PMU5_MAINPLL_SSB); |
| 426 | case BCMA_CHIP_ID_BCM5357: |
| 427 | case BCMA_CHIP_ID_BCM4749: |
| 428 | - return bcma_pmu_clock(cc, BCMA_CC_PMU5357_MAINPLL_PLL0, |
| 429 | - BCMA_CC_PMU5_MAINPLL_SSB); |
| 430 | + return bcma_pmu_pll_clock(cc, BCMA_CC_PMU5357_MAINPLL_PLL0, |
| 431 | + BCMA_CC_PMU5_MAINPLL_SSB); |
| 432 | case BCMA_CHIP_ID_BCM4706: |
| 433 | - return bcma_pmu_clock_bcm4706(cc, BCMA_CC_PMU4706_MAINPLL_PLL0, |
| 434 | - BCMA_CC_PMU5_MAINPLL_SSB); |
| 435 | + return bcma_pmu_pll_clock_bcm4706(cc, |
| 436 | + BCMA_CC_PMU4706_MAINPLL_PLL0, |
| 437 | + BCMA_CC_PMU5_MAINPLL_SSB); |
| 438 | case BCMA_CHIP_ID_BCM53572: |
| 439 | return 75000000; |
| 440 | default: |
| 441 | - bcma_warn(bus, "No backplane clock specified for %04X device, pmu rev. %d, using default %d Hz\n", |
| 442 | + bcma_warn(bus, "No bus clock specified for %04X device, pmu rev. %d, using default %d Hz\n", |
| 443 | bus->chipinfo.id, cc->pmu.rev, BCMA_CC_PMU_HT_CLOCK); |
| 444 | } |
| 445 | return BCMA_CC_PMU_HT_CLOCK; |
| 446 | } |
| 447 | |
| 448 | /* query cpu clock frequency for PMU-enabled chipcommon */ |
| 449 | -u32 bcma_pmu_get_clockcpu(struct bcma_drv_cc *cc) |
| 450 | +u32 bcma_pmu_get_cpu_clock(struct bcma_drv_cc *cc) |
| 451 | { |
| 452 | struct bcma_bus *bus = cc->core->bus; |
| 453 | |
| 454 | if (bus->chipinfo.id == BCMA_CHIP_ID_BCM53572) |
| 455 | return 300000000; |
| 456 | |
| 457 | + /* New PMUs can have different clock for bus and CPU */ |
| 458 | if (cc->pmu.rev >= 5) { |
| 459 | u32 pll; |
| 460 | switch (bus->chipinfo.id) { |
| 461 | case BCMA_CHIP_ID_BCM4706: |
| 462 | - return bcma_pmu_clock_bcm4706(cc, |
| 463 | + return bcma_pmu_pll_clock_bcm4706(cc, |
| 464 | BCMA_CC_PMU4706_MAINPLL_PLL0, |
| 465 | BCMA_CC_PMU5_MAINPLL_CPU); |
| 466 | case BCMA_CHIP_ID_BCM5356: |
| 467 | @@ -313,10 +321,11 @@ u32 bcma_pmu_get_clockcpu(struct bcma_dr |
| 468 | break; |
| 469 | } |
| 470 | |
| 471 | - return bcma_pmu_clock(cc, pll, BCMA_CC_PMU5_MAINPLL_CPU); |
| 472 | + return bcma_pmu_pll_clock(cc, pll, BCMA_CC_PMU5_MAINPLL_CPU); |
| 473 | } |
| 474 | |
| 475 | - return bcma_pmu_get_clockcontrol(cc); |
| 476 | + /* On old PMUs CPU has the same clock as the bus */ |
| 477 | + return bcma_pmu_get_bus_clock(cc); |
| 478 | } |
| 479 | |
| 480 | static void bcma_pmu_spuravoid_pll_write(struct bcma_drv_cc *cc, u32 offset, |
| 481 | --- a/drivers/bcma/driver_chipcommon_sflash.c |
| 482 | +++ b/drivers/bcma/driver_chipcommon_sflash.c |
| 483 | @@ -5,15 +5,161 @@ |
| 484 | * Licensed under the GNU/GPL. See COPYING for details. |
| 485 | */ |
| 486 | |
| 487 | +#include <linux/platform_device.h> |
| 488 | #include <linux/bcma/bcma.h> |
| 489 | -#include <linux/bcma/bcma_driver_chipcommon.h> |
| 490 | -#include <linux/delay.h> |
| 491 | |
| 492 | #include "bcma_private.h" |
| 493 | |
| 494 | +static struct resource bcma_sflash_resource = { |
| 495 | + .name = "bcma_sflash", |
| 496 | + .start = BCMA_SOC_FLASH2, |
| 497 | + .end = 0, |
| 498 | + .flags = IORESOURCE_MEM | IORESOURCE_READONLY, |
| 499 | +}; |
| 500 | + |
| 501 | +struct platform_device bcma_sflash_dev = { |
| 502 | + .name = "bcma_sflash", |
| 503 | + .resource = &bcma_sflash_resource, |
| 504 | + .num_resources = 1, |
| 505 | +}; |
| 506 | + |
| 507 | +struct bcma_sflash_tbl_e { |
| 508 | + char *name; |
| 509 | + u32 id; |
| 510 | + u32 blocksize; |
| 511 | + u16 numblocks; |
| 512 | +}; |
| 513 | + |
| 514 | +static struct bcma_sflash_tbl_e bcma_sflash_st_tbl[] = { |
| 515 | + { "M25P20", 0x11, 0x10000, 4, }, |
| 516 | + { "M25P40", 0x12, 0x10000, 8, }, |
| 517 | + |
| 518 | + { "M25P16", 0x14, 0x10000, 32, }, |
| 519 | + { "M25P32", 0x14, 0x10000, 64, }, |
| 520 | + { "M25P64", 0x16, 0x10000, 128, }, |
| 521 | + { "M25FL128", 0x17, 0x10000, 256, }, |
| 522 | + { 0 }, |
| 523 | +}; |
| 524 | + |
| 525 | +static struct bcma_sflash_tbl_e bcma_sflash_sst_tbl[] = { |
| 526 | + { "SST25WF512", 1, 0x1000, 16, }, |
| 527 | + { "SST25VF512", 0x48, 0x1000, 16, }, |
| 528 | + { "SST25WF010", 2, 0x1000, 32, }, |
| 529 | + { "SST25VF010", 0x49, 0x1000, 32, }, |
| 530 | + { "SST25WF020", 3, 0x1000, 64, }, |
| 531 | + { "SST25VF020", 0x43, 0x1000, 64, }, |
| 532 | + { "SST25WF040", 4, 0x1000, 128, }, |
| 533 | + { "SST25VF040", 0x44, 0x1000, 128, }, |
| 534 | + { "SST25VF040B", 0x8d, 0x1000, 128, }, |
| 535 | + { "SST25WF080", 5, 0x1000, 256, }, |
| 536 | + { "SST25VF080B", 0x8e, 0x1000, 256, }, |
| 537 | + { "SST25VF016", 0x41, 0x1000, 512, }, |
| 538 | + { "SST25VF032", 0x4a, 0x1000, 1024, }, |
| 539 | + { "SST25VF064", 0x4b, 0x1000, 2048, }, |
| 540 | + { 0 }, |
| 541 | +}; |
| 542 | + |
| 543 | +static struct bcma_sflash_tbl_e bcma_sflash_at_tbl[] = { |
| 544 | + { "AT45DB011", 0xc, 256, 512, }, |
| 545 | + { "AT45DB021", 0x14, 256, 1024, }, |
| 546 | + { "AT45DB041", 0x1c, 256, 2048, }, |
| 547 | + { "AT45DB081", 0x24, 256, 4096, }, |
| 548 | + { "AT45DB161", 0x2c, 512, 4096, }, |
| 549 | + { "AT45DB321", 0x34, 512, 8192, }, |
| 550 | + { "AT45DB642", 0x3c, 1024, 8192, }, |
| 551 | + { 0 }, |
| 552 | +}; |
| 553 | + |
| 554 | +static void bcma_sflash_cmd(struct bcma_drv_cc *cc, u32 opcode) |
| 555 | +{ |
| 556 | + int i; |
| 557 | + bcma_cc_write32(cc, BCMA_CC_FLASHCTL, |
| 558 | + BCMA_CC_FLASHCTL_START | opcode); |
| 559 | + for (i = 0; i < 1000; i++) { |
| 560 | + if (!(bcma_cc_read32(cc, BCMA_CC_FLASHCTL) & |
| 561 | + BCMA_CC_FLASHCTL_BUSY)) |
| 562 | + return; |
| 563 | + cpu_relax(); |
| 564 | + } |
| 565 | + bcma_err(cc->core->bus, "SFLASH control command failed (timeout)!\n"); |
| 566 | +} |
| 567 | + |
| 568 | /* Initialize serial flash access */ |
| 569 | int bcma_sflash_init(struct bcma_drv_cc *cc) |
| 570 | { |
| 571 | - bcma_err(cc->core->bus, "Serial flash support is broken\n"); |
| 572 | + struct bcma_bus *bus = cc->core->bus; |
| 573 | + struct bcma_sflash *sflash = &cc->sflash; |
| 574 | + struct bcma_sflash_tbl_e *e; |
| 575 | + u32 id, id2; |
| 576 | + |
| 577 | + switch (cc->capabilities & BCMA_CC_CAP_FLASHT) { |
| 578 | + case BCMA_CC_FLASHT_STSER: |
| 579 | + bcma_sflash_cmd(cc, BCMA_CC_FLASHCTL_ST_DP); |
| 580 | + |
| 581 | + bcma_cc_write32(cc, BCMA_CC_FLASHADDR, 0); |
| 582 | + bcma_sflash_cmd(cc, BCMA_CC_FLASHCTL_ST_RES); |
| 583 | + id = bcma_cc_read32(cc, BCMA_CC_FLASHDATA); |
| 584 | + |
| 585 | + bcma_cc_write32(cc, BCMA_CC_FLASHADDR, 1); |
| 586 | + bcma_sflash_cmd(cc, BCMA_CC_FLASHCTL_ST_RES); |
| 587 | + id2 = bcma_cc_read32(cc, BCMA_CC_FLASHDATA); |
| 588 | + |
| 589 | + switch (id) { |
| 590 | + case 0xbf: |
| 591 | + for (e = bcma_sflash_sst_tbl; e->name; e++) { |
| 592 | + if (e->id == id2) |
| 593 | + break; |
| 594 | + } |
| 595 | + break; |
| 596 | + case 0x13: |
| 597 | + return -ENOTSUPP; |
| 598 | + default: |
| 599 | + for (e = bcma_sflash_st_tbl; e->name; e++) { |
| 600 | + if (e->id == id) |
| 601 | + break; |
| 602 | + } |
| 603 | + break; |
| 604 | + } |
| 605 | + if (!e->name) { |
| 606 | + bcma_err(bus, "Unsupported ST serial flash (id: 0x%X, id2: 0x%X)\n", id, id2); |
| 607 | + return -ENOTSUPP; |
| 608 | + } |
| 609 | + |
| 610 | + break; |
| 611 | + case BCMA_CC_FLASHT_ATSER: |
| 612 | + bcma_sflash_cmd(cc, BCMA_CC_FLASHCTL_AT_STATUS); |
| 613 | + id = bcma_cc_read32(cc, BCMA_CC_FLASHDATA) & 0x3c; |
| 614 | + |
| 615 | + for (e = bcma_sflash_at_tbl; e->name; e++) { |
| 616 | + if (e->id == id) |
| 617 | + break; |
| 618 | + } |
| 619 | + if (!e->name) { |
| 620 | + bcma_err(bus, "Unsupported Atmel serial flash (id: 0x%X)\n", id); |
| 621 | + return -ENOTSUPP; |
| 622 | + } |
| 623 | + |
| 624 | + break; |
| 625 | + default: |
| 626 | + bcma_err(bus, "Unsupported flash type\n"); |
| 627 | + return -ENOTSUPP; |
| 628 | + } |
| 629 | + |
| 630 | + sflash->window = BCMA_SOC_FLASH2; |
| 631 | + sflash->blocksize = e->blocksize; |
| 632 | + sflash->numblocks = e->numblocks; |
| 633 | + sflash->size = sflash->blocksize * sflash->numblocks; |
| 634 | + sflash->present = true; |
| 635 | + |
| 636 | + bcma_info(bus, "Found %s serial flash (size: %dKiB, blocksize: 0x%X, blocks: %d)\n", |
| 637 | + e->name, sflash->size / 1024, sflash->blocksize, |
| 638 | + sflash->numblocks); |
| 639 | + |
| 640 | + /* Prepare platform device, but don't register it yet. It's too early, |
| 641 | + * malloc (required by device_private_init) is not available yet. */ |
| 642 | + bcma_sflash_dev.resource[0].end = bcma_sflash_dev.resource[0].start + |
| 643 | + sflash->size; |
| 644 | + bcma_sflash_dev.dev.platform_data = sflash; |
| 645 | + |
| 646 | return 0; |
| 647 | } |
| 648 | --- a/drivers/bcma/driver_mips.c |
| 649 | +++ b/drivers/bcma/driver_mips.c |
| 650 | @@ -115,7 +115,7 @@ static void bcma_core_mips_set_irq(struc |
| 651 | bcma_read32(mdev, BCMA_MIPS_MIPS74K_INTMASK(0)) & |
| 652 | ~(1 << irqflag)); |
| 653 | else |
| 654 | - bcma_write32(mdev, BCMA_MIPS_MIPS74K_INTMASK(irq), 0); |
| 655 | + bcma_write32(mdev, BCMA_MIPS_MIPS74K_INTMASK(oldirq), 0); |
| 656 | |
| 657 | /* assign the new one */ |
| 658 | if (irq == 0) { |
| 659 | @@ -171,7 +171,7 @@ u32 bcma_cpu_clock(struct bcma_drv_mips |
| 660 | struct bcma_bus *bus = mcore->core->bus; |
| 661 | |
| 662 | if (bus->drv_cc.capabilities & BCMA_CC_CAP_PMU) |
| 663 | - return bcma_pmu_get_clockcpu(&bus->drv_cc); |
| 664 | + return bcma_pmu_get_cpu_clock(&bus->drv_cc); |
| 665 | |
| 666 | bcma_err(bus, "No PMU available, need this to get the cpu clock\n"); |
| 667 | return 0; |
| 668 | @@ -181,47 +181,66 @@ EXPORT_SYMBOL(bcma_cpu_clock); |
| 669 | static void bcma_core_mips_flash_detect(struct bcma_drv_mips *mcore) |
| 670 | { |
| 671 | struct bcma_bus *bus = mcore->core->bus; |
| 672 | + struct bcma_drv_cc *cc = &bus->drv_cc; |
| 673 | |
| 674 | - switch (bus->drv_cc.capabilities & BCMA_CC_CAP_FLASHT) { |
| 675 | + switch (cc->capabilities & BCMA_CC_CAP_FLASHT) { |
| 676 | case BCMA_CC_FLASHT_STSER: |
| 677 | case BCMA_CC_FLASHT_ATSER: |
| 678 | bcma_debug(bus, "Found serial flash\n"); |
| 679 | - bcma_sflash_init(&bus->drv_cc); |
| 680 | + bcma_sflash_init(cc); |
| 681 | break; |
| 682 | case BCMA_CC_FLASHT_PARA: |
| 683 | bcma_debug(bus, "Found parallel flash\n"); |
| 684 | - bus->drv_cc.pflash.window = 0x1c000000; |
| 685 | - bus->drv_cc.pflash.window_size = 0x02000000; |
| 686 | + cc->pflash.present = true; |
| 687 | + cc->pflash.window = BCMA_SOC_FLASH2; |
| 688 | + cc->pflash.window_size = BCMA_SOC_FLASH2_SZ; |
| 689 | |
| 690 | - if ((bcma_read32(bus->drv_cc.core, BCMA_CC_FLASH_CFG) & |
| 691 | + if ((bcma_read32(cc->core, BCMA_CC_FLASH_CFG) & |
| 692 | BCMA_CC_FLASH_CFG_DS) == 0) |
| 693 | - bus->drv_cc.pflash.buswidth = 1; |
| 694 | + cc->pflash.buswidth = 1; |
| 695 | else |
| 696 | - bus->drv_cc.pflash.buswidth = 2; |
| 697 | + cc->pflash.buswidth = 2; |
| 698 | break; |
| 699 | default: |
| 700 | bcma_err(bus, "Flash type not supported\n"); |
| 701 | } |
| 702 | |
| 703 | - if (bus->drv_cc.core->id.rev == 38 || |
| 704 | + if (cc->core->id.rev == 38 || |
| 705 | bus->chipinfo.id == BCMA_CHIP_ID_BCM4706) { |
| 706 | - if (bus->drv_cc.capabilities & BCMA_CC_CAP_NFLASH) { |
| 707 | + if (cc->capabilities & BCMA_CC_CAP_NFLASH) { |
| 708 | bcma_debug(bus, "Found NAND flash\n"); |
| 709 | - bcma_nflash_init(&bus->drv_cc); |
| 710 | + bcma_nflash_init(cc); |
| 711 | } |
| 712 | } |
| 713 | } |
| 714 | |
| 715 | +void bcma_core_mips_early_init(struct bcma_drv_mips *mcore) |
| 716 | +{ |
| 717 | + struct bcma_bus *bus = mcore->core->bus; |
| 718 | + |
| 719 | + if (mcore->early_setup_done) |
| 720 | + return; |
| 721 | + |
| 722 | + bcma_chipco_serial_init(&bus->drv_cc); |
| 723 | + bcma_core_mips_flash_detect(mcore); |
| 724 | + |
| 725 | + mcore->early_setup_done = true; |
| 726 | +} |
| 727 | + |
| 728 | void bcma_core_mips_init(struct bcma_drv_mips *mcore) |
| 729 | { |
| 730 | struct bcma_bus *bus; |
| 731 | struct bcma_device *core; |
| 732 | bus = mcore->core->bus; |
| 733 | |
| 734 | + if (mcore->setup_done) |
| 735 | + return; |
| 736 | + |
| 737 | bcma_info(bus, "Initializing MIPS core...\n"); |
| 738 | |
| 739 | - if (!mcore->setup_done) |
| 740 | - mcore->assigned_irqs = 1; |
| 741 | + bcma_core_mips_early_init(mcore); |
| 742 | + |
| 743 | + mcore->assigned_irqs = 1; |
| 744 | |
| 745 | /* Assign IRQs to all cores on the bus */ |
| 746 | list_for_each_entry(core, &bus->cores, list) { |
| 747 | @@ -256,10 +275,5 @@ void bcma_core_mips_init(struct bcma_drv |
| 748 | bcma_info(bus, "IRQ reconfiguration done\n"); |
| 749 | bcma_core_mips_dump_irq(bus); |
| 750 | |
| 751 | - if (mcore->setup_done) |
| 752 | - return; |
| 753 | - |
| 754 | - bcma_chipco_serial_init(&bus->drv_cc); |
| 755 | - bcma_core_mips_flash_detect(mcore); |
| 756 | mcore->setup_done = true; |
| 757 | } |
| 758 | --- a/drivers/bcma/driver_pci.c |
| 759 | +++ b/drivers/bcma/driver_pci.c |
| 760 | @@ -51,7 +51,7 @@ static void bcma_pcie_mdio_set_phy(struc |
| 761 | v = pcicore_read32(pc, BCMA_CORE_PCI_MDIO_CONTROL); |
| 762 | if (v & BCMA_CORE_PCI_MDIOCTL_ACCESS_DONE) |
| 763 | break; |
| 764 | - msleep(1); |
| 765 | + usleep_range(1000, 2000); |
| 766 | } |
| 767 | } |
| 768 | |
| 769 | @@ -92,7 +92,7 @@ static u16 bcma_pcie_mdio_read(struct bc |
| 770 | ret = pcicore_read32(pc, BCMA_CORE_PCI_MDIO_DATA); |
| 771 | break; |
| 772 | } |
| 773 | - msleep(1); |
| 774 | + usleep_range(1000, 2000); |
| 775 | } |
| 776 | pcicore_write32(pc, BCMA_CORE_PCI_MDIO_CONTROL, 0); |
| 777 | return ret; |
| 778 | @@ -132,7 +132,7 @@ static void bcma_pcie_mdio_write(struct |
| 779 | v = pcicore_read32(pc, BCMA_CORE_PCI_MDIO_CONTROL); |
| 780 | if (v & BCMA_CORE_PCI_MDIOCTL_ACCESS_DONE) |
| 781 | break; |
| 782 | - msleep(1); |
| 783 | + usleep_range(1000, 2000); |
| 784 | } |
| 785 | pcicore_write32(pc, BCMA_CORE_PCI_MDIO_CONTROL, 0); |
| 786 | } |
| 787 | --- a/drivers/bcma/driver_pci_host.c |
| 788 | +++ b/drivers/bcma/driver_pci_host.c |
| 789 | @@ -35,11 +35,6 @@ bool __devinit bcma_core_pci_is_in_hostm |
| 790 | chipid_top != 0x5300) |
| 791 | return false; |
| 792 | |
| 793 | - if (bus->sprom.boardflags_lo & BCMA_CORE_PCI_BFL_NOPCI) { |
| 794 | - bcma_info(bus, "This PCI core is disabled and not working\n"); |
| 795 | - return false; |
| 796 | - } |
| 797 | - |
| 798 | bcma_core_enable(pc->core, 0); |
| 799 | |
| 800 | return !mips_busprobe32(tmp, pc->core->io_addr); |
| 801 | @@ -396,6 +391,11 @@ void __devinit bcma_core_pci_hostmode_in |
| 802 | |
| 803 | bcma_info(bus, "PCIEcore in host mode found\n"); |
| 804 | |
| 805 | + if (bus->sprom.boardflags_lo & BCMA_CORE_PCI_BFL_NOPCI) { |
| 806 | + bcma_info(bus, "This PCIE core is disabled and not working\n"); |
| 807 | + return; |
| 808 | + } |
| 809 | + |
| 810 | pc_host = kzalloc(sizeof(*pc_host), GFP_KERNEL); |
| 811 | if (!pc_host) { |
| 812 | bcma_err(bus, "can not allocate memory"); |
| 813 | @@ -425,9 +425,9 @@ void __devinit bcma_core_pci_hostmode_in |
| 814 | pc_host->io_resource.flags = IORESOURCE_IO | IORESOURCE_PCI_FIXED; |
| 815 | |
| 816 | /* Reset RC */ |
| 817 | - udelay(3000); |
| 818 | + usleep_range(3000, 5000); |
| 819 | pcicore_write32(pc, BCMA_CORE_PCI_CTL, BCMA_CORE_PCI_CTL_RST_OE); |
| 820 | - udelay(1000); |
| 821 | + usleep_range(1000, 2000); |
| 822 | pcicore_write32(pc, BCMA_CORE_PCI_CTL, BCMA_CORE_PCI_CTL_RST | |
| 823 | BCMA_CORE_PCI_CTL_RST_OE); |
| 824 | |
| 825 | @@ -452,6 +452,8 @@ void __devinit bcma_core_pci_hostmode_in |
| 826 | pc_host->mem_resource.start = BCMA_SOC_PCI_MEM; |
| 827 | pc_host->mem_resource.end = BCMA_SOC_PCI_MEM + |
| 828 | BCMA_SOC_PCI_MEM_SZ - 1; |
| 829 | + pc_host->io_resource.start = 0x100; |
| 830 | + pc_host->io_resource.end = 0x47F; |
| 831 | pci_membase_1G = BCMA_SOC_PCIE_DMA_H32; |
| 832 | pcicore_write32(pc, BCMA_CORE_PCI_SBTOPCI0, |
| 833 | tmp | BCMA_SOC_PCI_MEM); |
| 834 | @@ -459,6 +461,8 @@ void __devinit bcma_core_pci_hostmode_in |
| 835 | pc_host->mem_resource.start = BCMA_SOC_PCI1_MEM; |
| 836 | pc_host->mem_resource.end = BCMA_SOC_PCI1_MEM + |
| 837 | BCMA_SOC_PCI_MEM_SZ - 1; |
| 838 | + pc_host->io_resource.start = 0x480; |
| 839 | + pc_host->io_resource.end = 0x7FF; |
| 840 | pci_membase_1G = BCMA_SOC_PCIE1_DMA_H32; |
| 841 | pc_host->host_cfg_addr = BCMA_SOC_PCI1_CFG; |
| 842 | pcicore_write32(pc, BCMA_CORE_PCI_SBTOPCI0, |
| 843 | @@ -481,7 +485,7 @@ void __devinit bcma_core_pci_hostmode_in |
| 844 | * before issuing configuration requests to PCI Express |
| 845 | * devices. |
| 846 | */ |
| 847 | - udelay(100000); |
| 848 | + msleep(100); |
| 849 | |
| 850 | bcma_core_pci_enable_crs(pc); |
| 851 | |
| 852 | @@ -501,7 +505,7 @@ void __devinit bcma_core_pci_hostmode_in |
| 853 | set_io_port_base(pc_host->pci_controller.io_map_base); |
| 854 | /* Give some time to the PCI controller to configure itself with the new |
| 855 | * values. Not waiting at this point causes crashes of the machine. */ |
| 856 | - mdelay(10); |
| 857 | + usleep_range(10000, 15000); |
| 858 | register_pci_controller(&pc_host->pci_controller); |
| 859 | return; |
| 860 | } |
| 861 | @@ -534,7 +538,7 @@ DECLARE_PCI_FIXUP_EARLY(PCI_ANY_ID, PCI_ |
| 862 | static void bcma_core_pci_fixup_addresses(struct pci_dev *dev) |
| 863 | { |
| 864 | struct resource *res; |
| 865 | - int pos; |
| 866 | + int pos, err; |
| 867 | |
| 868 | if (dev->bus->ops->read != bcma_core_pci_hostmode_read_config) { |
| 869 | /* This is not a device on the PCI-core bridge. */ |
| 870 | @@ -547,8 +551,12 @@ static void bcma_core_pci_fixup_addresse |
| 871 | |
| 872 | for (pos = 0; pos < 6; pos++) { |
| 873 | res = &dev->resource[pos]; |
| 874 | - if (res->flags & (IORESOURCE_IO | IORESOURCE_MEM)) |
| 875 | - pci_assign_resource(dev, pos); |
| 876 | + if (res->flags & (IORESOURCE_IO | IORESOURCE_MEM)) { |
| 877 | + err = pci_assign_resource(dev, pos); |
| 878 | + if (err) |
| 879 | + pr_err("PCI: Problem fixing up the addresses on %s\n", |
| 880 | + pci_name(dev)); |
| 881 | + } |
| 882 | } |
| 883 | } |
| 884 | DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, bcma_core_pci_fixup_addresses); |
| 885 | --- a/drivers/bcma/host_pci.c |
| 886 | +++ b/drivers/bcma/host_pci.c |
| 887 | @@ -77,8 +77,8 @@ static void bcma_host_pci_write32(struct |
| 888 | } |
| 889 | |
| 890 | #ifdef CONFIG_BCMA_BLOCKIO |
| 891 | -void bcma_host_pci_block_read(struct bcma_device *core, void *buffer, |
| 892 | - size_t count, u16 offset, u8 reg_width) |
| 893 | +static void bcma_host_pci_block_read(struct bcma_device *core, void *buffer, |
| 894 | + size_t count, u16 offset, u8 reg_width) |
| 895 | { |
| 896 | void __iomem *addr = core->bus->mmio + offset; |
| 897 | if (core->bus->mapped_core != core) |
| 898 | @@ -100,8 +100,9 @@ void bcma_host_pci_block_read(struct bcm |
| 899 | } |
| 900 | } |
| 901 | |
| 902 | -void bcma_host_pci_block_write(struct bcma_device *core, const void *buffer, |
| 903 | - size_t count, u16 offset, u8 reg_width) |
| 904 | +static void bcma_host_pci_block_write(struct bcma_device *core, |
| 905 | + const void *buffer, size_t count, |
| 906 | + u16 offset, u8 reg_width) |
| 907 | { |
| 908 | void __iomem *addr = core->bus->mmio + offset; |
| 909 | if (core->bus->mapped_core != core) |
| 910 | @@ -139,7 +140,7 @@ static void bcma_host_pci_awrite32(struc |
| 911 | iowrite32(value, core->bus->mmio + (1 * BCMA_CORE_SIZE) + offset); |
| 912 | } |
| 913 | |
| 914 | -const struct bcma_host_ops bcma_host_pci_ops = { |
| 915 | +static const struct bcma_host_ops bcma_host_pci_ops = { |
| 916 | .read8 = bcma_host_pci_read8, |
| 917 | .read16 = bcma_host_pci_read16, |
| 918 | .read32 = bcma_host_pci_read32, |
| 919 | @@ -237,7 +238,7 @@ static void __devexit bcma_host_pci_remo |
| 920 | pci_set_drvdata(dev, NULL); |
| 921 | } |
| 922 | |
| 923 | -#ifdef CONFIG_PM |
| 924 | +#ifdef CONFIG_PM_SLEEP |
| 925 | static int bcma_host_pci_suspend(struct device *dev) |
| 926 | { |
| 927 | struct pci_dev *pdev = to_pci_dev(dev); |
| 928 | @@ -260,11 +261,11 @@ static SIMPLE_DEV_PM_OPS(bcma_pm_ops, bc |
| 929 | bcma_host_pci_resume); |
| 930 | #define BCMA_PM_OPS (&bcma_pm_ops) |
| 931 | |
| 932 | -#else /* CONFIG_PM */ |
| 933 | +#else /* CONFIG_PM_SLEEP */ |
| 934 | |
| 935 | #define BCMA_PM_OPS NULL |
| 936 | |
| 937 | -#endif /* CONFIG_PM */ |
| 938 | +#endif /* CONFIG_PM_SLEEP */ |
| 939 | |
| 940 | static DEFINE_PCI_DEVICE_TABLE(bcma_pci_bridge_tbl) = { |
| 941 | { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x0576) }, |
| 942 | @@ -272,6 +273,7 @@ static DEFINE_PCI_DEVICE_TABLE(bcma_pci_ |
| 943 | { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4331) }, |
| 944 | { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4353) }, |
| 945 | { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4357) }, |
| 946 | + { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4358) }, |
| 947 | { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4359) }, |
| 948 | { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4727) }, |
| 949 | { 0, }, |
| 950 | --- a/drivers/bcma/host_soc.c |
| 951 | +++ b/drivers/bcma/host_soc.c |
| 952 | @@ -143,7 +143,7 @@ static void bcma_host_soc_awrite32(struc |
| 953 | writel(value, core->io_wrap + offset); |
| 954 | } |
| 955 | |
| 956 | -const struct bcma_host_ops bcma_host_soc_ops = { |
| 957 | +static const struct bcma_host_ops bcma_host_soc_ops = { |
| 958 | .read8 = bcma_host_soc_read8, |
| 959 | .read16 = bcma_host_soc_read16, |
| 960 | .read32 = bcma_host_soc_read32, |
| 961 | --- a/drivers/bcma/main.c |
| 962 | +++ b/drivers/bcma/main.c |
| 963 | @@ -7,6 +7,7 @@ |
| 964 | |
| 965 | #include "bcma_private.h" |
| 966 | #include <linux/module.h> |
| 967 | +#include <linux/platform_device.h> |
| 968 | #include <linux/bcma/bcma.h> |
| 969 | #include <linux/slab.h> |
| 970 | |
| 971 | @@ -80,6 +81,18 @@ struct bcma_device *bcma_find_core(struc |
| 972 | } |
| 973 | EXPORT_SYMBOL_GPL(bcma_find_core); |
| 974 | |
| 975 | +static struct bcma_device *bcma_find_core_unit(struct bcma_bus *bus, u16 coreid, |
| 976 | + u8 unit) |
| 977 | +{ |
| 978 | + struct bcma_device *core; |
| 979 | + |
| 980 | + list_for_each_entry(core, &bus->cores, list) { |
| 981 | + if (core->id.id == coreid && core->core_unit == unit) |
| 982 | + return core; |
| 983 | + } |
| 984 | + return NULL; |
| 985 | +} |
| 986 | + |
| 987 | static void bcma_release_core_dev(struct device *dev) |
| 988 | { |
| 989 | struct bcma_device *core = container_of(dev, struct bcma_device, dev); |
| 990 | @@ -136,6 +149,28 @@ static int bcma_register_cores(struct bc |
| 991 | dev_id++; |
| 992 | } |
| 993 | |
| 994 | +#ifdef CONFIG_BCMA_SFLASH |
| 995 | + if (bus->drv_cc.sflash.present) { |
| 996 | + err = platform_device_register(&bcma_sflash_dev); |
| 997 | + if (err) |
| 998 | + bcma_err(bus, "Error registering serial flash\n"); |
| 999 | + } |
| 1000 | +#endif |
| 1001 | + |
| 1002 | +#ifdef CONFIG_BCMA_NFLASH |
| 1003 | + if (bus->drv_cc.nflash.present) { |
| 1004 | + err = platform_device_register(&bcma_nflash_dev); |
| 1005 | + if (err) |
| 1006 | + bcma_err(bus, "Error registering NAND flash\n"); |
| 1007 | + } |
| 1008 | +#endif |
| 1009 | + |
| 1010 | + if (bus->hosttype == BCMA_HOSTTYPE_SOC) { |
| 1011 | + err = bcma_chipco_watchdog_register(&bus->drv_cc); |
| 1012 | + if (err) |
| 1013 | + bcma_err(bus, "Error registering watchdog driver\n"); |
| 1014 | + } |
| 1015 | + |
| 1016 | return 0; |
| 1017 | } |
| 1018 | |
| 1019 | @@ -148,6 +183,8 @@ static void bcma_unregister_cores(struct |
| 1020 | if (core->dev_registered) |
| 1021 | device_unregister(&core->dev); |
| 1022 | } |
| 1023 | + if (bus->hosttype == BCMA_HOSTTYPE_SOC) |
| 1024 | + platform_device_unregister(bus->drv_cc.watchdog); |
| 1025 | } |
| 1026 | |
| 1027 | int __devinit bcma_bus_register(struct bcma_bus *bus) |
| 1028 | @@ -166,6 +203,20 @@ int __devinit bcma_bus_register(struct b |
| 1029 | return -1; |
| 1030 | } |
| 1031 | |
| 1032 | + /* Early init CC core */ |
| 1033 | + core = bcma_find_core(bus, bcma_cc_core_id(bus)); |
| 1034 | + if (core) { |
| 1035 | + bus->drv_cc.core = core; |
| 1036 | + bcma_core_chipcommon_early_init(&bus->drv_cc); |
| 1037 | + } |
| 1038 | + |
| 1039 | + /* Try to get SPROM */ |
| 1040 | + err = bcma_sprom_get(bus); |
| 1041 | + if (err == -ENOENT) { |
| 1042 | + bcma_err(bus, "No SPROM available\n"); |
| 1043 | + } else if (err) |
| 1044 | + bcma_err(bus, "Failed to get SPROM: %d\n", err); |
| 1045 | + |
| 1046 | /* Init CC core */ |
| 1047 | core = bcma_find_core(bus, bcma_cc_core_id(bus)); |
| 1048 | if (core) { |
| 1049 | @@ -181,10 +232,17 @@ int __devinit bcma_bus_register(struct b |
| 1050 | } |
| 1051 | |
| 1052 | /* Init PCIE core */ |
| 1053 | - core = bcma_find_core(bus, BCMA_CORE_PCIE); |
| 1054 | + core = bcma_find_core_unit(bus, BCMA_CORE_PCIE, 0); |
| 1055 | + if (core) { |
| 1056 | + bus->drv_pci[0].core = core; |
| 1057 | + bcma_core_pci_init(&bus->drv_pci[0]); |
| 1058 | + } |
| 1059 | + |
| 1060 | + /* Init PCIE core */ |
| 1061 | + core = bcma_find_core_unit(bus, BCMA_CORE_PCIE, 1); |
| 1062 | if (core) { |
| 1063 | - bus->drv_pci.core = core; |
| 1064 | - bcma_core_pci_init(&bus->drv_pci); |
| 1065 | + bus->drv_pci[1].core = core; |
| 1066 | + bcma_core_pci_init(&bus->drv_pci[1]); |
| 1067 | } |
| 1068 | |
| 1069 | /* Init GBIT MAC COMMON core */ |
| 1070 | @@ -194,13 +252,6 @@ int __devinit bcma_bus_register(struct b |
| 1071 | bcma_core_gmac_cmn_init(&bus->drv_gmac_cmn); |
| 1072 | } |
| 1073 | |
| 1074 | - /* Try to get SPROM */ |
| 1075 | - err = bcma_sprom_get(bus); |
| 1076 | - if (err == -ENOENT) { |
| 1077 | - bcma_err(bus, "No SPROM available\n"); |
| 1078 | - } else if (err) |
| 1079 | - bcma_err(bus, "Failed to get SPROM: %d\n", err); |
| 1080 | - |
| 1081 | /* Register found cores */ |
| 1082 | bcma_register_cores(bus); |
| 1083 | |
| 1084 | @@ -211,7 +262,17 @@ int __devinit bcma_bus_register(struct b |
| 1085 | |
| 1086 | void bcma_bus_unregister(struct bcma_bus *bus) |
| 1087 | { |
| 1088 | + struct bcma_device *cores[3]; |
| 1089 | + |
| 1090 | + cores[0] = bcma_find_core(bus, BCMA_CORE_MIPS_74K); |
| 1091 | + cores[1] = bcma_find_core(bus, BCMA_CORE_PCIE); |
| 1092 | + cores[2] = bcma_find_core(bus, BCMA_CORE_4706_MAC_GBIT_COMMON); |
| 1093 | + |
| 1094 | bcma_unregister_cores(bus); |
| 1095 | + |
| 1096 | + kfree(cores[2]); |
| 1097 | + kfree(cores[1]); |
| 1098 | + kfree(cores[0]); |
| 1099 | } |
| 1100 | |
| 1101 | int __init bcma_bus_early_register(struct bcma_bus *bus, |
| 1102 | @@ -248,18 +309,18 @@ int __init bcma_bus_early_register(struc |
| 1103 | return -1; |
| 1104 | } |
| 1105 | |
| 1106 | - /* Init CC core */ |
| 1107 | + /* Early init CC core */ |
| 1108 | core = bcma_find_core(bus, bcma_cc_core_id(bus)); |
| 1109 | if (core) { |
| 1110 | bus->drv_cc.core = core; |
| 1111 | - bcma_core_chipcommon_init(&bus->drv_cc); |
| 1112 | + bcma_core_chipcommon_early_init(&bus->drv_cc); |
| 1113 | } |
| 1114 | |
| 1115 | - /* Init MIPS core */ |
| 1116 | + /* Early init MIPS core */ |
| 1117 | core = bcma_find_core(bus, BCMA_CORE_MIPS_74K); |
| 1118 | if (core) { |
| 1119 | bus->drv_mips.core = core; |
| 1120 | - bcma_core_mips_init(&bus->drv_mips); |
| 1121 | + bcma_core_mips_early_init(&bus->drv_mips); |
| 1122 | } |
| 1123 | |
| 1124 | bcma_info(bus, "Early bus registered\n"); |
| 1125 | --- a/drivers/bcma/sprom.c |
| 1126 | +++ b/drivers/bcma/sprom.c |
| 1127 | @@ -507,7 +507,9 @@ static bool bcma_sprom_onchip_available( |
| 1128 | /* for these chips OTP is always available */ |
| 1129 | present = true; |
| 1130 | break; |
| 1131 | + case BCMA_CHIP_ID_BCM43227: |
| 1132 | case BCMA_CHIP_ID_BCM43228: |
| 1133 | + case BCMA_CHIP_ID_BCM43428: |
| 1134 | present = chip_status & BCMA_CC_CHIPST_43228_OTP_PRESENT; |
| 1135 | break; |
| 1136 | default: |
| 1137 | @@ -593,8 +595,11 @@ int bcma_sprom_get(struct bcma_bus *bus) |
| 1138 | bcma_chipco_bcm4331_ext_pa_lines_ctl(&bus->drv_cc, true); |
| 1139 | |
| 1140 | err = bcma_sprom_valid(sprom); |
| 1141 | - if (err) |
| 1142 | + if (err) { |
| 1143 | + bcma_warn(bus, "invalid sprom read from the PCIe card, try to use fallback sprom\n"); |
| 1144 | + err = bcma_fill_sprom_with_fallback(bus, &bus->sprom); |
| 1145 | goto out; |
| 1146 | + } |
| 1147 | |
| 1148 | bcma_sprom_extract_r8(bus, sprom); |
| 1149 | |
| 1150 | --- a/include/linux/bcma/bcma.h |
| 1151 | +++ b/include/linux/bcma/bcma.h |
| 1152 | @@ -10,7 +10,7 @@ |
| 1153 | #include <linux/bcma/bcma_driver_gmac_cmn.h> |
| 1154 | #include <linux/ssb/ssb.h> /* SPROM sharing */ |
| 1155 | |
| 1156 | -#include "bcma_regs.h" |
| 1157 | +#include <linux/bcma/bcma_regs.h> |
| 1158 | |
| 1159 | struct bcma_device; |
| 1160 | struct bcma_bus; |
| 1161 | @@ -157,6 +157,7 @@ struct bcma_host_ops { |
| 1162 | |
| 1163 | /* Chip IDs of SoCs */ |
| 1164 | #define BCMA_CHIP_ID_BCM4706 0x5300 |
| 1165 | +#define BCMA_PKG_ID_BCM4706L 1 |
| 1166 | #define BCMA_CHIP_ID_BCM4716 0x4716 |
| 1167 | #define BCMA_PKG_ID_BCM4716 8 |
| 1168 | #define BCMA_PKG_ID_BCM4717 9 |
| 1169 | @@ -166,7 +167,11 @@ struct bcma_host_ops { |
| 1170 | #define BCMA_CHIP_ID_BCM4749 0x4749 |
| 1171 | #define BCMA_CHIP_ID_BCM5356 0x5356 |
| 1172 | #define BCMA_CHIP_ID_BCM5357 0x5357 |
| 1173 | +#define BCMA_PKG_ID_BCM5358 9 |
| 1174 | +#define BCMA_PKG_ID_BCM47186 10 |
| 1175 | +#define BCMA_PKG_ID_BCM5357 11 |
| 1176 | #define BCMA_CHIP_ID_BCM53572 53572 |
| 1177 | +#define BCMA_PKG_ID_BCM47188 9 |
| 1178 | |
| 1179 | struct bcma_device { |
| 1180 | struct bcma_bus *bus; |
| 1181 | @@ -251,7 +256,7 @@ struct bcma_bus { |
| 1182 | u8 num; |
| 1183 | |
| 1184 | struct bcma_drv_cc drv_cc; |
| 1185 | - struct bcma_drv_pci drv_pci; |
| 1186 | + struct bcma_drv_pci drv_pci[2]; |
| 1187 | struct bcma_drv_mips drv_mips; |
| 1188 | struct bcma_drv_gmac_cmn drv_gmac_cmn; |
| 1189 | |
| 1190 | --- a/include/linux/bcma/bcma_driver_chipcommon.h |
| 1191 | +++ b/include/linux/bcma/bcma_driver_chipcommon.h |
| 1192 | @@ -1,6 +1,8 @@ |
| 1193 | #ifndef LINUX_BCMA_DRIVER_CC_H_ |
| 1194 | #define LINUX_BCMA_DRIVER_CC_H_ |
| 1195 | |
| 1196 | +#include <linux/platform_device.h> |
| 1197 | + |
| 1198 | /** ChipCommon core registers. **/ |
| 1199 | #define BCMA_CC_ID 0x0000 |
| 1200 | #define BCMA_CC_ID_ID 0x0000FFFF |
| 1201 | @@ -100,6 +102,7 @@ |
| 1202 | #define BCMA_CC_CHIPST_4706_SFLASH_TYPE BIT(2) /* 0: 8b-p/ST-s flash, 1: 16b-p/Atmal-s flash */ |
| 1203 | #define BCMA_CC_CHIPST_4706_MIPS_BENDIAN BIT(3) /* 0: little, 1: big endian */ |
| 1204 | #define BCMA_CC_CHIPST_4706_PCIE1_DISABLE BIT(5) /* PCIE1 enable strap pin */ |
| 1205 | +#define BCMA_CC_CHIPST_5357_NAND_BOOT BIT(4) /* NAND boot, valid for CC rev 38 and/or BCM5357 */ |
| 1206 | #define BCMA_CC_JCMD 0x0030 /* Rev >= 10 only */ |
| 1207 | #define BCMA_CC_JCMD_START 0x80000000 |
| 1208 | #define BCMA_CC_JCMD_BUSY 0x80000000 |
| 1209 | @@ -266,6 +269,29 @@ |
| 1210 | #define BCMA_CC_SROM_CONTROL_SIZE_16K 0x00000004 |
| 1211 | #define BCMA_CC_SROM_CONTROL_SIZE_SHIFT 1 |
| 1212 | #define BCMA_CC_SROM_CONTROL_PRESENT 0x00000001 |
| 1213 | +/* Block 0x140 - 0x190 registers are chipset specific */ |
| 1214 | +#define BCMA_CC_4706_FLASHSCFG 0x18C /* Flash struct configuration */ |
| 1215 | +#define BCMA_CC_4706_FLASHSCFG_MASK 0x000000ff |
| 1216 | +#define BCMA_CC_4706_FLASHSCFG_SF1 0x00000001 /* 2nd serial flash present */ |
| 1217 | +#define BCMA_CC_4706_FLASHSCFG_PF1 0x00000002 /* 2nd parallel flash present */ |
| 1218 | +#define BCMA_CC_4706_FLASHSCFG_SF1_TYPE 0x00000004 /* 2nd serial flash type : 0 : ST, 1 : Atmel */ |
| 1219 | +#define BCMA_CC_4706_FLASHSCFG_NF1 0x00000008 /* 2nd NAND flash present */ |
| 1220 | +#define BCMA_CC_4706_FLASHSCFG_1ST_MADDR_SEG_MASK 0x000000f0 |
| 1221 | +#define BCMA_CC_4706_FLASHSCFG_1ST_MADDR_SEG_4MB 0x00000010 /* 4MB */ |
| 1222 | +#define BCMA_CC_4706_FLASHSCFG_1ST_MADDR_SEG_8MB 0x00000020 /* 8MB */ |
| 1223 | +#define BCMA_CC_4706_FLASHSCFG_1ST_MADDR_SEG_16MB 0x00000030 /* 16MB */ |
| 1224 | +#define BCMA_CC_4706_FLASHSCFG_1ST_MADDR_SEG_32MB 0x00000040 /* 32MB */ |
| 1225 | +#define BCMA_CC_4706_FLASHSCFG_1ST_MADDR_SEG_64MB 0x00000050 /* 64MB */ |
| 1226 | +#define BCMA_CC_4706_FLASHSCFG_1ST_MADDR_SEG_128MB 0x00000060 /* 128MB */ |
| 1227 | +#define BCMA_CC_4706_FLASHSCFG_1ST_MADDR_SEG_256MB 0x00000070 /* 256MB */ |
| 1228 | +/* NAND flash registers for BCM4706 (corerev = 31) */ |
| 1229 | +#define BCMA_CC_NFLASH_CTL 0x01A0 |
| 1230 | +#define BCMA_CC_NFLASH_CTL_ERR 0x08000000 |
| 1231 | +#define BCMA_CC_NFLASH_CONF 0x01A4 |
| 1232 | +#define BCMA_CC_NFLASH_COL_ADDR 0x01A8 |
| 1233 | +#define BCMA_CC_NFLASH_ROW_ADDR 0x01AC |
| 1234 | +#define BCMA_CC_NFLASH_DATA 0x01B0 |
| 1235 | +#define BCMA_CC_NFLASH_WAITCNT0 0x01B4 |
| 1236 | /* 0x1E0 is defined as shared BCMA_CLKCTLST */ |
| 1237 | #define BCMA_CC_HW_WORKAROUND 0x01E4 /* Hardware workaround (rev >= 20) */ |
| 1238 | #define BCMA_CC_UART0_DATA 0x0300 |
| 1239 | @@ -325,6 +351,60 @@ |
| 1240 | #define BCMA_CC_PLLCTL_ADDR 0x0660 |
| 1241 | #define BCMA_CC_PLLCTL_DATA 0x0664 |
| 1242 | #define BCMA_CC_SPROM 0x0800 /* SPROM beginning */ |
| 1243 | +/* NAND flash MLC controller registers (corerev >= 38) */ |
| 1244 | +#define BCMA_CC_NAND_REVISION 0x0C00 |
| 1245 | +#define BCMA_CC_NAND_CMD_START 0x0C04 |
| 1246 | +#define BCMA_CC_NAND_CMD_ADDR_X 0x0C08 |
| 1247 | +#define BCMA_CC_NAND_CMD_ADDR 0x0C0C |
| 1248 | +#define BCMA_CC_NAND_CMD_END_ADDR 0x0C10 |
| 1249 | +#define BCMA_CC_NAND_CS_NAND_SELECT 0x0C14 |
| 1250 | +#define BCMA_CC_NAND_CS_NAND_XOR 0x0C18 |
| 1251 | +#define BCMA_CC_NAND_SPARE_RD0 0x0C20 |
| 1252 | +#define BCMA_CC_NAND_SPARE_RD4 0x0C24 |
| 1253 | +#define BCMA_CC_NAND_SPARE_RD8 0x0C28 |
| 1254 | +#define BCMA_CC_NAND_SPARE_RD12 0x0C2C |
| 1255 | +#define BCMA_CC_NAND_SPARE_WR0 0x0C30 |
| 1256 | +#define BCMA_CC_NAND_SPARE_WR4 0x0C34 |
| 1257 | +#define BCMA_CC_NAND_SPARE_WR8 0x0C38 |
| 1258 | +#define BCMA_CC_NAND_SPARE_WR12 0x0C3C |
| 1259 | +#define BCMA_CC_NAND_ACC_CONTROL 0x0C40 |
| 1260 | +#define BCMA_CC_NAND_CONFIG 0x0C48 |
| 1261 | +#define BCMA_CC_NAND_TIMING_1 0x0C50 |
| 1262 | +#define BCMA_CC_NAND_TIMING_2 0x0C54 |
| 1263 | +#define BCMA_CC_NAND_SEMAPHORE 0x0C58 |
| 1264 | +#define BCMA_CC_NAND_DEVID 0x0C60 |
| 1265 | +#define BCMA_CC_NAND_DEVID_X 0x0C64 |
| 1266 | +#define BCMA_CC_NAND_BLOCK_LOCK_STATUS 0x0C68 |
| 1267 | +#define BCMA_CC_NAND_INTFC_STATUS 0x0C6C |
| 1268 | +#define BCMA_CC_NAND_ECC_CORR_ADDR_X 0x0C70 |
| 1269 | +#define BCMA_CC_NAND_ECC_CORR_ADDR 0x0C74 |
| 1270 | +#define BCMA_CC_NAND_ECC_UNC_ADDR_X 0x0C78 |
| 1271 | +#define BCMA_CC_NAND_ECC_UNC_ADDR 0x0C7C |
| 1272 | +#define BCMA_CC_NAND_READ_ERROR_COUNT 0x0C80 |
| 1273 | +#define BCMA_CC_NAND_CORR_STAT_THRESHOLD 0x0C84 |
| 1274 | +#define BCMA_CC_NAND_READ_ADDR_X 0x0C90 |
| 1275 | +#define BCMA_CC_NAND_READ_ADDR 0x0C94 |
| 1276 | +#define BCMA_CC_NAND_PAGE_PROGRAM_ADDR_X 0x0C98 |
| 1277 | +#define BCMA_CC_NAND_PAGE_PROGRAM_ADDR 0x0C9C |
| 1278 | +#define BCMA_CC_NAND_COPY_BACK_ADDR_X 0x0CA0 |
| 1279 | +#define BCMA_CC_NAND_COPY_BACK_ADDR 0x0CA4 |
| 1280 | +#define BCMA_CC_NAND_BLOCK_ERASE_ADDR_X 0x0CA8 |
| 1281 | +#define BCMA_CC_NAND_BLOCK_ERASE_ADDR 0x0CAC |
| 1282 | +#define BCMA_CC_NAND_INV_READ_ADDR_X 0x0CB0 |
| 1283 | +#define BCMA_CC_NAND_INV_READ_ADDR 0x0CB4 |
| 1284 | +#define BCMA_CC_NAND_BLK_WR_PROTECT 0x0CC0 |
| 1285 | +#define BCMA_CC_NAND_ACC_CONTROL_CS1 0x0CD0 |
| 1286 | +#define BCMA_CC_NAND_CONFIG_CS1 0x0CD4 |
| 1287 | +#define BCMA_CC_NAND_TIMING_1_CS1 0x0CD8 |
| 1288 | +#define BCMA_CC_NAND_TIMING_2_CS1 0x0CDC |
| 1289 | +#define BCMA_CC_NAND_SPARE_RD16 0x0D30 |
| 1290 | +#define BCMA_CC_NAND_SPARE_RD20 0x0D34 |
| 1291 | +#define BCMA_CC_NAND_SPARE_RD24 0x0D38 |
| 1292 | +#define BCMA_CC_NAND_SPARE_RD28 0x0D3C |
| 1293 | +#define BCMA_CC_NAND_CACHE_ADDR 0x0D40 |
| 1294 | +#define BCMA_CC_NAND_CACHE_DATA 0x0D44 |
| 1295 | +#define BCMA_CC_NAND_CTRL_CONFIG 0x0D48 |
| 1296 | +#define BCMA_CC_NAND_CTRL_STATUS 0x0D4C |
| 1297 | |
| 1298 | /* Divider allocation in 4716/47162/5356 */ |
| 1299 | #define BCMA_CC_PMU5_MAINPLL_CPU 1 |
| 1300 | @@ -415,6 +495,13 @@ |
| 1301 | /* 4313 Chip specific ChipControl register bits */ |
| 1302 | #define BCMA_CCTRL_4313_12MA_LED_DRIVE 0x00000007 /* 12 mA drive strengh for later 4313 */ |
| 1303 | |
| 1304 | +/* BCM5357 ChipControl register bits */ |
| 1305 | +#define BCMA_CHIPCTL_5357_EXTPA BIT(14) |
| 1306 | +#define BCMA_CHIPCTL_5357_ANT_MUX_2O3 BIT(15) |
| 1307 | +#define BCMA_CHIPCTL_5357_NFLASH BIT(16) |
| 1308 | +#define BCMA_CHIPCTL_5357_I2S_PINS_ENABLE BIT(18) |
| 1309 | +#define BCMA_CHIPCTL_5357_I2CSPI_PINS_ENABLE BIT(19) |
| 1310 | + |
| 1311 | /* Data for the PMU, if available. |
| 1312 | * Check availability with ((struct bcma_chipcommon)->capabilities & BCMA_CC_CAP_PMU) |
| 1313 | */ |
| 1314 | @@ -425,11 +512,35 @@ struct bcma_chipcommon_pmu { |
| 1315 | |
| 1316 | #ifdef CONFIG_BCMA_DRIVER_MIPS |
| 1317 | struct bcma_pflash { |
| 1318 | + bool present; |
| 1319 | u8 buswidth; |
| 1320 | u32 window; |
| 1321 | u32 window_size; |
| 1322 | }; |
| 1323 | |
| 1324 | +#ifdef CONFIG_BCMA_SFLASH |
| 1325 | +struct bcma_sflash { |
| 1326 | + bool present; |
| 1327 | + u32 window; |
| 1328 | + u32 blocksize; |
| 1329 | + u16 numblocks; |
| 1330 | + u32 size; |
| 1331 | + |
| 1332 | + struct mtd_info *mtd; |
| 1333 | +}; |
| 1334 | +#endif |
| 1335 | + |
| 1336 | +#ifdef CONFIG_BCMA_NFLASH |
| 1337 | +struct mtd_info; |
| 1338 | + |
| 1339 | +struct bcma_nflash { |
| 1340 | + bool present; |
| 1341 | + bool boot; /* This is the flash the SoC boots from */ |
| 1342 | + |
| 1343 | + struct mtd_info *mtd; |
| 1344 | +}; |
| 1345 | +#endif |
| 1346 | + |
| 1347 | struct bcma_serial_port { |
| 1348 | void *regs; |
| 1349 | unsigned long clockspeed; |
| 1350 | @@ -445,15 +556,24 @@ struct bcma_drv_cc { |
| 1351 | u32 capabilities; |
| 1352 | u32 capabilities_ext; |
| 1353 | u8 setup_done:1; |
| 1354 | + u8 early_setup_done:1; |
| 1355 | /* Fast Powerup Delay constant */ |
| 1356 | u16 fast_pwrup_delay; |
| 1357 | struct bcma_chipcommon_pmu pmu; |
| 1358 | #ifdef CONFIG_BCMA_DRIVER_MIPS |
| 1359 | struct bcma_pflash pflash; |
| 1360 | +#ifdef CONFIG_BCMA_SFLASH |
| 1361 | + struct bcma_sflash sflash; |
| 1362 | +#endif |
| 1363 | +#ifdef CONFIG_BCMA_NFLASH |
| 1364 | + struct bcma_nflash nflash; |
| 1365 | +#endif |
| 1366 | |
| 1367 | int nr_serial_ports; |
| 1368 | struct bcma_serial_port serial_ports[4]; |
| 1369 | #endif /* CONFIG_BCMA_DRIVER_MIPS */ |
| 1370 | + u32 ticks_per_ms; |
| 1371 | + struct platform_device *watchdog; |
| 1372 | }; |
| 1373 | |
| 1374 | /* Register access */ |
| 1375 | @@ -470,14 +590,14 @@ struct bcma_drv_cc { |
| 1376 | bcma_cc_write32(cc, offset, (bcma_cc_read32(cc, offset) & (mask)) | (set)) |
| 1377 | |
| 1378 | extern void bcma_core_chipcommon_init(struct bcma_drv_cc *cc); |
| 1379 | +extern void bcma_core_chipcommon_early_init(struct bcma_drv_cc *cc); |
| 1380 | |
| 1381 | extern void bcma_chipco_suspend(struct bcma_drv_cc *cc); |
| 1382 | extern void bcma_chipco_resume(struct bcma_drv_cc *cc); |
| 1383 | |
| 1384 | void bcma_chipco_bcm4331_ext_pa_lines_ctl(struct bcma_drv_cc *cc, bool enable); |
| 1385 | |
| 1386 | -extern void bcma_chipco_watchdog_timer_set(struct bcma_drv_cc *cc, |
| 1387 | - u32 ticks); |
| 1388 | +extern u32 bcma_chipco_watchdog_timer_set(struct bcma_drv_cc *cc, u32 ticks); |
| 1389 | |
| 1390 | void bcma_chipco_irq_mask(struct bcma_drv_cc *cc, u32 mask, u32 value); |
| 1391 | |
| 1392 | @@ -493,6 +613,7 @@ u32 bcma_chipco_gpio_polarity(struct bcm |
| 1393 | |
| 1394 | /* PMU support */ |
| 1395 | extern void bcma_pmu_init(struct bcma_drv_cc *cc); |
| 1396 | +extern void bcma_pmu_early_init(struct bcma_drv_cc *cc); |
| 1397 | |
| 1398 | extern void bcma_chipco_pll_write(struct bcma_drv_cc *cc, u32 offset, |
| 1399 | u32 value); |
| 1400 | --- a/include/linux/bcma/bcma_driver_mips.h |
| 1401 | +++ b/include/linux/bcma/bcma_driver_mips.h |
| 1402 | @@ -35,13 +35,16 @@ struct bcma_device; |
| 1403 | struct bcma_drv_mips { |
| 1404 | struct bcma_device *core; |
| 1405 | u8 setup_done:1; |
| 1406 | + u8 early_setup_done:1; |
| 1407 | unsigned int assigned_irqs; |
| 1408 | }; |
| 1409 | |
| 1410 | #ifdef CONFIG_BCMA_DRIVER_MIPS |
| 1411 | extern void bcma_core_mips_init(struct bcma_drv_mips *mcore); |
| 1412 | +extern void bcma_core_mips_early_init(struct bcma_drv_mips *mcore); |
| 1413 | #else |
| 1414 | static inline void bcma_core_mips_init(struct bcma_drv_mips *mcore) { } |
| 1415 | +static inline void bcma_core_mips_early_init(struct bcma_drv_mips *mcore) { } |
| 1416 | #endif |
| 1417 | |
| 1418 | extern u32 bcma_cpu_clock(struct bcma_drv_mips *mcore); |
| 1419 | --- a/include/linux/bcma/bcma_regs.h |
| 1420 | +++ b/include/linux/bcma/bcma_regs.h |
| 1421 | @@ -11,11 +11,13 @@ |
| 1422 | #define BCMA_CLKCTLST_HAVEHTREQ 0x00000010 /* HT available request */ |
| 1423 | #define BCMA_CLKCTLST_HWCROFF 0x00000020 /* Force HW clock request off */ |
| 1424 | #define BCMA_CLKCTLST_EXTRESREQ 0x00000700 /* Mask of external resource requests */ |
| 1425 | +#define BCMA_CLKCTLST_EXTRESREQ_SHIFT 8 |
| 1426 | #define BCMA_CLKCTLST_HAVEALP 0x00010000 /* ALP available */ |
| 1427 | #define BCMA_CLKCTLST_HAVEHT 0x00020000 /* HT available */ |
| 1428 | #define BCMA_CLKCTLST_BP_ON_ALP 0x00040000 /* RO: running on ALP clock */ |
| 1429 | #define BCMA_CLKCTLST_BP_ON_HT 0x00080000 /* RO: running on HT clock */ |
| 1430 | #define BCMA_CLKCTLST_EXTRESST 0x07000000 /* Mask of external resource status */ |
| 1431 | +#define BCMA_CLKCTLST_EXTRESST_SHIFT 24 |
| 1432 | /* Is there any BCM4328 on BCMA bus? */ |
| 1433 | #define BCMA_CLKCTLST_4328A0_HAVEHT 0x00010000 /* 4328a0 has reversed bits */ |
| 1434 | #define BCMA_CLKCTLST_4328A0_HAVEALP 0x00020000 /* 4328a0 has reversed bits */ |
| 1435 | @@ -83,4 +85,9 @@ |
| 1436 | * (2 ZettaBytes), high 32 bits |
| 1437 | */ |
| 1438 | |
| 1439 | +#define BCMA_SOC_FLASH1 0x1fc00000 /* MIPS Flash Region 1 */ |
| 1440 | +#define BCMA_SOC_FLASH1_SZ 0x00400000 /* MIPS Size of Flash Region 1 */ |
| 1441 | +#define BCMA_SOC_FLASH2 0x1c000000 /* Flash Region 2 (region 1 shadowed here) */ |
| 1442 | +#define BCMA_SOC_FLASH2_SZ 0x02000000 /* Size of Flash Region 2 */ |
| 1443 | + |
| 1444 | #endif /* LINUX_BCMA_REGS_H_ */ |
| 1445 | --- a/drivers/net/wireless/b43/main.c |
| 1446 | +++ b/drivers/net/wireless/b43/main.c |
| 1447 | @@ -4622,7 +4622,7 @@ static int b43_wireless_core_init(struct |
| 1448 | switch (dev->dev->bus_type) { |
| 1449 | #ifdef CONFIG_B43_BCMA |
| 1450 | case B43_BUS_BCMA: |
| 1451 | - bcma_core_pci_irq_ctl(&dev->dev->bdev->bus->drv_pci, |
| 1452 | + bcma_core_pci_irq_ctl(&dev->dev->bdev->bus->drv_pci[0], |
| 1453 | dev->dev->bdev, true); |
| 1454 | break; |
| 1455 | #endif |
| 1456 | --- a/drivers/net/wireless/brcm80211/brcmsmac/aiutils.c |
| 1457 | +++ b/drivers/net/wireless/brcm80211/brcmsmac/aiutils.c |
| 1458 | @@ -695,7 +695,7 @@ void ai_pci_up(struct si_pub *sih) |
| 1459 | sii = container_of(sih, struct si_info, pub); |
| 1460 | |
| 1461 | if (sii->icbus->hosttype == BCMA_HOSTTYPE_PCI) |
| 1462 | - bcma_core_pci_extend_L1timer(&sii->icbus->drv_pci, true); |
| 1463 | + bcma_core_pci_extend_L1timer(&sii->icbus->drv_pci[0], true); |
| 1464 | } |
| 1465 | |
| 1466 | /* Unconfigure and/or apply various WARs when going down */ |
| 1467 | @@ -706,7 +706,7 @@ void ai_pci_down(struct si_pub *sih) |
| 1468 | sii = container_of(sih, struct si_info, pub); |
| 1469 | |
| 1470 | if (sii->icbus->hosttype == BCMA_HOSTTYPE_PCI) |
| 1471 | - bcma_core_pci_extend_L1timer(&sii->icbus->drv_pci, false); |
| 1472 | + bcma_core_pci_extend_L1timer(&sii->icbus->drv_pci[0], false); |
| 1473 | } |
| 1474 | |
| 1475 | /* Enable BT-COEX & Ex-PA for 4313 */ |
| 1476 | --- a/drivers/net/wireless/brcm80211/brcmsmac/main.c |
| 1477 | +++ b/drivers/net/wireless/brcm80211/brcmsmac/main.c |
| 1478 | @@ -5077,7 +5077,7 @@ static int brcms_b_up_prep(struct brcms_ |
| 1479 | * Configure pci/pcmcia here instead of in brcms_c_attach() |
| 1480 | * to allow mfg hotswap: down, hotswap (chip power cycle), up. |
| 1481 | */ |
| 1482 | - bcma_core_pci_irq_ctl(&wlc_hw->d11core->bus->drv_pci, wlc_hw->d11core, |
| 1483 | + bcma_core_pci_irq_ctl(&wlc_hw->d11core->bus->drv_pci[0], wlc_hw->d11core, |
| 1484 | true); |
| 1485 | |
| 1486 | /* |
| 1487 | |
