| 1 | From f2bbe41c507b475c6f0ae1fca69c7aac6d31d228 Mon Sep 17 00:00:00 2001 |
| 2 | From: John Crispin <blogic@openwrt.org> |
| 3 | Date: Fri, 9 Nov 2012 13:34:18 +0100 |
| 4 | Subject: [PATCH 4/6] MIPS: lantiq: adds xrx200 ethernet clock definition |
| 5 | |
| 6 | Signed-off-by: John Crispin <blogic@openwrt.org> |
| 7 | Patchwork: http://patchwork.linux-mips.org/patch/4521 |
| 8 | --- |
| 9 | arch/mips/lantiq/xway/sysctrl.c | 4 ++++ |
| 10 | 1 file changed, 4 insertions(+) |
| 11 | |
| 12 | diff --git a/arch/mips/lantiq/xway/sysctrl.c b/arch/mips/lantiq/xway/sysctrl.c |
| 13 | index 2917b56..3925e66 100644 |
| 14 | --- a/arch/mips/lantiq/xway/sysctrl.c |
| 15 | +++ b/arch/mips/lantiq/xway/sysctrl.c |
| 16 | @@ -370,6 +370,10 @@ void __init ltq_soc_init(void) |
| 17 | clkdev_add_pmu("1d900000.pcie", "pdi", 1, PMU1_PCIE_PDI); |
| 18 | clkdev_add_pmu("1d900000.pcie", "ctl", 1, PMU1_PCIE_CTL); |
| 19 | clkdev_add_pmu("1d900000.pcie", "ahb", 0, PMU_AHBM | PMU_AHBS); |
| 20 | + clkdev_add_pmu("1e108000.eth", NULL, 0, |
| 21 | + PMU_SWITCH | PMU_PPE_DPLUS | PMU_PPE_DPLUM | |
| 22 | + PMU_PPE_EMA | PMU_PPE_TC | PMU_PPE_SLL01 | |
| 23 | + PMU_PPE_QSB | PMU_PPE_TOP); |
| 24 | } else if (of_machine_is_compatible("lantiq,ar9")) { |
| 25 | clkdev_add_static(ltq_ar9_cpu_hz(), ltq_ar9_fpi_hz(), |
| 26 | ltq_ar9_fpi_hz()); |
| 27 | -- |
| 28 | 1.7.10.4 |
| 29 | |
| 30 | |
